1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Linux DHD Bus Module for PCIE
4 *
5 * Copyright (C) 1999-2019, Broadcom.
6 *
7 * Unless you and Broadcom execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2 (the "GPL"),
10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11 * following added to such license:
12 *
13 * As a special exception, the copyright holders of this software give you
14 * permission to link this software with independent modules, and to copy and
15 * distribute the resulting executable under terms of your choice, provided that
16 * you also meet, for each linked independent module, the terms and conditions of
17 * the license of that module. An independent module is a module which is not
18 * derived from this software. The special exception does not apply to any
19 * modifications of the software.
20 *
21 * Notwithstanding the above, under no circumstances may you combine this
22 * software in any way with any other Broadcom software provided under a license
23 * other than the GPL, without Broadcom's express prior written consent.
24 *
25 *
26 * <<Broadcom-WL-IPTag/Open:>>
27 *
28 * $Id: dhd_pcie.h 816392 2019-04-24 14:39:02Z $
29 */
30
31 #ifndef dhd_pcie_h
32 #define dhd_pcie_h
33
34 #include <bcmpcie.h>
35 #include <hnd_cons.h>
36 #include <dhd_linux.h>
37
38 /* defines */
39 #define PCIE_SHARED_VERSION PCIE_SHARED_VERSION_7
40
41 #define PCMSGBUF_HDRLEN 0
42 #define DONGLE_REG_MAP_SIZE (32 * 1024)
43 #define DONGLE_TCM_MAP_SIZE (4096 * 1024)
44 #define DONGLE_MIN_MEMSIZE (128 *1024)
45 #ifdef DHD_DEBUG
46 #define DHD_PCIE_SUCCESS 0
47 #define DHD_PCIE_FAILURE 1
48 #endif /* DHD_DEBUG */
49 #define REMAP_ENAB(bus) ((bus)->remap)
50 #define REMAP_ISADDR(bus, a) (((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
51
52 #define MAX_DHD_TX_FLOWS 320
53
54 /* user defined data structures */
55 /* Device console log buffer state */
56 #define CONSOLE_LINE_MAX 192u
57 #define CONSOLE_BUFFER_MAX (8 * 1024)
58
59 #ifdef IDLE_TX_FLOW_MGMT
60 #define IDLE_FLOW_LIST_TIMEOUT 5000
61 #define IDLE_FLOW_RING_TIMEOUT 5000
62 #endif /* IDLE_TX_FLOW_MGMT */
63
64 /* HWA enabled and inited */
65 #define HWA_ACTIVE(dhd) (((dhd)->hwa_enable) && ((dhd)->hwa_inited))
66
67 /* implicit DMA for h2d wr and d2h rd indice from Host memory to TCM */
68 #define IDMA_ENAB(dhd) ((dhd)->idma_enable)
69 #define IDMA_ACTIVE(dhd) (((dhd)->idma_enable) && ((dhd)->idma_inited))
70
71 #define IDMA_CAPABLE(bus) (((bus)->sih->buscorerev == 19) || ((bus)->sih->buscorerev >= 23))
72
73 /* IFRM (Implicit Flow Ring Manager enable and inited */
74 #define IFRM_ENAB(dhd) ((dhd)->ifrm_enable)
75 #define IFRM_ACTIVE(dhd) (((dhd)->ifrm_enable) && ((dhd)->ifrm_inited))
76
77 /* DAR registers use for h2d doorbell */
78 #define DAR_ENAB(dhd) ((dhd)->dar_enable)
79 #define DAR_ACTIVE(dhd) (((dhd)->dar_enable) && ((dhd)->dar_inited))
80
81 /* DAR WAR for revs < 64 */
82 #define DAR_PWRREQ(bus) (((bus)->_dar_war) && DAR_ACTIVE((bus)->dhd))
83
84 /* PCIE CTO Prevention and Recovery */
85 #define PCIECTO_ENAB(bus) ((bus)->cto_enable)
86
87 /* Implicit DMA index usage :
88 * Index 0 for h2d write index transfer
89 * Index 1 for d2h read index transfer
90 */
91 #define IDMA_IDX0 0
92 #define IDMA_IDX1 1
93 #define IDMA_IDX2 2
94 #define IDMA_IDX3 3
95 #define DMA_TYPE_SHIFT 4
96 #define DMA_TYPE_IDMA 1
97
98 #define DHDPCIE_CONFIG_HDR_SIZE 16
99 #define DHDPCIE_CONFIG_CHECK_DELAY_MS 10 /* 10ms */
100 #define DHDPCIE_CONFIG_CHECK_RETRY_COUNT 20
101 #define DHDPCIE_DONGLE_PWR_TOGGLE_DELAY 1000 /* 1ms in units of us */
102 #define DHDPCIE_PM_D3_DELAY 200000 /* 200ms in units of us */
103 #define DHDPCIE_PM_D2_DELAY 200 /* 200us */
104
105 typedef struct ring_sh_info {
106 uint32 ring_mem_addr;
107 uint32 ring_state_w;
108 uint32 ring_state_r;
109 } ring_sh_info_t;
110
111 #define DEVICE_WAKE_NONE 0
112 #define DEVICE_WAKE_OOB 1
113 #define DEVICE_WAKE_INB 2
114
115 #define INBAND_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_INB)
116 #define OOB_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_OOB)
117 #define NO_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_NONE)
118
119 #define PCIE_RELOAD_WAR_ENAB(buscorerev) \
120 ((buscorerev == 66) || (buscorerev == 67) || (buscorerev == 68) || (buscorerev == 70))
121
122 /*
123 * HW JIRA - CRWLPCIEGEN2-672
124 * Producer Index Feature which is used by F1 gets reset on F0 FLR
125 * fixed in REV68
126 */
127 #define PCIE_ENUM_RESET_WAR_ENAB(buscorerev) \
128 ((buscorerev == 66) || (buscorerev == 67))
129
130 struct dhd_bus;
131
132 struct dhd_pcie_rev {
133 uint8 fw_rev;
134 void (*handle_mb_data)(struct dhd_bus *);
135 };
136
137 typedef struct dhdpcie_config_save
138 {
139 uint32 header[DHDPCIE_CONFIG_HDR_SIZE];
140 /* pmcsr save */
141 uint32 pmcsr;
142 /* express save */
143 uint32 exp_dev_ctrl_stat;
144 uint32 exp_link_ctrl_stat;
145 uint32 exp_dev_ctrl_stat2;
146 uint32 exp_link_ctrl_stat2;
147 /* msi save */
148 uint32 msi_cap;
149 uint32 msi_addr0;
150 uint32 msi_addr1;
151 uint32 msi_data;
152 /* l1pm save */
153 uint32 l1pm0;
154 uint32 l1pm1;
155 /* ltr save */
156 uint32 ltr;
157 /* aer save */
158 uint32 aer_caps_ctrl; /* 0x18 */
159 uint32 aer_severity; /* 0x0C */
160 uint32 aer_umask; /* 0x08 */
161 uint32 aer_cmask; /* 0x14 */
162 uint32 aer_root_cmd; /* 0x2c */
163 /* BAR0 and BAR1 windows */
164 uint32 bar0_win;
165 uint32 bar1_win;
166 } dhdpcie_config_save_t;
167
168 /* The level of bus communication with the dongle */
169 enum dhd_bus_low_power_state {
170 DHD_BUS_NO_LOW_POWER_STATE, /* Not in low power state */
171 DHD_BUS_D3_INFORM_SENT, /* D3 INFORM sent */
172 DHD_BUS_D3_ACK_RECIEVED, /* D3 ACK recieved */
173 };
174
175 /** Instantiated once for each hardware (dongle) instance that this DHD manages */
176 typedef struct dhd_bus {
177 dhd_pub_t *dhd; /**< pointer to per hardware (dongle) unique instance */
178 struct pci_dev *rc_dev; /* pci RC device handle */
179 struct pci_dev *dev; /* pci device handle */
180
181 dll_t flowring_active_list; /* constructed list of tx flowring queues */
182 #ifdef IDLE_TX_FLOW_MGMT
183 uint64 active_list_last_process_ts;
184 /* stores the timestamp of active list processing */
185 #endif /* IDLE_TX_FLOW_MGMT */
186
187 si_t *sih; /* Handle for SI calls */
188 char *vars; /* Variables (from CIS and/or other) */
189 uint varsz; /* Size of variables buffer */
190 uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
191 sbpcieregs_t *reg; /* Registers for PCIE core */
192
193 uint armrev; /* CPU core revision */
194 uint coreid; /* CPU core id */
195 uint ramrev; /* SOCRAM core revision */
196 uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
197 uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
198 bool ramsize_adjusted; /* flag to note adjustment, so that
199 * adjustment routine and file io
200 * are avoided on D3 cold -> D0
201 */
202 uint32 srmemsize; /* Size of SRMEM */
203
204 uint32 bus; /* gSPI or SDIO bus */
205 uint32 bus_num; /* bus number */
206 uint32 slot_num; /* slot ID */
207 uint32 intstatus; /* Intstatus bits (events) pending */
208 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
209 bool fcstate; /* State of dongle flow-control */
210
211 uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
212 char *fw_path; /* module_param: path to firmware image */
213 char *nv_path; /* module_param: path to nvram vars file */
214
215 struct pktq txq; /* Queue length used for flow-control */
216
217 bool intr; /* Use interrupts */
218 bool poll; /* Use polling */
219 bool ipend; /* Device interrupt is pending */
220 bool intdis; /* Interrupts disabled by isr */
221 uint intrcount; /* Count of device interrupt callbacks */
222 uint lastintrs; /* Count as of last watchdog timer */
223
224 dhd_console_t console; /* Console output polling support */
225 uint console_addr; /* Console address from shared struct */
226
227 bool alp_only; /* Don't use HT clock (ALP only) */
228
229 bool remap; /* Contiguous 1MB RAM: 512K socram + 512K devram
230 * Available with socram rev 16
231 * Remap region not DMA-able
232 */
233 uint32 resetinstr;
234 uint32 dongle_ram_base;
235
236 ulong shared_addr;
237 pciedev_shared_t *pcie_sh;
238 uint32 dma_rxoffset;
239 volatile char *regs; /* pci device memory va */
240 volatile char *tcm; /* pci device memory va */
241 osl_t *osh;
242 uint32 nvram_csm; /* Nvram checksum */
243 uint16 pollrate;
244 uint16 polltick;
245
246 volatile uint32 *pcie_mb_intr_addr;
247 volatile uint32 *pcie_mb_intr_2_addr;
248 void *pcie_mb_intr_osh;
249 bool sleep_allowed;
250
251 wake_counts_t wake_counts;
252
253 /* version 3 shared struct related info start */
254 ring_sh_info_t ring_sh[BCMPCIE_COMMON_MSGRINGS + MAX_DHD_TX_FLOWS];
255
256 uint8 h2d_ring_count;
257 uint8 d2h_ring_count;
258 uint32 ringmem_ptr;
259 uint32 ring_state_ptr;
260
261 uint32 d2h_dma_scratch_buffer_mem_addr;
262
263 uint32 h2d_mb_data_ptr_addr;
264 uint32 d2h_mb_data_ptr_addr;
265 /* version 3 shared struct related info end */
266
267 uint32 def_intmask;
268 uint32 d2h_mb_mask;
269 uint32 pcie_mailbox_mask;
270 uint32 pcie_mailbox_int;
271 bool ltrsleep_on_unload;
272 uint wait_for_d3_ack;
273 uint16 max_tx_flowrings;
274 uint16 max_submission_rings;
275 uint16 max_completion_rings;
276 uint16 max_cmn_rings;
277 uint32 rw_index_sz;
278 bool db1_for_mb;
279
280 dhd_timeout_t doorbell_timer;
281 bool device_wake_state;
282 bool irq_registered;
283 bool d2h_intr_method;
284 int32 idletime; /* Control for activity timeout */
285 uint32 d3_inform_cnt;
286 uint32 d0_inform_cnt;
287 uint32 d0_inform_in_use_cnt;
288 uint8 force_suspend;
289 uint8 is_linkdown;
290 uint8 no_bus_init;
291 #ifdef IDLE_TX_FLOW_MGMT
292 bool enable_idle_flowring_mgmt;
293 #endif /* IDLE_TX_FLOW_MGMT */
294 struct dhd_pcie_rev api;
295 bool use_mailbox;
296 bool use_d0_inform;
297 void *bus_lock;
298 void *backplane_access_lock;
299 enum dhd_bus_low_power_state bus_low_power_state;
300 uint32 hostready_count; /* Number of hostready issued */
301 #if defined(BCMPCIE_OOB_HOST_WAKE)
302 bool oob_presuspend;
303 #endif // endif
304 dhdpcie_config_save_t saved_config;
305 ulong resume_intr_enable_count;
306 ulong dpc_intr_enable_count;
307 ulong isr_intr_disable_count;
308 ulong suspend_intr_disable_count;
309 ulong dpc_return_busdown_count;
310 ulong non_ours_irq_count;
311 #ifdef BCMPCIE_OOB_HOST_WAKE
312 ulong oob_intr_count;
313 ulong oob_intr_enable_count;
314 ulong oob_intr_disable_count;
315 uint64 last_oob_irq_time;
316 uint64 last_oob_irq_enable_time;
317 uint64 last_oob_irq_disable_time;
318 #endif /* BCMPCIE_OOB_HOST_WAKE */
319 uint64 isr_entry_time;
320 uint64 isr_exit_time;
321 uint64 dpc_sched_time;
322 uint64 dpc_entry_time;
323 uint64 dpc_exit_time;
324 uint64 resched_dpc_time;
325 uint64 last_d3_inform_time;
326 uint64 last_process_ctrlbuf_time;
327 uint64 last_process_flowring_time;
328 uint64 last_process_txcpl_time;
329 uint64 last_process_rxcpl_time;
330 uint64 last_process_infocpl_time;
331 uint64 last_process_edl_time;
332 uint64 last_suspend_start_time;
333 uint64 last_suspend_end_time;
334 uint64 last_resume_start_time;
335 uint64 last_resume_end_time;
336 uint64 last_non_ours_irq_time;
337 uint8 hwa_enab_bmap;
338 bool idma_enabled;
339 bool ifrm_enabled;
340 bool dar_enabled;
341 uint32 dmaxfer_complete;
342 uint8 dw_option;
343 bool _dar_war;
344 uint8 dma_chan;
345 bool cto_enable; /* enable PCIE CTO Prevention and recovery */
346 uint32 cto_threshold; /* PCIE CTO timeout threshold */
347 bool cto_triggered; /* CTO is triggered */
348 int pwr_req_ref;
349 bool flr_force_fail; /* user intends to simulate flr force fail */
350 bool intr_enabled; /* ready to receive interrupts from dongle */
351 bool force_bt_quiesce; /* send bt_quiesce command to BT driver. */
352 #if defined(DHD_H2D_LOG_TIME_SYNC)
353 ulong dhd_rte_time_sync_count; /* OSL_SYSUPTIME_US() */
354 #endif /* DHD_H2D_LOG_TIME_SYNC */
355 bool rc_ep_aspm_cap; /* RC and EP ASPM capable */
356 bool rc_ep_l1ss_cap; /* EC and EP L1SS capable */
357 uint16 hp2p_txcpl_max_items;
358 uint16 hp2p_rxcpl_max_items;
359 /* PCIE coherent status */
360 uint32 coherent_state;
361 } dhd_bus_t;
362
363 #ifdef DHD_MSI_SUPPORT
364 extern uint enable_msi;
365 #endif /* DHD_MSI_SUPPORT */
366
367 enum {
368 PCIE_INTX = 0,
369 PCIE_MSI = 1
370 };
371
372 /* function declarations */
373
374 extern uint32* dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size);
375 extern int dhdpcie_bus_register(void);
376 extern void dhdpcie_bus_unregister(void);
377 extern bool dhdpcie_chipmatch(uint16 vendor, uint16 device);
378
379 extern int dhdpcie_bus_attach(osl_t *osh, dhd_bus_t **bus_ptr,
380 volatile char *regs, volatile char *tcm, void *pci_dev, wifi_adapter_info_t *adapter);
381 extern uint32 dhdpcie_bus_cfg_read_dword(struct dhd_bus *bus, uint32 addr, uint32 size);
382 extern void dhdpcie_bus_cfg_write_dword(struct dhd_bus *bus, uint32 addr, uint32 size, uint32 data);
383 extern void dhdpcie_bus_intr_enable(struct dhd_bus *bus);
384 extern void dhdpcie_bus_intr_disable(struct dhd_bus *bus);
385 extern int dhpcie_bus_mask_interrupt(dhd_bus_t *bus);
386 extern void dhdpcie_bus_release(struct dhd_bus *bus);
387 extern int32 dhdpcie_bus_isr(struct dhd_bus *bus);
388 extern void dhdpcie_free_irq(dhd_bus_t *bus);
389 extern void dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value);
390 extern void dhdpcie_bus_ringbell_2_fast(struct dhd_bus *bus, uint32 value, bool devwake);
391 extern void dhdpcie_dongle_reset(dhd_bus_t *bus);
392 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
393 extern int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state, bool byint);
394 #else
395 extern int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state);
396 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
397 extern int dhdpcie_pci_suspend_resume(struct dhd_bus *bus, bool state);
398 extern uint32 dhdpcie_force_alp(struct dhd_bus *bus, bool enable);
399 extern uint32 dhdpcie_set_l1_entry_time(struct dhd_bus *bus, int force_l1_entry_time);
400 extern bool dhdpcie_tcm_valid(dhd_bus_t *bus);
401 extern void dhdpcie_pme_active(osl_t *osh, bool enable);
402 extern bool dhdpcie_pme_cap(osl_t *osh);
403 extern uint32 dhdpcie_lcreg(osl_t *osh, uint32 mask, uint32 val);
404 extern void dhdpcie_set_pmu_min_res_mask(struct dhd_bus *bus, uint min_res_mask);
405 extern uint8 dhdpcie_clkreq(osl_t *osh, uint32 mask, uint32 val);
406 extern int dhdpcie_disable_irq(dhd_bus_t *bus);
407 extern int dhdpcie_disable_irq_nosync(dhd_bus_t *bus);
408 extern int dhdpcie_enable_irq(dhd_bus_t *bus);
409
410 extern void dhd_bus_dump_dar_registers(struct dhd_bus *bus);
411
412 extern uint32 dhdpcie_rc_config_read(dhd_bus_t *bus, uint offset);
413 extern uint32 dhdpcie_rc_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext,
414 bool is_write, uint32 writeval);
415 extern uint32 dhdpcie_ep_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext,
416 bool is_write, uint32 writeval);
417 extern uint32 dhd_debug_get_rc_linkcap(dhd_bus_t *bus);
418 extern int dhdpcie_start_host_pcieclock(dhd_bus_t *bus);
419 extern int dhdpcie_stop_host_pcieclock(dhd_bus_t *bus);
420 extern int dhdpcie_disable_device(dhd_bus_t *bus);
421 extern int dhdpcie_alloc_resource(dhd_bus_t *bus);
422 extern void dhdpcie_free_resource(dhd_bus_t *bus);
423 extern void dhdpcie_dump_resource(dhd_bus_t *bus);
424 extern int dhdpcie_bus_request_irq(struct dhd_bus *bus);
425 void dhdpcie_os_setbar1win(dhd_bus_t *bus, uint32 addr);
426 void dhdpcie_os_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data);
427 uint8 dhdpcie_os_rtcm8(dhd_bus_t *bus, ulong offset);
428 void dhdpcie_os_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data);
429 uint16 dhdpcie_os_rtcm16(dhd_bus_t *bus, ulong offset);
430 void dhdpcie_os_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data);
431 uint32 dhdpcie_os_rtcm32(dhd_bus_t *bus, ulong offset);
432 #ifdef DHD_SUPPORT_64BIT
433 void dhdpcie_os_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data);
434 uint64 dhdpcie_os_rtcm64(dhd_bus_t *bus, ulong offset);
435 #endif // endif
436
437 extern int dhdpcie_enable_device(dhd_bus_t *bus);
438
439 #ifdef BCMPCIE_OOB_HOST_WAKE
440 extern int dhdpcie_oob_intr_register(dhd_bus_t *bus);
441 extern void dhdpcie_oob_intr_unregister(dhd_bus_t *bus);
442 extern void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable);
443 extern int dhdpcie_get_oob_irq_num(struct dhd_bus *bus);
444 extern int dhdpcie_get_oob_irq_status(struct dhd_bus *bus);
445 extern int dhdpcie_get_oob_irq_level(void);
446 #endif /* BCMPCIE_OOB_HOST_WAKE */
447
448 #if defined(CONFIG_ARCH_EXYNOS)
449 #define SAMSUNG_PCIE_VENDOR_ID 0x144d
450 #if defined(CONFIG_MACH_UNIVERSAL7420) || defined(CONFIG_SOC_EXYNOS7420)
451 #define SAMSUNG_PCIE_DEVICE_ID 0xa575
452 #define SAMSUNG_PCIE_CH_NUM 1
453 #elif defined(CONFIG_SOC_EXYNOS8890)
454 #define SAMSUNG_PCIE_DEVICE_ID 0xa544
455 #define SAMSUNG_PCIE_CH_NUM 0
456 #elif defined(CONFIG_SOC_EXYNOS8895) || defined(CONFIG_SOC_EXYNOS9810) || \
457 defined(CONFIG_SOC_EXYNOS9820)
458 #define SAMSUNG_PCIE_DEVICE_ID 0xecec
459 #define SAMSUNG_PCIE_CH_NUM 0
460 #else
461 #error "Not supported platform"
462 #endif /* CONFIG_SOC_EXYNOSXXXX & CONFIG_MACH_UNIVERSALXXXX */
463 #endif /* CONFIG_ARCH_EXYNOS */
464
465 #if defined(CONFIG_ARCH_MSM)
466 #define MSM_PCIE_VENDOR_ID 0x17cb
467 #if defined(CONFIG_ARCH_APQ8084)
468 #define MSM_PCIE_DEVICE_ID 0x0101
469 #elif defined(CONFIG_ARCH_MSM8994)
470 #define MSM_PCIE_DEVICE_ID 0x0300
471 #elif defined(CONFIG_ARCH_MSM8996)
472 #define MSM_PCIE_DEVICE_ID 0x0104
473 #elif defined(CONFIG_ARCH_MSM8998)
474 #define MSM_PCIE_DEVICE_ID 0x0105
475 #elif defined(CONFIG_ARCH_SDM845) || defined(CONFIG_ARCH_SM8150)
476 #define MSM_PCIE_DEVICE_ID 0x0106
477 #else
478 #error "Not supported platform"
479 #endif // endif
480 #endif /* CONFIG_ARCH_MSM */
481
482 #if defined(CONFIG_X86)
483 #define X86_PCIE_VENDOR_ID 0x8086
484 #define X86_PCIE_DEVICE_ID 0x9c1a
485 #endif /* CONFIG_X86 */
486
487 #if defined(CONFIG_ARCH_TEGRA)
488 #define TEGRA_PCIE_VENDOR_ID 0x14e4
489 #define TEGRA_PCIE_DEVICE_ID 0x4347
490 #endif /* CONFIG_ARCH_TEGRA */
491
492 #define HIKEY_PCIE_VENDOR_ID 0x19e5
493 #define HIKEY_PCIE_DEVICE_ID 0x3660
494
495 #define DUMMY_PCIE_VENDOR_ID 0xffff
496 #define DUMMY_PCIE_DEVICE_ID 0xffff
497
498 #if defined(CONFIG_ARCH_EXYNOS)
499 #define PCIE_RC_VENDOR_ID SAMSUNG_PCIE_VENDOR_ID
500 #define PCIE_RC_DEVICE_ID SAMSUNG_PCIE_DEVICE_ID
501 #elif defined(CONFIG_ARCH_MSM)
502 #define PCIE_RC_VENDOR_ID MSM_PCIE_VENDOR_ID
503 #define PCIE_RC_DEVICE_ID MSM_PCIE_DEVICE_ID
504 #elif defined(CONFIG_X86)
505 #define PCIE_RC_VENDOR_ID X86_PCIE_VENDOR_ID
506 #define PCIE_RC_DEVICE_ID X86_PCIE_DEVICE_ID
507 #elif defined(CONFIG_ARCH_TEGRA)
508 #define PCIE_RC_VENDOR_ID TEGRA_PCIE_VENDOR_ID
509 #define PCIE_RC_DEVICE_ID TEGRA_PCIE_DEVICE_ID
510 #else
511 #define PCIE_RC_VENDOR_ID HIKEY_PCIE_VENDOR_ID
512 #define PCIE_RC_DEVICE_ID HIKEY_PCIE_DEVICE_ID
513 #endif /* CONFIG_ARCH_EXYNOS */
514
515 #define DHD_REGULAR_RING 0
516 #define DHD_HP2P_RING 1
517
518 #ifdef USE_EXYNOS_PCIE_RC_PMPATCH
519 extern int exynos_pcie_pm_suspend(int ch_num);
520 extern int exynos_pcie_pm_resume(int ch_num);
521 #endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
522
523 #ifdef CONFIG_ARCH_TEGRA
524 extern int tegra_pcie_pm_suspend(void);
525 extern int tegra_pcie_pm_resume(void);
526 #endif /* CONFIG_ARCH_TEGRA */
527
528 extern int dhd_buzzz_dump_dngl(dhd_bus_t *bus);
529 #ifdef IDLE_TX_FLOW_MGMT
530 extern int dhd_bus_flow_ring_resume_request(struct dhd_bus *bus, void *arg);
531 extern void dhd_bus_flow_ring_resume_response(struct dhd_bus *bus, uint16 flowid, int32 status);
532 extern int dhd_bus_flow_ring_suspend_request(struct dhd_bus *bus, void *arg);
533 extern void dhd_bus_flow_ring_suspend_response(struct dhd_bus *bus, uint16 flowid, uint32 status);
534 extern void dhd_flow_ring_move_to_active_list_head(struct dhd_bus *bus,
535 flow_ring_node_t *flow_ring_node);
536 extern void dhd_flow_ring_add_to_active_list(struct dhd_bus *bus,
537 flow_ring_node_t *flow_ring_node);
538 extern void dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
539 flow_ring_node_t *flow_ring_node);
540 extern void __dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
541 flow_ring_node_t *flow_ring_node);
542 #endif /* IDLE_TX_FLOW_MGMT */
543
544 extern int dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data);
545
546 #ifdef DHD_WAKE_STATUS
547 int bcmpcie_get_total_wake(struct dhd_bus *bus);
548 int bcmpcie_set_get_wake(struct dhd_bus *bus, int flag);
549 #endif /* DHD_WAKE_STATUS */
550 extern bool dhdpcie_bus_get_pcie_hostready_supported(dhd_bus_t *bus);
551 extern void dhd_bus_hostready(struct dhd_bus *bus);
552 extern void dhdpcie_bus_enab_pcie_dw(dhd_bus_t *bus, uint8 dw_option);
553 extern int dhdpcie_irq_disabled(struct dhd_bus *bus);
554
dhdpcie_is_arm_halted(struct dhd_bus * bus)555 static INLINE bool dhdpcie_is_arm_halted(struct dhd_bus *bus) {return TRUE;}
dhd_os_wifi_platform_set_power(uint32 value)556 static INLINE int dhd_os_wifi_platform_set_power(uint32 value) {return BCME_OK; }
557 static INLINE void
dhdpcie_dongle_flr_or_pwr_toggle(dhd_bus_t * bus)558 dhdpcie_dongle_flr_or_pwr_toggle(dhd_bus_t *bus)
559 { return; }
560
561 int dhdpcie_config_check(dhd_bus_t *bus);
562 int dhdpcie_config_restore(dhd_bus_t *bus, bool restore_pmcsr);
563 int dhdpcie_config_save(dhd_bus_t *bus);
564 int dhdpcie_set_pwr_state(dhd_bus_t *bus, uint state);
565
566 extern bool dhdpcie_bus_get_pcie_hwa_supported(dhd_bus_t *bus);
567 extern bool dhdpcie_bus_get_pcie_idma_supported(dhd_bus_t *bus);
568 extern bool dhdpcie_bus_get_pcie_ifrm_supported(dhd_bus_t *bus);
569 extern bool dhdpcie_bus_get_pcie_dar_supported(dhd_bus_t *bus);
570
571 static INLINE uint32
dhd_pcie_config_read(osl_t * osh,uint offset,uint size)572 dhd_pcie_config_read(osl_t *osh, uint offset, uint size)
573 {
574 OSL_DELAY(100);
575 return OSL_PCI_READ_CONFIG(osh, offset, size);
576 }
577
578 static INLINE uint32
dhd_pcie_corereg_read(si_t * sih,uint val)579 dhd_pcie_corereg_read(si_t *sih, uint val)
580 {
581 OSL_DELAY(100);
582 si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, val);
583 return si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), 0, 0);
584 }
585
586 extern int dhdpcie_get_fwpath_otp(dhd_bus_t *bus, char *fw_path, char *nv_path,
587 char *clm_path, char *txcap_path);
588
589 extern int dhd_pcie_debug_info_dump(dhd_pub_t *dhd);
590 extern void dhd_pcie_intr_count_dump(dhd_pub_t *dhd);
591 extern void dhdpcie_bus_clear_intstatus(dhd_bus_t *bus);
592 #ifdef DHD_HP2P
593 extern uint16 dhd_bus_get_hp2p_ring_max_size(dhd_bus_t *bus, bool tx);
594 #endif // endif
595
596 #endif /* dhd_pcie_h */
597