1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 #ifndef __HDMI_REG_AON_H__ 19 #define __HDMI_REG_AON_H__ 20 21 typedef union { 22 struct { 23 unsigned int tx_hw_day : 8; /* [7:0] */ 24 unsigned int tx_hw_month : 8; /* [15:8] */ 25 unsigned int tx_hw_year : 16; /* [31:16] */ 26 } bits; 27 unsigned int u32; 28 } tx_hw_info; 29 30 typedef union { 31 struct { 32 unsigned int tx_reg_version : 8; /* [7:0] */ 33 unsigned int tx_drv_version : 8; /* [15:8] */ 34 unsigned int tx_rtl_version : 8; /* [23:16] */ 35 unsigned int rsv_0 : 8; /* [31:24] */ 36 } bits; 37 unsigned int u32; 38 } tx_hw_version; 39 40 typedef union { 41 struct { 42 unsigned int rsv_1 : 32; /* [31:0] */ 43 } bits; 44 unsigned int u32; 45 } tx_hw_feature; 46 47 typedef union { 48 struct { 49 unsigned int tx_aon_soft_arst_req : 1; /* [0] */ 50 unsigned int rsv_2 : 31; /* [31:1] */ 51 } bits; 52 unsigned int u32; 53 } tx_aon_rst_ctrl; 54 55 typedef union { 56 struct { 57 unsigned int hpd_fillter_en : 1; /* [0] */ 58 unsigned int hpd_override_en : 1; /* [1] */ 59 unsigned int hpd_polarity_ctl : 1; /* [2] */ 60 unsigned int hpd_soft_value : 1; /* [3] */ 61 unsigned int osc_div_cnt : 12; /* [15:4] */ 62 unsigned int rsv_3 : 16; /* [31:16] */ 63 } bits; 64 unsigned int u32; 65 } hotplug_st_cfg; 66 67 typedef union { 68 struct { 69 unsigned int hpd_high_reshold : 16; /* [15:0] */ 70 unsigned int hpd_low_reshold : 16; /* [31:16] */ 71 } bits; 72 unsigned int u32; 73 } hotplug_fillter_cfg; 74 75 typedef union { 76 struct { 77 unsigned int hotplug_state : 1; /* [0] */ 78 unsigned int phy_rx_sense : 1; /* [1] */ 79 unsigned int rsv_4 : 30; /* [31:2] */ 80 } bits; 81 unsigned int u32; 82 } tx_aon_state; 83 84 typedef union { 85 struct { 86 unsigned int aon_intr_mask0 : 1; /* [0] */ 87 unsigned int aon_intr_mask1 : 1; /* [1] */ 88 unsigned int rsv_5 : 1; /* [2] */ 89 unsigned int rsv_6 : 1; /* [3] */ 90 unsigned int aon_intr_mask4 : 1; /* [4] */ 91 unsigned int aon_intr_mask5 : 1; /* [5] */ 92 unsigned int aon_intr_mask6 : 1; /* [6] */ 93 unsigned int aon_intr_mask7 : 1; /* [7] */ 94 unsigned int aon_intr_mask8 : 1; /* [8] */ 95 unsigned int aon_intr_mask9 : 1; /* [9] */ 96 unsigned int aon_intr_mask10 : 1; /* [10] */ 97 unsigned int aon_intr_mask11 : 1; /* [11] */ 98 unsigned int aon_intr_mask12 : 1; /* [12] */ 99 unsigned int aon_intr_mask13 : 1; /* [13] */ 100 unsigned int rsv_7 : 18; /* [31:14] */ 101 } bits; 102 unsigned int u32; 103 } tx_aon_intr_mask; 104 105 typedef union { 106 struct { 107 unsigned int aon_intr_stat0 : 1; /* [0] */ 108 unsigned int aon_intr_stat1 : 1; /* [1] */ 109 unsigned int rsv_8 : 1; /* [2] */ 110 unsigned int rsv_9 : 1; /* [3] */ 111 unsigned int aon_intr_stat4 : 1; /* [4] */ 112 unsigned int aon_intr_stat5 : 1; /* [5] */ 113 unsigned int aon_intr_stat6 : 1; /* [6] */ 114 unsigned int aon_intr_stat7 : 1; /* [7] */ 115 unsigned int aon_intr_stat8 : 1; /* [8] */ 116 unsigned int aon_intr_stat9 : 1; /* [9] */ 117 unsigned int aon_intr_stat10 : 1; /* [10] */ 118 unsigned int aon_intr_stat11 : 1; /* [11] */ 119 unsigned int aon_intr_stat12 : 1; /* [12] */ 120 unsigned int aon_intr_stat13 : 1; /* [13] */ 121 unsigned int rsv_10 : 18; /* [31:14] */ 122 } bits; 123 unsigned int u32; 124 } tx_aon_intr_state; 125 126 typedef union { 127 struct { 128 unsigned int ddc_aon_access : 1; /* [0] */ 129 unsigned int dcc_man_en : 1; /* [1] */ 130 unsigned int rsv_11 : 2; /* [3:2] */ 131 unsigned int ddc_speed_cnt : 9; /* [12:4] */ 132 unsigned int rsv_12 : 19; /* [31:13] */ 133 } bits; 134 unsigned int u32; 135 } ddc_mst_ctrl; 136 137 typedef union { 138 struct { 139 unsigned int ddc_fifo_data_out : 8; /* [7:0] */ 140 unsigned int rsv_13 : 24; /* [31:8] */ 141 } bits; 142 unsigned int u32; 143 } ddc_fifo_rdata; 144 145 typedef union { 146 struct { 147 unsigned int ddc_fifo_data_in : 8; /* [7:0] */ 148 unsigned int rsv_14 : 24; /* [31:8] */ 149 } bits; 150 unsigned int u32; 151 } ddc_fifo_wdata; 152 153 typedef union { 154 struct { 155 unsigned int ddc_fifo_data_cnt : 5; /* [4:0] */ 156 unsigned int rsv_15 : 3; /* [7:5] */ 157 unsigned int ddc_data_out_cnt : 10; /* [17:8] */ 158 unsigned int rsv_16 : 14; /* [31:18] */ 159 } bits; 160 unsigned int u32; 161 } ddc_data_cnt; 162 163 typedef union { 164 struct { 165 unsigned int ddc_slave_addr : 8; /* [7:0] */ 166 unsigned int ddc_slave_offset : 8; /* [15:8] */ 167 unsigned int ddc_slave_seg : 8; /* [23:16] */ 168 unsigned int rsv_17 : 8; /* [31:24] */ 169 } bits; 170 unsigned int u32; 171 } ddc_slave_cfg; 172 173 typedef union { 174 struct { 175 unsigned int ddc_i2c_no_ack : 1; /* [0] */ 176 unsigned int ddc_i2c_bus_low : 1; /* [1] */ 177 unsigned int ddc_i2c_in_prog : 1; /* [2] */ 178 unsigned int ddc_fifo_wr_in_use : 1; /* [3] */ 179 unsigned int ddc_fifo_rd_in_use : 1; /* [4] */ 180 unsigned int ddc_fifo_empty : 1; /* [5] */ 181 unsigned int ddc_fifo_half_full : 1; /* [6] */ 182 unsigned int ddc_fifo_full : 1; /* [7] */ 183 unsigned int rsv_18 : 24; /* [31:8] */ 184 } bits; 185 unsigned int u32; 186 } ddc_mst_state; 187 188 typedef union { 189 struct { 190 unsigned int ddc_mst_cmd : 4; /* [3:0] */ 191 unsigned int rsv_19 : 28; /* [31:4] */ 192 } bits; 193 unsigned int u32; 194 } ddc_mst_cmd; 195 196 typedef union { 197 struct { 198 unsigned int ddc_scl_st : 1; /* [0] */ 199 unsigned int ddc_sda_st : 1; /* [1] */ 200 unsigned int ddc_scl_oen : 1; /* [2] */ 201 unsigned int ddc_sda_oen : 1; /* [3] */ 202 unsigned int rsv_20 : 28; /* [31:4] */ 203 } bits; 204 unsigned int u32; 205 } ddc_man_ctrl; 206 207 typedef union { 208 struct { 209 unsigned int ddc_clr_bus_low : 1; /* [0] */ 210 unsigned int ddc_clr_no_ack : 1; /* [1] */ 211 unsigned int rsv_21 : 30; /* [31:2] */ 212 } bits; 213 unsigned int u32; 214 } ddc_state_clr; 215 216 typedef struct { 217 volatile tx_hw_info hw_info; /* 4000 */ 218 volatile tx_hw_version tx_hw_vers; /* 4004 */ 219 volatile tx_hw_feature hw_feature; /* 4008 */ 220 unsigned int reserved_0[4]; /* 400C-4018 */ 221 volatile tx_aon_rst_ctrl aon_rst; /* 401C */ 222 volatile hotplug_st_cfg hpd_cfg; /* 4020 */ 223 volatile hotplug_fillter_cfg hpd_filt_cfg; /* 4024 */ 224 volatile tx_aon_state aon_state; /* 4028 */ 225 unsigned int reserved_2[1]; /* 402C */ 226 volatile tx_aon_intr_mask aon_irq_mask; /* 4030 */ 227 volatile tx_aon_intr_state aon_irq_state; /* 4034 */ 228 unsigned int reserved_3[2]; /* 4038-403C */ 229 volatile ddc_mst_ctrl ddc_ctrl; /* 4040 */ 230 volatile ddc_fifo_rdata ddc_rdata; /* 4044 */ 231 volatile ddc_fifo_wdata ddc_wdata; /* 4048 */ 232 volatile ddc_data_cnt data_count; /* 404C */ 233 volatile ddc_slave_cfg slave_cfg; /* 4050 */ 234 volatile ddc_mst_state mst_state; /* 4054 */ 235 volatile ddc_mst_cmd mst_cmd; /* 4058 */ 236 volatile ddc_man_ctrl ddc_sw_ctrl; /* 405C */ 237 volatile ddc_state_clr state_clr; /* 4060 */ 238 } tx_aon_regs; 239 240 int hdmi_reg_aon_regs_init(char *addr); 241 int hdmi_reg_aon_regs_deinit(void); 242 int hdmi_reg_aon_intr_mask0_set(unsigned int aon_intr_mask0); 243 int hdmi_reg_aon_intr_stat0_set(unsigned int aon_intr_stat0); 244 int hdmi_reg_aon_intr_stat1_set(unsigned int aon_intr_stat1); 245 int hdmi_reg_dcc_man_en_set(unsigned int dcc_man_en); 246 int hdmi_reg_ddc_scl_oen_set(unsigned int ddc_scl_oen); 247 int hdmi_reg_ddc_sda_oen_set(unsigned int ddc_sda_oen); 248 int hdmi_reg_ddc_i2c_bus_low_get(void); 249 int hdmi_reg_ddc_i2c_no_ack_get(void); 250 int hdmi_reg_hpd_polarity_ctl_get(void); 251 int hdmi_reg_hotplug_state_get(void); 252 int hdmi_reg_phy_rx_sense_get(void); 253 int hdmi_reg_aon_intr_stat0_get(void); 254 int hdmi_reg_aon_intr_stat1_get(void); 255 int hdmi_reg_ddc_scl_st_get(void); 256 int hdmi_reg_ddc_sda_st_get(void); 257 258 #endif /* __HDMI_REG_AON_H__ */ 259 260