1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Broadcom BCMSDH to gSPI Protocol Conversion Layer
4 *
5 * Copyright (C) 1999-2019, Broadcom.
6 *
7 * Unless you and Broadcom execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2 (the "GPL"),
10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11 * following added to such license:
12 *
13 * As a special exception, the copyright holders of this software give you
14 * permission to link this software with independent modules, and to copy and
15 * distribute the resulting executable under terms of your choice, provided that
16 * you also meet, for each linked independent module, the terms and conditions of
17 * the license of that module. An independent module is a module which is not
18 * derived from this software. The special exception does not apply to any
19 * modifications of the software.
20 *
21 * Notwithstanding the above, under no circumstances may you combine this
22 * software in any way with any other Broadcom software provided under a license
23 * other than the GPL, without Broadcom's express prior written consent.
24 *
25 *
26 * <<Broadcom-WL-IPTag/Open:>>
27 *
28 * $Id: bcmspibrcm.c 700323 2017-05-18 16:12:11Z $
29 */
30
31 #define HSMODE
32
33 #include <typedefs.h>
34
35 #include <bcmdevs.h>
36 #include <bcmendian.h>
37 #include <bcmutils.h>
38 #include <osl.h>
39 #include <hndsoc.h>
40 #include <siutils.h>
41 #include <sbchipc.h>
42 #include <sbsdio.h> /* SDIO device core hardware definitions. */
43 #include <spid.h>
44
45 #include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
46 #include <sdiovar.h> /* ioctl/iovars */
47 #include <sdio.h> /* SDIO Device and Protocol Specs */
48
49 #include <pcicfg.h>
50
51 #include <bcmspibrcm.h>
52 #ifdef BCMSPI_ANDROID
53 extern void spi_sendrecv(sdioh_info_t *sd, uint8 *msg_out, uint8 *msg_in, int msglen);
54 #else
55 #include <bcmspi.h>
56 #endif /* BCMSPI_ANDROID */
57
58 /* these are for the older cores... for newer cores we have control for each of them */
59 #define F0_RESPONSE_DELAY 16
60 #define F1_RESPONSE_DELAY 16
61 #define F2_RESPONSE_DELAY F0_RESPONSE_DELAY
62
63 #define GSPI_F0_RESP_DELAY 0
64 #define GSPI_F1_RESP_DELAY F1_RESPONSE_DELAY
65 #define GSPI_F2_RESP_DELAY 0
66 #define GSPI_F3_RESP_DELAY 0
67
68 #define CMDLEN 4
69
70 /* Globals */
71 #if defined(DHD_DEBUG)
72 uint sd_msglevel = SDH_ERROR_VAL;
73 #else
74 uint sd_msglevel = 0;
75 #endif // endif
76
77 uint sd_hiok = FALSE; /* Use hi-speed mode if available? */
78 uint sd_sdmode = SDIOH_MODE_SPI; /* Use SD4 mode by default */
79 uint sd_f2_blocksize = 64; /* Default blocksize */
80
81 uint sd_divisor = 2;
82 uint sd_power = 1; /* Default to SD Slot powered ON */
83 uint sd_clock = 1; /* Default to SD Clock turned ON */
84 uint sd_crc = 0; /* Default to SPI CRC Check turned OFF */
85 uint sd_pci_slot = 0xFFFFffff; /* Used to force selection of a particular PCI slot */
86
87 uint8 spi_outbuf[SPI_MAX_PKT_LEN];
88 uint8 spi_inbuf[SPI_MAX_PKT_LEN];
89
90 /* 128bytes buffer is enough to clear data-not-available and program response-delay F0 bits
91 * assuming we will not exceed F0 response delay > 100 bytes at 48MHz.
92 */
93 #define BUF2_PKT_LEN 128
94 uint8 spi_outbuf2[BUF2_PKT_LEN];
95 uint8 spi_inbuf2[BUF2_PKT_LEN];
96 #ifdef BCMSPI_ANDROID
97 uint *dhd_spi_lockcount = NULL;
98 #endif /* BCMSPI_ANDROID */
99
100 #if !(defined(SPI_PIO_RW_BIGENDIAN) && defined(SPI_PIO_32BIT_RW))
101 #define SPISWAP_WD4(x) bcmswap32(x);
102 #define SPISWAP_WD2(x) (bcmswap16(x & 0xffff)) | \
103 (bcmswap16((x & 0xffff0000) >> 16) << 16);
104 #else
105 #define SPISWAP_WD4(x) x;
106 #define SPISWAP_WD2(x) bcmswap32by16(x);
107 #endif // endif
108
109 /* Prototypes */
110 static bool bcmspi_test_card(sdioh_info_t *sd);
111 static bool bcmspi_host_device_init_adapt(sdioh_info_t *sd);
112 static int bcmspi_set_highspeed_mode(sdioh_info_t *sd, bool hsmode);
113 static int bcmspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd_arg,
114 uint32 *data, uint32 datalen);
115 static int bcmspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr,
116 int regsize, uint32 *data);
117 static int bcmspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr,
118 int regsize, uint32 data);
119 static int bcmspi_card_bytewrite(sdioh_info_t *sd, int func, uint32 regaddr,
120 uint8 *data);
121 static int bcmspi_driver_init(sdioh_info_t *sd);
122 static int bcmspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
123 uint32 addr, int nbytes, uint32 *data);
124 static int bcmspi_card_regread_fixedaddr(sdioh_info_t *sd, int func, uint32 regaddr, int regsize,
125 uint32 *data);
126 static void bcmspi_cmd_getdstatus(sdioh_info_t *sd, uint32 *dstatus_buffer);
127 static int bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg);
128
129 /*
130 * Public entry points & extern's
131 */
132 extern sdioh_info_t *
sdioh_attach(osl_t * osh,void * bar0,uint irq)133 sdioh_attach(osl_t *osh, void *bar0, uint irq)
134 {
135 sdioh_info_t *sd;
136
137 sd_trace(("%s\n", __FUNCTION__));
138 if ((sd = (sdioh_info_t *)MALLOC(osh, sizeof(sdioh_info_t))) == NULL) {
139 sd_err(("%s: out of memory, malloced %d bytes\n", __FUNCTION__, MALLOCED(osh)));
140 return NULL;
141 }
142 bzero((char *)sd, sizeof(sdioh_info_t));
143 sd->osh = osh;
144 if (spi_osinit(sd) != 0) {
145 sd_err(("%s: spi_osinit() failed\n", __FUNCTION__));
146 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
147 return NULL;
148 }
149
150 #ifndef BCMSPI_ANDROID
151 sd->bar0 = bar0;
152 #endif /* !BCMSPI_ANDROID */
153 sd->irq = irq;
154 #ifndef BCMSPI_ANDROID
155 sd->intr_handler = NULL;
156 sd->intr_handler_arg = NULL;
157 sd->intr_handler_valid = FALSE;
158 #endif /* !BCMSPI_ANDROID */
159
160 /* Set defaults */
161 sd->use_client_ints = TRUE;
162 sd->sd_use_dma = FALSE; /* DMA Not supported */
163
164 /* Spi device default is 16bit mode, change to 4 when device is changed to 32bit
165 * mode
166 */
167 sd->wordlen = 2;
168
169 #ifdef BCMSPI_ANDROID
170 dhd_spi_lockcount = &sd->lockcount;
171 #endif /* BCMSPI_ANDROID */
172
173 #ifndef BCMSPI_ANDROID
174 if (!spi_hw_attach(sd)) {
175 sd_err(("%s: spi_hw_attach() failed\n", __FUNCTION__));
176 spi_osfree(sd);
177 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
178 return (NULL);
179 }
180 #endif /* !BCMSPI_ANDROID */
181
182 if (bcmspi_driver_init(sd) != SUCCESS) {
183 sd_err(("%s: bcmspi_driver_init() failed()\n", __FUNCTION__));
184 #ifndef BCMSPI_ANDROID
185 spi_hw_detach(sd);
186 #endif /* !BCMSPI_ANDROID */
187 spi_osfree(sd);
188 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
189 return (NULL);
190 }
191
192 if (spi_register_irq(sd, irq) != SUCCESS) {
193 sd_err(("%s: spi_register_irq() failed for irq = %d\n", __FUNCTION__, irq));
194 #ifndef BCMSPI_ANDROID
195 spi_hw_detach(sd);
196 #endif /* !BCMSPI_ANDROID */
197 spi_osfree(sd);
198 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
199 return (NULL);
200 }
201
202 sd_trace(("%s: Done\n", __FUNCTION__));
203
204 return sd;
205 }
206
207 extern SDIOH_API_RC
sdioh_detach(osl_t * osh,sdioh_info_t * sd)208 sdioh_detach(osl_t *osh, sdioh_info_t *sd)
209 {
210 sd_trace(("%s\n", __FUNCTION__));
211 if (sd) {
212 sd_err(("%s: detaching from hardware\n", __FUNCTION__));
213 spi_free_irq(sd->irq, sd);
214 #ifndef BCMSPI_ANDROID
215 spi_hw_detach(sd);
216 #endif /* !BCMSPI_ANDROID */
217 spi_osfree(sd);
218 #ifdef BCMSPI_ANDROID
219 dhd_spi_lockcount = NULL;
220 #endif /* !BCMSPI_ANDROID */
221 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
222 }
223 return SDIOH_API_RC_SUCCESS;
224 }
225
226 /* Configure callback to client when we recieve client interrupt */
227 extern SDIOH_API_RC
sdioh_interrupt_register(sdioh_info_t * sd,sdioh_cb_fn_t fn,void * argh)228 sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
229 {
230 sd_trace(("%s: Entering\n", __FUNCTION__));
231 #if !defined(OOB_INTR_ONLY)
232 sd->intr_handler = fn;
233 sd->intr_handler_arg = argh;
234 sd->intr_handler_valid = TRUE;
235 #endif /* !defined(OOB_INTR_ONLY) */
236 return SDIOH_API_RC_SUCCESS;
237 }
238
239 extern SDIOH_API_RC
sdioh_interrupt_deregister(sdioh_info_t * sd)240 sdioh_interrupt_deregister(sdioh_info_t *sd)
241 {
242 sd_trace(("%s: Entering\n", __FUNCTION__));
243 #if !defined(OOB_INTR_ONLY)
244 sd->intr_handler_valid = FALSE;
245 sd->intr_handler = NULL;
246 sd->intr_handler_arg = NULL;
247 #endif /* !defined(OOB_INTR_ONLY) */
248 return SDIOH_API_RC_SUCCESS;
249 }
250
251 extern SDIOH_API_RC
sdioh_interrupt_query(sdioh_info_t * sd,bool * onoff)252 sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
253 {
254 #ifndef BCMSPI_ANDROID
255 sd_trace(("%s: Entering\n", __FUNCTION__));
256 *onoff = sd->client_intr_enabled;
257 #endif /* !BCMSPI_ANDROID */
258 return SDIOH_API_RC_SUCCESS;
259 }
260
261 #if defined(DHD_DEBUG)
262 extern bool
sdioh_interrupt_pending(sdioh_info_t * sd)263 sdioh_interrupt_pending(sdioh_info_t *sd)
264 {
265 return 0;
266 }
267 #endif // endif
268
269 /* Provide dstatus bits of spi-transaction for dhd layers. */
270 extern uint32
sdioh_get_dstatus(sdioh_info_t * sd)271 sdioh_get_dstatus(sdioh_info_t *sd)
272 {
273 return sd->card_dstatus;
274 }
275
276 extern void
sdioh_chipinfo(sdioh_info_t * sd,uint32 chip,uint32 chiprev)277 sdioh_chipinfo(sdioh_info_t *sd, uint32 chip, uint32 chiprev)
278 {
279 sd->chip = chip;
280 sd->chiprev = chiprev;
281 }
282
283 extern void
sdioh_dwordmode(sdioh_info_t * sd,bool set)284 sdioh_dwordmode(sdioh_info_t *sd, bool set)
285 {
286 uint8 reg = 0;
287 int status;
288
289 if ((status = sdioh_request_byte(sd, SDIOH_READ, SPI_FUNC_0, SPID_STATUS_ENABLE, ®)) !=
290 SUCCESS) {
291 sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
292 return;
293 }
294
295 if (set) {
296 reg |= DWORD_PKT_LEN_EN;
297 sd->dwordmode = TRUE;
298 sd->client_block_size[SPI_FUNC_2] = 4096; /* h2spi's limit is 4KB, we support 8KB */
299 } else {
300 reg &= ~DWORD_PKT_LEN_EN;
301 sd->dwordmode = FALSE;
302 sd->client_block_size[SPI_FUNC_2] = 2048;
303 }
304
305 if ((status = sdioh_request_byte(sd, SDIOH_WRITE, SPI_FUNC_0, SPID_STATUS_ENABLE, ®)) !=
306 SUCCESS) {
307 sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
308 return;
309 }
310 }
311
312 uint
sdioh_query_iofnum(sdioh_info_t * sd)313 sdioh_query_iofnum(sdioh_info_t *sd)
314 {
315 return sd->num_funcs;
316 }
317
318 /* IOVar table */
319 enum {
320 IOV_MSGLEVEL = 1,
321 IOV_BLOCKMODE,
322 IOV_BLOCKSIZE,
323 IOV_DMA,
324 IOV_USEINTS,
325 IOV_NUMINTS,
326 IOV_NUMLOCALINTS,
327 IOV_HOSTREG,
328 IOV_DEVREG,
329 IOV_DIVISOR,
330 IOV_SDMODE,
331 IOV_HISPEED,
332 IOV_HCIREGS,
333 IOV_POWER,
334 IOV_CLOCK,
335 IOV_SPIERRSTATS,
336 IOV_RESP_DELAY_ALL
337 };
338
339 const bcm_iovar_t sdioh_iovars[] = {
340 {"sd_msglevel", IOV_MSGLEVEL, 0, IOVT_UINT32, 0 },
341 {"sd_blocksize", IOV_BLOCKSIZE, 0, IOVT_UINT32, 0 }, /* ((fn << 16) | size) */
342 {"sd_dma", IOV_DMA, 0, IOVT_BOOL, 0 },
343 {"sd_ints", IOV_USEINTS, 0, IOVT_BOOL, 0 },
344 {"sd_numints", IOV_NUMINTS, 0, IOVT_UINT32, 0 },
345 {"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32, 0 },
346 {"sd_hostreg", IOV_HOSTREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
347 {"sd_devreg", IOV_DEVREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
348 {"sd_divisor", IOV_DIVISOR, 0, IOVT_UINT32, 0 },
349 {"sd_power", IOV_POWER, 0, IOVT_UINT32, 0 },
350 {"sd_clock", IOV_CLOCK, 0, IOVT_UINT32, 0 },
351 {"sd_mode", IOV_SDMODE, 0, IOVT_UINT32, 100},
352 {"sd_highspeed", IOV_HISPEED, 0, IOVT_UINT32, 0},
353 {"spi_errstats", IOV_SPIERRSTATS, 0, IOVT_BUFFER, sizeof(struct spierrstats_t) },
354 {"spi_respdelay", IOV_RESP_DELAY_ALL, 0, IOVT_BOOL, 0 },
355 {NULL, 0, 0, 0, 0 }
356 };
357
358 int
sdioh_iovar_op(sdioh_info_t * si,const char * name,void * params,int plen,void * arg,int len,bool set)359 sdioh_iovar_op(sdioh_info_t *si, const char *name,
360 void *params, int plen, void *arg, int len, bool set)
361 {
362 const bcm_iovar_t *vi = NULL;
363 int bcmerror = 0;
364 int val_size;
365 int32 int_val = 0;
366 bool bool_val;
367 uint32 actionid;
368 /*
369 sdioh_regs_t *regs;
370 */
371
372 ASSERT(name);
373 ASSERT(len >= 0);
374
375 /* Get must have return space; Set does not take qualifiers */
376 ASSERT(set || (arg && len));
377 ASSERT(!set || (!params && !plen));
378
379 sd_trace(("%s: Enter (%s %s)\n", __FUNCTION__, (set ? "set" : "get"), name));
380
381 if ((vi = bcm_iovar_lookup(sdioh_iovars, name)) == NULL) {
382 bcmerror = BCME_UNSUPPORTED;
383 goto exit;
384 }
385
386 if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, set)) != 0)
387 goto exit;
388
389 /* Set up params so get and set can share the convenience variables */
390 if (params == NULL) {
391 params = arg;
392 plen = len;
393 }
394
395 if (vi->type == IOVT_VOID)
396 val_size = 0;
397 else if (vi->type == IOVT_BUFFER)
398 val_size = len;
399 else
400 val_size = sizeof(int);
401
402 if (plen >= (int)sizeof(int_val))
403 bcopy(params, &int_val, sizeof(int_val));
404
405 bool_val = (int_val != 0) ? TRUE : FALSE;
406
407 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
408 switch (actionid) {
409 case IOV_GVAL(IOV_MSGLEVEL):
410 int_val = (int32)sd_msglevel;
411 bcopy(&int_val, arg, val_size);
412 break;
413
414 case IOV_SVAL(IOV_MSGLEVEL):
415 sd_msglevel = int_val;
416 break;
417
418 case IOV_GVAL(IOV_BLOCKSIZE):
419 if ((uint32)int_val > si->num_funcs) {
420 bcmerror = BCME_BADARG;
421 break;
422 }
423 int_val = (int32)si->client_block_size[int_val];
424 bcopy(&int_val, arg, val_size);
425 break;
426
427 case IOV_GVAL(IOV_DMA):
428 int_val = (int32)si->sd_use_dma;
429 bcopy(&int_val, arg, val_size);
430 break;
431
432 case IOV_SVAL(IOV_DMA):
433 si->sd_use_dma = (bool)int_val;
434 break;
435
436 case IOV_GVAL(IOV_USEINTS):
437 int_val = (int32)si->use_client_ints;
438 bcopy(&int_val, arg, val_size);
439 break;
440
441 case IOV_SVAL(IOV_USEINTS):
442 break;
443
444 case IOV_GVAL(IOV_DIVISOR):
445 int_val = (uint32)sd_divisor;
446 bcopy(&int_val, arg, val_size);
447 break;
448
449 #ifndef BCMSPI_ANDROID
450 case IOV_SVAL(IOV_DIVISOR):
451 sd_divisor = int_val;
452 if (!spi_start_clock(si, (uint16)sd_divisor)) {
453 sd_err(("%s: set clock failed\n", __FUNCTION__));
454 bcmerror = BCME_ERROR;
455 }
456 break;
457 #endif /* !BCMSPI_ANDROID */
458
459 case IOV_GVAL(IOV_POWER):
460 int_val = (uint32)sd_power;
461 bcopy(&int_val, arg, val_size);
462 break;
463
464 case IOV_SVAL(IOV_POWER):
465 sd_power = int_val;
466 break;
467
468 case IOV_GVAL(IOV_CLOCK):
469 int_val = (uint32)sd_clock;
470 bcopy(&int_val, arg, val_size);
471 break;
472
473 case IOV_SVAL(IOV_CLOCK):
474 sd_clock = int_val;
475 break;
476
477 case IOV_GVAL(IOV_SDMODE):
478 int_val = (uint32)sd_sdmode;
479 bcopy(&int_val, arg, val_size);
480 break;
481
482 case IOV_SVAL(IOV_SDMODE):
483 sd_sdmode = int_val;
484 break;
485
486 case IOV_GVAL(IOV_HISPEED):
487 int_val = (uint32)sd_hiok;
488 bcopy(&int_val, arg, val_size);
489 break;
490
491 case IOV_SVAL(IOV_HISPEED):
492 sd_hiok = int_val;
493
494 if (!bcmspi_set_highspeed_mode(si, (bool)sd_hiok)) {
495 sd_err(("%s: Failed changing highspeed mode to %d.\n",
496 __FUNCTION__, sd_hiok));
497 bcmerror = BCME_ERROR;
498 return ERROR;
499 }
500 break;
501
502 case IOV_GVAL(IOV_NUMINTS):
503 int_val = (int32)si->intrcount;
504 bcopy(&int_val, arg, val_size);
505 break;
506
507 case IOV_GVAL(IOV_NUMLOCALINTS):
508 int_val = (int32)si->local_intrcount;
509 bcopy(&int_val, arg, val_size);
510 break;
511 case IOV_GVAL(IOV_DEVREG):
512 {
513 sdreg_t *sd_ptr = (sdreg_t *)params;
514 uint8 data;
515
516 if (sdioh_cfg_read(si, sd_ptr->func, sd_ptr->offset, &data)) {
517 bcmerror = BCME_SDIO_ERROR;
518 break;
519 }
520
521 int_val = (int)data;
522 bcopy(&int_val, arg, sizeof(int_val));
523 break;
524 }
525
526 case IOV_SVAL(IOV_DEVREG):
527 {
528 sdreg_t *sd_ptr = (sdreg_t *)params;
529 uint8 data = (uint8)sd_ptr->value;
530
531 if (sdioh_cfg_write(si, sd_ptr->func, sd_ptr->offset, &data)) {
532 bcmerror = BCME_SDIO_ERROR;
533 break;
534 }
535 break;
536 }
537
538 case IOV_GVAL(IOV_SPIERRSTATS):
539 {
540 bcopy(&si->spierrstats, arg, sizeof(struct spierrstats_t));
541 break;
542 }
543
544 case IOV_SVAL(IOV_SPIERRSTATS):
545 {
546 bzero(&si->spierrstats, sizeof(struct spierrstats_t));
547 break;
548 }
549
550 case IOV_GVAL(IOV_RESP_DELAY_ALL):
551 int_val = (int32)si->resp_delay_all;
552 bcopy(&int_val, arg, val_size);
553 break;
554
555 case IOV_SVAL(IOV_RESP_DELAY_ALL):
556 si->resp_delay_all = (bool)int_val;
557 int_val = STATUS_ENABLE|INTR_WITH_STATUS;
558 if (si->resp_delay_all)
559 int_val |= RESP_DELAY_ALL;
560 else {
561 if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_RESPONSE_DELAY, 1,
562 F1_RESPONSE_DELAY) != SUCCESS) {
563 sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
564 bcmerror = BCME_SDIO_ERROR;
565 break;
566 }
567 }
568
569 if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_STATUS_ENABLE, 1, int_val)
570 != SUCCESS) {
571 sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
572 bcmerror = BCME_SDIO_ERROR;
573 break;
574 }
575 break;
576
577 default:
578 bcmerror = BCME_UNSUPPORTED;
579 break;
580 }
581 exit:
582
583 return bcmerror;
584 }
585
586 extern SDIOH_API_RC
sdioh_cfg_read(sdioh_info_t * sd,uint fnc_num,uint32 addr,uint8 * data)587 sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
588 {
589 SDIOH_API_RC status;
590 /* No lock needed since sdioh_request_byte does locking */
591 status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
592 return status;
593 }
594
595 extern SDIOH_API_RC
sdioh_cfg_write(sdioh_info_t * sd,uint fnc_num,uint32 addr,uint8 * data)596 sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
597 {
598 /* No lock needed since sdioh_request_byte does locking */
599 SDIOH_API_RC status;
600
601 if ((fnc_num == SPI_FUNC_1) && (addr == SBSDIO_FUNC1_FRAMECTRL)) {
602 uint8 dummy_data;
603 status = sdioh_cfg_read(sd, fnc_num, addr, &dummy_data);
604 if (status) {
605 sd_err(("sdioh_cfg_read() failed.\n"));
606 return status;
607 }
608 }
609
610 status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
611 return status;
612 }
613
614 extern SDIOH_API_RC
sdioh_cis_read(sdioh_info_t * sd,uint func,uint8 * cisd,uint32 length)615 sdioh_cis_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 length)
616 {
617 uint32 count;
618 int offset;
619 uint32 cis_byte;
620 uint16 *cis = (uint16 *)cisd;
621 uint bar0 = SI_ENUM_BASE(sd->sih);
622 int status;
623 uint8 data;
624
625 sd_trace(("%s: Func %d\n", __FUNCTION__, func));
626
627 spi_lock(sd);
628
629 /* Set sb window address to 0x18000000 */
630 data = (bar0 >> 8) & SBSDIO_SBADDRLOW_MASK;
631 status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW, &data);
632 if (status == SUCCESS) {
633 data = (bar0 >> 16) & SBSDIO_SBADDRMID_MASK;
634 status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID, &data);
635 } else {
636 sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
637 spi_unlock(sd);
638 return (BCME_ERROR);
639 }
640 if (status == SUCCESS) {
641 data = (bar0 >> 24) & SBSDIO_SBADDRHIGH_MASK;
642 status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH, &data);
643 } else {
644 sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
645 spi_unlock(sd);
646 return (BCME_ERROR);
647 }
648
649 offset = CC_SROM_OTP; /* OTP offset in chipcommon. */
650 for (count = 0; count < length/2; count++) {
651 if (bcmspi_card_regread (sd, SDIO_FUNC_1, offset, 2, &cis_byte) < 0) {
652 sd_err(("%s: regread failed: Can't read CIS\n", __FUNCTION__));
653 spi_unlock(sd);
654 return (BCME_ERROR);
655 }
656
657 *cis = (uint16)cis_byte;
658 cis++;
659 offset += 2;
660 }
661
662 spi_unlock(sd);
663
664 return (BCME_OK);
665 }
666
667 extern SDIOH_API_RC
sdioh_request_byte(sdioh_info_t * sd,uint rw,uint func,uint regaddr,uint8 * byte)668 sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr, uint8 *byte)
669 {
670 int status;
671 uint32 cmd_arg;
672 uint32 dstatus;
673 uint32 data = (uint32)(*byte);
674
675 spi_lock(sd);
676
677 cmd_arg = 0;
678 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
679 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
680 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
681 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, rw == SDIOH_READ ? 0 : 1);
682 cmd_arg = SFIELD(cmd_arg, SPI_LEN, 1);
683
684 if (rw == SDIOH_READ) {
685 sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x\n",
686 __FUNCTION__, cmd_arg, func, regaddr));
687 } else {
688 sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x data=0x%x\n",
689 __FUNCTION__, cmd_arg, func, regaddr, data));
690 }
691
692 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, 1)) != SUCCESS) {
693 spi_unlock(sd);
694 return status;
695 }
696
697 if (rw == SDIOH_READ) {
698 *byte = (uint8)data;
699 sd_trace(("%s: RD result=0x%x\n", __FUNCTION__, *byte));
700 }
701
702 bcmspi_cmd_getdstatus(sd, &dstatus);
703 if (dstatus)
704 sd_trace(("dstatus=0x%x\n", dstatus));
705
706 spi_unlock(sd);
707 return SDIOH_API_RC_SUCCESS;
708 }
709
710 extern SDIOH_API_RC
sdioh_request_word(sdioh_info_t * sd,uint cmd_type,uint rw,uint func,uint addr,uint32 * word,uint nbytes)711 sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, uint addr,
712 uint32 *word, uint nbytes)
713 {
714 int status;
715
716 spi_lock(sd);
717
718 if (rw == SDIOH_READ)
719 status = bcmspi_card_regread(sd, func, addr, nbytes, word);
720 else
721 status = bcmspi_card_regwrite(sd, func, addr, nbytes, *word);
722
723 spi_unlock(sd);
724 return (status == SUCCESS ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
725 }
726
727 extern SDIOH_API_RC
sdioh_request_buffer(sdioh_info_t * sd,uint pio_dma,uint fix_inc,uint rw,uint func,uint addr,uint reg_width,uint buflen_u,uint8 * buffer,void * pkt)728 sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint rw, uint func,
729 uint addr, uint reg_width, uint buflen_u, uint8 *buffer, void *pkt)
730 {
731 int len;
732 int buflen = (int)buflen_u;
733 bool fifo = (fix_inc == SDIOH_DATA_FIX);
734
735 spi_lock(sd);
736
737 ASSERT(reg_width == 4);
738 ASSERT(buflen_u < (1 << 30));
739 ASSERT(sd->client_block_size[func]);
740
741 sd_data(("%s: %c len %d r_cnt %d t_cnt %d, pkt @0x%p\n",
742 __FUNCTION__, rw == SDIOH_READ ? 'R' : 'W',
743 buflen_u, sd->r_cnt, sd->t_cnt, pkt));
744
745 /* Break buffer down into blocksize chunks. */
746 while (buflen > 0) {
747 len = MIN(sd->client_block_size[func], buflen);
748 if (bcmspi_card_buf(sd, rw, func, fifo, addr, len, (uint32 *)buffer) != SUCCESS) {
749 sd_err(("%s: bcmspi_card_buf %s failed\n",
750 __FUNCTION__, rw == SDIOH_READ ? "Read" : "Write"));
751 spi_unlock(sd);
752 return SDIOH_API_RC_FAIL;
753 }
754 buffer += len;
755 buflen -= len;
756 if (!fifo)
757 addr += len;
758 }
759 spi_unlock(sd);
760 return SDIOH_API_RC_SUCCESS;
761 }
762
763 /* This function allows write to gspi bus when another rd/wr function is deep down the call stack.
764 * Its main aim is to have simpler spi writes rather than recursive writes.
765 * e.g. When there is a need to program response delay on the fly after detecting the SPI-func
766 * this call will allow to program the response delay.
767 */
768 static int
bcmspi_card_byterewrite(sdioh_info_t * sd,int func,uint32 regaddr,uint8 byte)769 bcmspi_card_byterewrite(sdioh_info_t *sd, int func, uint32 regaddr, uint8 byte)
770 {
771 uint32 cmd_arg;
772 uint32 datalen = 1;
773 uint32 hostlen;
774
775 cmd_arg = 0;
776
777 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
778 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
779 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
780 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
781 cmd_arg = SFIELD(cmd_arg, SPI_LEN, datalen);
782
783 sd_trace(("%s cmd_arg = 0x%x\n", __FUNCTION__, cmd_arg));
784
785 /* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
786 * according to the wordlen mode(16/32bit) the device is in.
787 */
788 ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
789 datalen = ROUNDUP(datalen, sd->wordlen);
790
791 /* Start by copying command in the spi-outbuffer */
792 if (sd->wordlen == 4) { /* 32bit spid */
793 *(uint32 *)spi_outbuf2 = SPISWAP_WD4(cmd_arg);
794 if (datalen & 0x3)
795 datalen += (4 - (datalen & 0x3));
796 } else if (sd->wordlen == 2) { /* 16bit spid */
797 *(uint32 *)spi_outbuf2 = SPISWAP_WD2(cmd_arg);
798 if (datalen & 0x1)
799 datalen++;
800 } else {
801 sd_err(("%s: Host is %d bit spid, could not create SPI command.\n",
802 __FUNCTION__, 8 * sd->wordlen));
803 return ERROR;
804 }
805
806 /* for Write, put the data into the output buffer */
807 if (datalen != 0) {
808 if (sd->wordlen == 4) { /* 32bit spid */
809 *(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD4(byte);
810 } else if (sd->wordlen == 2) { /* 16bit spid */
811 *(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD2(byte);
812 }
813 }
814
815 /* +4 for cmd, +4 for dstatus */
816 hostlen = datalen + 8;
817 hostlen += (4 - (hostlen & 0x3));
818 spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, hostlen);
819
820 /* Last 4bytes are dstatus. Device is configured to return status bits. */
821 if (sd->wordlen == 4) { /* 32bit spid */
822 sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
823 } else if (sd->wordlen == 2) { /* 16bit spid */
824 sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
825 } else {
826 sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
827 __FUNCTION__, 8 * sd->wordlen));
828 return ERROR;
829 }
830
831 if (sd->card_dstatus)
832 sd_trace(("dstatus after byte rewrite = 0x%x\n", sd->card_dstatus));
833
834 return (BCME_OK);
835 }
836
837 /* Program the response delay corresponding to the spi function */
838 static int
bcmspi_prog_resp_delay(sdioh_info_t * sd,int func,uint8 resp_delay)839 bcmspi_prog_resp_delay(sdioh_info_t *sd, int func, uint8 resp_delay)
840 {
841 if (sd->resp_delay_all == FALSE)
842 return (BCME_OK);
843
844 if (sd->prev_fun == func)
845 return (BCME_OK);
846
847 if (F0_RESPONSE_DELAY == F1_RESPONSE_DELAY)
848 return (BCME_OK);
849
850 bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_RESPONSE_DELAY, resp_delay);
851
852 /* Remember function for which to avoid reprogramming resp-delay in next iteration */
853 sd->prev_fun = func;
854
855 return (BCME_OK);
856
857 }
858
859 #define GSPI_RESYNC_PATTERN 0x0
860
861 /* A resync pattern is a 32bit MOSI line with all zeros. Its a special command in gSPI.
862 * It resets the spi-bkplane logic so that all F1 related ping-pong buffer logic is
863 * synchronised and all queued resuests are cancelled.
864 */
865 static int
bcmspi_resync_f1(sdioh_info_t * sd)866 bcmspi_resync_f1(sdioh_info_t *sd)
867 {
868 uint32 cmd_arg = GSPI_RESYNC_PATTERN, data = 0, datalen = 0;
869
870 /* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
871 * according to the wordlen mode(16/32bit) the device is in.
872 */
873 ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
874 datalen = ROUNDUP(datalen, sd->wordlen);
875
876 /* Start by copying command in the spi-outbuffer */
877 *(uint32 *)spi_outbuf2 = cmd_arg;
878
879 /* for Write, put the data into the output buffer */
880 *(uint32 *)&spi_outbuf2[CMDLEN] = data;
881
882 /* +4 for cmd, +4 for dstatus */
883 spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, datalen + 8);
884
885 /* Last 4bytes are dstatus. Device is configured to return status bits. */
886 if (sd->wordlen == 4) { /* 32bit spid */
887 sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
888 } else if (sd->wordlen == 2) { /* 16bit spid */
889 sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
890 } else {
891 sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
892 __FUNCTION__, 8 * sd->wordlen));
893 return ERROR;
894 }
895
896 if (sd->card_dstatus)
897 sd_trace(("dstatus after resync pattern write = 0x%x\n", sd->card_dstatus));
898
899 return (BCME_OK);
900 }
901
902 uint32 dstatus_count = 0;
903
904 static int
bcmspi_update_stats(sdioh_info_t * sd,uint32 cmd_arg)905 bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg)
906 {
907 uint32 dstatus = sd->card_dstatus;
908 struct spierrstats_t *spierrstats = &sd->spierrstats;
909 int err = SUCCESS;
910
911 sd_trace(("cmd = 0x%x, dstatus = 0x%x\n", cmd_arg, dstatus));
912
913 /* Store dstatus of last few gSPI transactions */
914 spierrstats->dstatus[dstatus_count % NUM_PREV_TRANSACTIONS] = dstatus;
915 spierrstats->spicmd[dstatus_count % NUM_PREV_TRANSACTIONS] = cmd_arg;
916 dstatus_count++;
917
918 if (sd->card_init_done == FALSE)
919 return err;
920
921 if (dstatus & STATUS_DATA_NOT_AVAILABLE) {
922 spierrstats->dna++;
923 sd_trace(("Read data not available on F1 addr = 0x%x\n",
924 GFIELD(cmd_arg, SPI_REG_ADDR)));
925 /* Clear dna bit */
926 bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, DATA_UNAVAILABLE);
927 }
928
929 if (dstatus & STATUS_UNDERFLOW) {
930 spierrstats->rdunderflow++;
931 sd_err(("FIFO underflow happened due to current F2 read command.\n"));
932 }
933
934 if (dstatus & STATUS_OVERFLOW) {
935 spierrstats->wroverflow++;
936 sd_err(("FIFO overflow happened due to current (F1/F2) write command.\n"));
937 bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, F1_OVERFLOW);
938 bcmspi_resync_f1(sd);
939 sd_err(("Recovering from F1 FIFO overflow.\n"));
940 }
941
942 if (dstatus & STATUS_F2_INTR) {
943 spierrstats->f2interrupt++;
944 sd_trace(("Interrupt from F2. SW should clear corresponding IntStatus bits\n"));
945 }
946
947 if (dstatus & STATUS_F3_INTR) {
948 spierrstats->f3interrupt++;
949 sd_err(("Interrupt from F3. SW should clear corresponding IntStatus bits\n"));
950 }
951
952 if (dstatus & STATUS_HOST_CMD_DATA_ERR) {
953 spierrstats->hostcmddataerr++;
954 sd_err(("Error in CMD or Host data, detected by CRC/Checksum (optional)\n"));
955 }
956
957 if (dstatus & STATUS_F2_PKT_AVAILABLE) {
958 spierrstats->f2pktavailable++;
959 sd_trace(("Packet is available/ready in F2 TX FIFO\n"));
960 sd_trace(("Packet length = %d\n", sd->dwordmode ?
961 ((dstatus & STATUS_F2_PKT_LEN_MASK) >> (STATUS_F2_PKT_LEN_SHIFT - 2)) :
962 ((dstatus & STATUS_F2_PKT_LEN_MASK) >> STATUS_F2_PKT_LEN_SHIFT)));
963 }
964
965 if (dstatus & STATUS_F3_PKT_AVAILABLE) {
966 spierrstats->f3pktavailable++;
967 sd_err(("Packet is available/ready in F3 TX FIFO\n"));
968 sd_err(("Packet length = %d\n",
969 (dstatus & STATUS_F3_PKT_LEN_MASK) >> STATUS_F3_PKT_LEN_SHIFT));
970 }
971
972 return err;
973 }
974
975 extern int
sdioh_abort(sdioh_info_t * sd,uint func)976 sdioh_abort(sdioh_info_t *sd, uint func)
977 {
978 return 0;
979 }
980
981 int
sdioh_start(sdioh_info_t * sd,int stage)982 sdioh_start(sdioh_info_t *sd, int stage)
983 {
984 return SUCCESS;
985 }
986
987 int
sdioh_stop(sdioh_info_t * sd)988 sdioh_stop(sdioh_info_t *sd)
989 {
990 return SUCCESS;
991 }
992
993 int
sdioh_waitlockfree(sdioh_info_t * sd)994 sdioh_waitlockfree(sdioh_info_t *sd)
995 {
996 return SUCCESS;
997 }
998
999 /*
1000 * Private/Static work routines
1001 */
1002 static int
bcmspi_host_init(sdioh_info_t * sd)1003 bcmspi_host_init(sdioh_info_t *sd)
1004 {
1005
1006 /* Default power on mode */
1007 sd->sd_mode = SDIOH_MODE_SPI;
1008 sd->polled_mode = TRUE;
1009 sd->host_init_done = TRUE;
1010 sd->card_init_done = FALSE;
1011 sd->adapter_slot = 1;
1012
1013 return (SUCCESS);
1014 }
1015
1016 static int
get_client_blocksize(sdioh_info_t * sd)1017 get_client_blocksize(sdioh_info_t *sd)
1018 {
1019 uint32 regdata[2];
1020 int status;
1021
1022 /* Find F1/F2/F3 max packet size */
1023 if ((status = bcmspi_card_regread(sd, 0, SPID_F1_INFO_REG,
1024 8, regdata)) != SUCCESS) {
1025 return status;
1026 }
1027
1028 sd_trace(("pkt_size regdata[0] = 0x%x, regdata[1] = 0x%x\n",
1029 regdata[0], regdata[1]));
1030
1031 sd->client_block_size[1] = (regdata[0] & F1_MAX_PKT_SIZE) >> 2;
1032 sd_trace(("Func1 blocksize = %d\n", sd->client_block_size[1]));
1033 ASSERT(sd->client_block_size[1] == BLOCK_SIZE_F1);
1034
1035 sd->client_block_size[2] = ((regdata[0] >> 16) & F2_MAX_PKT_SIZE) >> 2;
1036 sd_trace(("Func2 blocksize = %d\n", sd->client_block_size[2]));
1037 ASSERT(sd->client_block_size[2] == BLOCK_SIZE_F2);
1038
1039 sd->client_block_size[3] = (regdata[1] & F3_MAX_PKT_SIZE) >> 2;
1040 sd_trace(("Func3 blocksize = %d\n", sd->client_block_size[3]));
1041 ASSERT(sd->client_block_size[3] == BLOCK_SIZE_F3);
1042
1043 return 0;
1044 }
1045
1046 static int
bcmspi_client_init(sdioh_info_t * sd)1047 bcmspi_client_init(sdioh_info_t *sd)
1048 {
1049 uint32 status_en_reg = 0;
1050 sd_trace(("%s: Powering up slot %d\n", __FUNCTION__, sd->adapter_slot));
1051
1052 #ifndef BCMSPI_ANDROID
1053 #ifdef HSMODE
1054 if (!spi_start_clock(sd, (uint16)sd_divisor)) {
1055 sd_err(("spi_start_clock failed\n"));
1056 return ERROR;
1057 }
1058 #else
1059 /* Start at ~400KHz clock rate for initialization */
1060 if (!spi_start_clock(sd, 128)) {
1061 sd_err(("spi_start_clock failed\n"));
1062 return ERROR;
1063 }
1064 #endif /* HSMODE */
1065 #endif /* !BCMSPI_ANDROID */
1066
1067 if (!bcmspi_host_device_init_adapt(sd)) {
1068 sd_err(("bcmspi_host_device_init_adapt failed\n"));
1069 return ERROR;
1070 }
1071
1072 if (!bcmspi_test_card(sd)) {
1073 sd_err(("bcmspi_test_card failed\n"));
1074 return ERROR;
1075 }
1076
1077 sd->num_funcs = SPI_MAX_IOFUNCS;
1078
1079 get_client_blocksize(sd);
1080
1081 /* Apply resync pattern cmd with all zeros to reset spi-bkplane F1 logic */
1082 bcmspi_resync_f1(sd);
1083
1084 sd->dwordmode = FALSE;
1085
1086 bcmspi_card_regread(sd, 0, SPID_STATUS_ENABLE, 1, &status_en_reg);
1087
1088 sd_trace(("%s: Enabling interrupt with dstatus \n", __FUNCTION__));
1089 status_en_reg |= INTR_WITH_STATUS;
1090
1091 if (bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_STATUS_ENABLE, 1,
1092 status_en_reg & 0xff) != SUCCESS) {
1093 sd_err(("%s: Unable to set response delay for all fun's.\n", __FUNCTION__));
1094 return ERROR;
1095 }
1096
1097 #ifndef HSMODE
1098 #ifndef BCMSPI_ANDROID
1099 /* After configuring for High-Speed mode, set the desired clock rate. */
1100 if (!spi_start_clock(sd, 4)) {
1101 sd_err(("spi_start_clock failed\n"));
1102 return ERROR;
1103 }
1104 #endif /* !BCMSPI_ANDROID */
1105 #endif /* HSMODE */
1106
1107 /* check to see if the response delay needs to be programmed properly */
1108 {
1109 uint32 f1_respdelay = 0;
1110 bcmspi_card_regread(sd, 0, SPID_RESP_DELAY_F1, 1, &f1_respdelay);
1111 if ((f1_respdelay == 0) || (f1_respdelay == 0xFF)) {
1112 /* older sdiodevice core and has no separte resp delay for each of */
1113 sd_err(("older corerev < 4 so use the same resp delay for all funcs\n"));
1114 sd->resp_delay_new = FALSE;
1115 }
1116 else {
1117 /* older sdiodevice core and has no separte resp delay for each of */
1118 int ret_val;
1119 sd->resp_delay_new = TRUE;
1120 sd_err(("new corerev >= 4 so set the resp delay for each of the funcs\n"));
1121 sd_trace(("resp delay for funcs f0(%d), f1(%d), f2(%d), f3(%d)\n",
1122 GSPI_F0_RESP_DELAY, GSPI_F1_RESP_DELAY,
1123 GSPI_F2_RESP_DELAY, GSPI_F3_RESP_DELAY));
1124 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F0, 1,
1125 GSPI_F0_RESP_DELAY);
1126 if (ret_val != SUCCESS) {
1127 sd_err(("%s: Unable to set response delay for F0\n", __FUNCTION__));
1128 return ERROR;
1129 }
1130 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F1, 1,
1131 GSPI_F1_RESP_DELAY);
1132 if (ret_val != SUCCESS) {
1133 sd_err(("%s: Unable to set response delay for F1\n", __FUNCTION__));
1134 return ERROR;
1135 }
1136 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F2, 1,
1137 GSPI_F2_RESP_DELAY);
1138 if (ret_val != SUCCESS) {
1139 sd_err(("%s: Unable to set response delay for F2\n", __FUNCTION__));
1140 return ERROR;
1141 }
1142 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F3, 1,
1143 GSPI_F3_RESP_DELAY);
1144 if (ret_val != SUCCESS) {
1145 sd_err(("%s: Unable to set response delay for F2\n", __FUNCTION__));
1146 return ERROR;
1147 }
1148 }
1149 }
1150
1151 sd->card_init_done = TRUE;
1152
1153 /* get the device rev to program the prop respdelays */
1154
1155 return SUCCESS;
1156 }
1157
1158 static int
bcmspi_set_highspeed_mode(sdioh_info_t * sd,bool hsmode)1159 bcmspi_set_highspeed_mode(sdioh_info_t *sd, bool hsmode)
1160 {
1161 uint32 regdata;
1162 int status;
1163
1164 if ((status = bcmspi_card_regread(sd, 0, SPID_CONFIG,
1165 4, ®data)) != SUCCESS)
1166 return status;
1167
1168 sd_trace(("In %s spih-ctrl = 0x%x \n", __FUNCTION__, regdata));
1169
1170 if (hsmode == TRUE) {
1171 sd_trace(("Attempting to enable High-Speed mode.\n"));
1172
1173 if (regdata & HIGH_SPEED_MODE) {
1174 sd_trace(("Device is already in High-Speed mode.\n"));
1175 return status;
1176 } else {
1177 regdata |= HIGH_SPEED_MODE;
1178 sd_trace(("Writing %08x to device at %08x\n", regdata, SPID_CONFIG));
1179 if ((status = bcmspi_card_regwrite(sd, 0, SPID_CONFIG,
1180 4, regdata)) != SUCCESS) {
1181 return status;
1182 }
1183 }
1184 } else {
1185 sd_trace(("Attempting to disable High-Speed mode.\n"));
1186
1187 if (regdata & HIGH_SPEED_MODE) {
1188 regdata &= ~HIGH_SPEED_MODE;
1189 sd_trace(("Writing %08x to device at %08x\n", regdata, SPID_CONFIG));
1190 if ((status = bcmspi_card_regwrite(sd, 0, SPID_CONFIG,
1191 4, regdata)) != SUCCESS)
1192 return status;
1193 }
1194 else {
1195 sd_trace(("Device is already in Low-Speed mode.\n"));
1196 return status;
1197 }
1198 }
1199 #ifndef BCMSPI_ANDROID
1200 spi_controller_highspeed_mode(sd, hsmode);
1201 #endif /* !BCMSPI_ANDROID */
1202
1203 return TRUE;
1204 }
1205
1206 #define bcmspi_find_curr_mode(sd) { \
1207 sd->wordlen = 2; \
1208 status = bcmspi_card_regread_fixedaddr(sd, 0, SPID_TEST_READ, 4, ®data); \
1209 regdata &= 0xff; \
1210 if ((regdata == 0xad) || (regdata == 0x5b) || \
1211 (regdata == 0x5d) || (regdata == 0x5a)) \
1212 break; \
1213 sd->wordlen = 4; \
1214 status = bcmspi_card_regread_fixedaddr(sd, 0, SPID_TEST_READ, 4, ®data); \
1215 regdata &= 0xff; \
1216 if ((regdata == 0xad) || (regdata == 0x5b) || \
1217 (regdata == 0x5d) || (regdata == 0x5a)) \
1218 break; \
1219 sd_trace(("Silicon testability issue: regdata = 0x%x." \
1220 " Expected 0xad, 0x5a, 0x5b or 0x5d.\n", regdata)); \
1221 OSL_DELAY(100000); \
1222 }
1223
1224 #define INIT_ADAPT_LOOP 100
1225
1226 /* Adapt clock-phase-speed-bitwidth between host and device */
1227 static bool
bcmspi_host_device_init_adapt(sdioh_info_t * sd)1228 bcmspi_host_device_init_adapt(sdioh_info_t *sd)
1229 {
1230 uint32 wrregdata, regdata = 0;
1231 int status;
1232 int i;
1233
1234 /* Due to a silicon testability issue, the first command from the Host
1235 * to the device will get corrupted (first bit will be lost). So the
1236 * Host should poll the device with a safe read request. ie: The Host
1237 * should try to read F0 addr 0x14 using the Fixed address mode
1238 * (This will prevent a unintended write command to be detected by device)
1239 */
1240 for (i = 0; i < INIT_ADAPT_LOOP; i++) {
1241 /* If device was not power-cycled it will stay in 32bit mode with
1242 * response-delay-all bit set. Alternate the iteration so that
1243 * read either with or without response-delay for F0 to succeed.
1244 */
1245 bcmspi_find_curr_mode(sd);
1246 sd->resp_delay_all = (i & 0x1) ? TRUE : FALSE;
1247
1248 bcmspi_find_curr_mode(sd);
1249 sd->dwordmode = TRUE;
1250
1251 bcmspi_find_curr_mode(sd);
1252 sd->dwordmode = FALSE;
1253 }
1254
1255 /* Bail out, device not detected */
1256 if (i == INIT_ADAPT_LOOP)
1257 return FALSE;
1258
1259 /* Softreset the spid logic */
1260 if ((sd->dwordmode) || (sd->wordlen == 4)) {
1261 bcmspi_card_regwrite(sd, 0, SPID_RESET_BP, 1, RESET_ON_WLAN_BP_RESET|RESET_SPI);
1262 bcmspi_card_regread(sd, 0, SPID_RESET_BP, 1, ®data);
1263 sd_trace(("reset reg read = 0x%x\n", regdata));
1264 sd_trace(("dwordmode = %d, wordlen = %d, resp_delay_all = %d\n", sd->dwordmode,
1265 sd->wordlen, sd->resp_delay_all));
1266 /* Restore default state after softreset */
1267 sd->wordlen = 2;
1268 sd->dwordmode = FALSE;
1269 }
1270
1271 if (sd->wordlen == 4) {
1272 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) !=
1273 SUCCESS)
1274 return FALSE;
1275 if (regdata == TEST_RO_DATA_32BIT_LE) {
1276 sd_trace(("Spid is already in 32bit LE mode. Value read = 0x%x\n",
1277 regdata));
1278 sd_trace(("Spid power was left on.\n"));
1279 } else {
1280 sd_err(("Spid power was left on but signature read failed."
1281 " Value read = 0x%x\n", regdata));
1282 return FALSE;
1283 }
1284 } else {
1285 sd->wordlen = 2;
1286
1287 #define CTRL_REG_DEFAULT 0x00010430 /* according to the host m/c */
1288
1289 wrregdata = (CTRL_REG_DEFAULT);
1290
1291 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) != SUCCESS)
1292 return FALSE;
1293 sd_trace(("(we are still in 16bit mode) 32bit READ LE regdata = 0x%x\n", regdata));
1294
1295 #ifndef HSMODE
1296 wrregdata |= (CLOCK_PHASE | CLOCK_POLARITY);
1297 wrregdata &= ~HIGH_SPEED_MODE;
1298 bcmspi_card_regwrite(sd, 0, SPID_CONFIG, 4, wrregdata);
1299 #endif /* HSMODE */
1300
1301 for (i = 0; i < INIT_ADAPT_LOOP; i++) {
1302 if ((regdata == 0xfdda7d5b) || (regdata == 0xfdda7d5a)) {
1303 sd_trace(("0xfeedbead was leftshifted by 1-bit.\n"));
1304 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4,
1305 ®data)) != SUCCESS)
1306 return FALSE;
1307 }
1308 OSL_DELAY(1000);
1309 }
1310
1311 #if defined(CHANGE_SPI_INTR_POLARITY_ACTIVE_HIGH)
1312 /* Change to host controller intr-polarity of active-high */
1313 wrregdata |= INTR_POLARITY;
1314 #else
1315 /* Change to host controller intr-polarity of active-low */
1316 wrregdata &= ~INTR_POLARITY;
1317 #endif /* CHANGE_SPI_INTR_POLARITY_ACTIVE_HIGH */
1318
1319 sd_trace(("(we are still in 16bit mode) 32bit Write LE reg-ctrl-data = 0x%x\n",
1320 wrregdata));
1321 /* Change to 32bit mode */
1322 wrregdata |= WORD_LENGTH_32;
1323 bcmspi_card_regwrite(sd, 0, SPID_CONFIG, 4, wrregdata);
1324
1325 /* Change command/data packaging in 32bit LE mode */
1326 sd->wordlen = 4;
1327
1328 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) != SUCCESS)
1329 return FALSE;
1330
1331 if (regdata == TEST_RO_DATA_32BIT_LE) {
1332 sd_trace(("Read spid passed. Value read = 0x%x\n", regdata));
1333 sd_trace(("Spid had power-on cycle OR spi was soft-resetted \n"));
1334 } else {
1335 sd_err(("Stale spid reg values read as it was kept powered. Value read ="
1336 "0x%x\n", regdata));
1337 return FALSE;
1338 }
1339 }
1340
1341 return TRUE;
1342 }
1343
1344 static bool
bcmspi_test_card(sdioh_info_t * sd)1345 bcmspi_test_card(sdioh_info_t *sd)
1346 {
1347 uint32 regdata;
1348 int status;
1349
1350 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) != SUCCESS)
1351 return FALSE;
1352
1353 if (regdata == (TEST_RO_DATA_32BIT_LE))
1354 sd_trace(("32bit LE regdata = 0x%x\n", regdata));
1355 else {
1356 sd_trace(("Incorrect 32bit LE regdata = 0x%x\n", regdata));
1357 return FALSE;
1358 }
1359
1360 #define RW_PATTERN1 0xA0A1A2A3
1361 #define RW_PATTERN2 0x4B5B6B7B
1362
1363 regdata = RW_PATTERN1;
1364 if ((status = bcmspi_card_regwrite(sd, 0, SPID_TEST_RW, 4, regdata)) != SUCCESS)
1365 return FALSE;
1366 regdata = 0;
1367 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_RW, 4, ®data)) != SUCCESS)
1368 return FALSE;
1369 if (regdata != RW_PATTERN1) {
1370 sd_err(("Write-Read spid failed. Value wrote = 0x%x, Value read = 0x%x\n",
1371 RW_PATTERN1, regdata));
1372 return FALSE;
1373 } else
1374 sd_trace(("R/W spid passed. Value read = 0x%x\n", regdata));
1375
1376 regdata = RW_PATTERN2;
1377 if ((status = bcmspi_card_regwrite(sd, 0, SPID_TEST_RW, 4, regdata)) != SUCCESS)
1378 return FALSE;
1379 regdata = 0;
1380 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_RW, 4, ®data)) != SUCCESS)
1381 return FALSE;
1382 if (regdata != RW_PATTERN2) {
1383 sd_err(("Write-Read spid failed. Value wrote = 0x%x, Value read = 0x%x\n",
1384 RW_PATTERN2, regdata));
1385 return FALSE;
1386 } else
1387 sd_trace(("R/W spid passed. Value read = 0x%x\n", regdata));
1388
1389 return TRUE;
1390 }
1391
1392 static int
bcmspi_driver_init(sdioh_info_t * sd)1393 bcmspi_driver_init(sdioh_info_t *sd)
1394 {
1395 sd_trace(("%s\n", __FUNCTION__));
1396 if ((bcmspi_host_init(sd)) != SUCCESS) {
1397 return ERROR;
1398 }
1399
1400 if (bcmspi_client_init(sd) != SUCCESS) {
1401 return ERROR;
1402 }
1403
1404 return SUCCESS;
1405 }
1406
1407 /* Read device reg */
1408 static int
bcmspi_card_regread(sdioh_info_t * sd,int func,uint32 regaddr,int regsize,uint32 * data)1409 bcmspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
1410 {
1411 int status;
1412 uint32 cmd_arg, dstatus;
1413
1414 ASSERT(regsize);
1415
1416 if (func == 2)
1417 sd_trace(("Reg access on F2 will generate error indication in dstatus bits.\n"));
1418
1419 cmd_arg = 0;
1420 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 0);
1421 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
1422 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1423 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1424 cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize == BLOCK_SIZE_F2 ? 0 : regsize);
1425
1426 sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d\n",
1427 __FUNCTION__, cmd_arg, func, regaddr, regsize));
1428
1429 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, regsize)) != SUCCESS)
1430 return status;
1431
1432 bcmspi_cmd_getdstatus(sd, &dstatus);
1433 if (dstatus)
1434 sd_trace(("dstatus =0x%x\n", dstatus));
1435
1436 return SUCCESS;
1437 }
1438
1439 static int
bcmspi_card_regread_fixedaddr(sdioh_info_t * sd,int func,uint32 regaddr,int regsize,uint32 * data)1440 bcmspi_card_regread_fixedaddr(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
1441 {
1442
1443 int status;
1444 uint32 cmd_arg;
1445 uint32 dstatus;
1446
1447 ASSERT(regsize);
1448
1449 if (func == 2)
1450 sd_trace(("Reg access on F2 will generate error indication in dstatus bits.\n"));
1451
1452 cmd_arg = 0;
1453 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 0);
1454 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 0); /* Fixed access */
1455 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1456 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1457 cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize);
1458
1459 sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d\n",
1460 __FUNCTION__, cmd_arg, func, regaddr, regsize));
1461
1462 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, regsize)) != SUCCESS)
1463 return status;
1464
1465 sd_trace(("%s: RD result=0x%x\n", __FUNCTION__, *data));
1466
1467 bcmspi_cmd_getdstatus(sd, &dstatus);
1468 sd_trace(("dstatus =0x%x\n", dstatus));
1469 return SUCCESS;
1470 }
1471
1472 /* write a device register */
1473 static int
bcmspi_card_regwrite(sdioh_info_t * sd,int func,uint32 regaddr,int regsize,uint32 data)1474 bcmspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 data)
1475 {
1476 int status;
1477 uint32 cmd_arg, dstatus;
1478
1479 ASSERT(regsize);
1480
1481 cmd_arg = 0;
1482
1483 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
1484 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
1485 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1486 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1487 cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize == BLOCK_SIZE_F2 ? 0 : regsize);
1488
1489 sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d data=0x%x\n",
1490 __FUNCTION__, cmd_arg, func, regaddr, regsize, data));
1491
1492 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, regsize)) != SUCCESS)
1493 return status;
1494
1495 bcmspi_cmd_getdstatus(sd, &dstatus);
1496 if (dstatus)
1497 sd_trace(("dstatus=0x%x\n", dstatus));
1498
1499 return SUCCESS;
1500 }
1501
1502 /* write a device register - 1 byte */
1503 static int
bcmspi_card_bytewrite(sdioh_info_t * sd,int func,uint32 regaddr,uint8 * byte)1504 bcmspi_card_bytewrite(sdioh_info_t *sd, int func, uint32 regaddr, uint8 *byte)
1505 {
1506 int status;
1507 uint32 cmd_arg;
1508 uint32 dstatus;
1509 uint32 data = (uint32)(*byte);
1510
1511 cmd_arg = 0;
1512 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1513 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
1514 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1515 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
1516 cmd_arg = SFIELD(cmd_arg, SPI_LEN, 1);
1517
1518 sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x data=0x%x\n",
1519 __FUNCTION__, cmd_arg, func, regaddr, data));
1520
1521 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, 1)) != SUCCESS)
1522 return status;
1523
1524 bcmspi_cmd_getdstatus(sd, &dstatus);
1525 if (dstatus)
1526 sd_trace(("dstatus =0x%x\n", dstatus));
1527
1528 return SUCCESS;
1529 }
1530
1531 void
bcmspi_cmd_getdstatus(sdioh_info_t * sd,uint32 * dstatus_buffer)1532 bcmspi_cmd_getdstatus(sdioh_info_t *sd, uint32 *dstatus_buffer)
1533 {
1534 *dstatus_buffer = sd->card_dstatus;
1535 }
1536
1537 /* 'data' is of type uint32 whereas other buffers are of type uint8 */
1538 static int
bcmspi_cmd_issue(sdioh_info_t * sd,bool use_dma,uint32 cmd_arg,uint32 * data,uint32 datalen)1539 bcmspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd_arg,
1540 uint32 *data, uint32 datalen)
1541 {
1542 uint32 i, j;
1543 uint8 resp_delay = 0;
1544 int err = SUCCESS;
1545 uint32 hostlen;
1546 uint32 spilen = 0;
1547 uint32 dstatus_idx = 0;
1548 uint16 templen, buslen, len, *ptr = NULL;
1549
1550 sd_trace(("spi cmd = 0x%x\n", cmd_arg));
1551
1552 /* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
1553 * according to the wordlen mode(16/32bit) the device is in.
1554 */
1555 if (sd->wordlen == 4) { /* 32bit spid */
1556 *(uint32 *)spi_outbuf = SPISWAP_WD4(cmd_arg);
1557 if (datalen & 0x3)
1558 datalen += (4 - (datalen & 0x3));
1559 } else if (sd->wordlen == 2) { /* 16bit spid */
1560 *(uint32 *)spi_outbuf = SPISWAP_WD2(cmd_arg);
1561 if (datalen & 0x1)
1562 datalen++;
1563 if (datalen < 4)
1564 datalen = ROUNDUP(datalen, 4);
1565 } else {
1566 sd_err(("Host is %d bit spid, could not create SPI command.\n",
1567 8 * sd->wordlen));
1568 return ERROR;
1569 }
1570
1571 /* for Write, put the data into the output buffer */
1572 if (GFIELD(cmd_arg, SPI_RW_FLAG) == 1) {
1573 /* We send len field of hw-header always a mod16 size, both from host and dongle */
1574 if (datalen != 0) {
1575 for (i = 0; i < datalen/4; i++) {
1576 if (sd->wordlen == 4) { /* 32bit spid */
1577 *(uint32 *)&spi_outbuf[i * 4 + CMDLEN] =
1578 SPISWAP_WD4(data[i]);
1579 } else if (sd->wordlen == 2) { /* 16bit spid */
1580 *(uint32 *)&spi_outbuf[i * 4 + CMDLEN] =
1581 SPISWAP_WD2(data[i]);
1582 }
1583 }
1584 }
1585 }
1586
1587 /* Append resp-delay number of bytes and clock them out for F0/1/2 reads. */
1588 if ((GFIELD(cmd_arg, SPI_RW_FLAG) == 0)) {
1589 int func = GFIELD(cmd_arg, SPI_FUNCTION);
1590 switch (func) {
1591 case 0:
1592 if (sd->resp_delay_new)
1593 resp_delay = GSPI_F0_RESP_DELAY;
1594 else
1595 resp_delay = sd->resp_delay_all ? F0_RESPONSE_DELAY : 0;
1596 break;
1597 case 1:
1598 if (sd->resp_delay_new)
1599 resp_delay = GSPI_F1_RESP_DELAY;
1600 else
1601 resp_delay = F1_RESPONSE_DELAY;
1602 break;
1603 case 2:
1604 if (sd->resp_delay_new)
1605 resp_delay = GSPI_F2_RESP_DELAY;
1606 else
1607 resp_delay = sd->resp_delay_all ? F2_RESPONSE_DELAY : 0;
1608 break;
1609 default:
1610 ASSERT(0);
1611 break;
1612 }
1613 /* Program response delay */
1614 if (sd->resp_delay_new == FALSE)
1615 bcmspi_prog_resp_delay(sd, func, resp_delay);
1616 }
1617
1618 /* +4 for cmd and +4 for dstatus */
1619 hostlen = datalen + 8 + resp_delay;
1620 hostlen += dstatus_idx;
1621 #ifdef BCMSPI_ANDROID
1622 if (hostlen%4) {
1623 sd_err(("Unaligned data len %d, hostlen %d\n",
1624 datalen, hostlen));
1625 #endif /* BCMSPI_ANDROID */
1626 hostlen += (4 - (hostlen & 0x3));
1627 #ifdef BCMSPI_ANDROID
1628 }
1629 #endif /* BCMSPI_ANDROID */
1630 spi_sendrecv(sd, spi_outbuf, spi_inbuf, hostlen);
1631
1632 /* for Read, get the data into the input buffer */
1633 if (datalen != 0) {
1634 if (GFIELD(cmd_arg, SPI_RW_FLAG) == 0) { /* if read cmd */
1635 for (j = 0; j < datalen/4; j++) {
1636 if (sd->wordlen == 4) { /* 32bit spid */
1637 data[j] = SPISWAP_WD4(*(uint32 *)&spi_inbuf[j * 4 +
1638 CMDLEN + resp_delay]);
1639 } else if (sd->wordlen == 2) { /* 16bit spid */
1640 data[j] = SPISWAP_WD2(*(uint32 *)&spi_inbuf[j * 4 +
1641 CMDLEN + resp_delay]);
1642 }
1643 }
1644 }
1645 }
1646
1647 dstatus_idx += (datalen + CMDLEN + resp_delay);
1648 /* Last 4bytes are dstatus. Device is configured to return status bits. */
1649 if (sd->wordlen == 4) { /* 32bit spid */
1650 sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf[dstatus_idx]);
1651 } else if (sd->wordlen == 2) { /* 16bit spid */
1652 sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf[dstatus_idx]);
1653 } else {
1654 sd_err(("Host is %d bit machine, could not read SPI dstatus.\n",
1655 8 * sd->wordlen));
1656 return ERROR;
1657 }
1658 if (sd->card_dstatus == 0xffffffff) {
1659 sd_err(("looks like not a GSPI device or device is not powered.\n"));
1660 }
1661
1662 err = bcmspi_update_stats(sd, cmd_arg);
1663
1664 return err;
1665
1666 }
1667
1668 static int
bcmspi_card_buf(sdioh_info_t * sd,int rw,int func,bool fifo,uint32 addr,int nbytes,uint32 * data)1669 bcmspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
1670 uint32 addr, int nbytes, uint32 *data)
1671 {
1672 int status;
1673 uint32 cmd_arg;
1674 bool write = rw == SDIOH_READ ? 0 : 1;
1675 uint retries = 0;
1676
1677 bool enable;
1678 uint32 spilen;
1679
1680 cmd_arg = 0;
1681
1682 ASSERT(nbytes);
1683 ASSERT(nbytes <= sd->client_block_size[func]);
1684
1685 if (write) sd->t_cnt++; else sd->r_cnt++;
1686
1687 if (func == 2) {
1688 /* Frame len check limited by gSPI. */
1689 if ((nbytes > 2000) && write) {
1690 sd_trace((">2KB write: F2 wr of %d bytes\n", nbytes));
1691 }
1692 /* ASSERT(nbytes <= 2048); Fix bigger len gspi issue and uncomment. */
1693 /* If F2 fifo on device is not ready to receive data, don't do F2 transfer */
1694 if (write) {
1695 uint32 dstatus;
1696 /* check F2 ready with cached one */
1697 bcmspi_cmd_getdstatus(sd, &dstatus);
1698 if ((dstatus & STATUS_F2_RX_READY) == 0) {
1699 retries = WAIT_F2RXFIFORDY;
1700 enable = 0;
1701 while (retries-- && !enable) {
1702 OSL_DELAY(WAIT_F2RXFIFORDY_DELAY * 1000);
1703 bcmspi_card_regread(sd, SPI_FUNC_0, SPID_STATUS_REG, 4,
1704 &dstatus);
1705 if (dstatus & STATUS_F2_RX_READY)
1706 enable = TRUE;
1707 }
1708 if (!enable) {
1709 struct spierrstats_t *spierrstats = &sd->spierrstats;
1710 spierrstats->f2rxnotready++;
1711 sd_err(("F2 FIFO is not ready to receive data.\n"));
1712 return ERROR;
1713 }
1714 sd_trace(("No of retries on F2 ready %d\n",
1715 (WAIT_F2RXFIFORDY - retries)));
1716 }
1717 }
1718 }
1719
1720 /* F2 transfers happen on 0 addr */
1721 addr = (func == 2) ? 0 : addr;
1722
1723 /* In pio mode buffer is read using fixed address fifo in func 1 */
1724 if ((func == 1) && (fifo))
1725 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 0);
1726 else
1727 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);
1728
1729 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1730 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, addr);
1731 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, write);
1732 spilen = sd->data_xfer_count = MIN(sd->client_block_size[func], nbytes);
1733 if ((sd->dwordmode == TRUE) && (GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2)) {
1734 /* convert len to mod4 size */
1735 spilen = spilen + ((spilen & 0x3) ? (4 - (spilen & 0x3)): 0);
1736 cmd_arg = SFIELD(cmd_arg, SPI_LEN, (spilen >> 2));
1737 } else
1738 cmd_arg = SFIELD(cmd_arg, SPI_LEN, spilen);
1739
1740 if ((func == 2) && (fifo == 1)) {
1741 sd_data(("%s: %s func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
1742 __FUNCTION__, write ? "Wr" : "Rd", func, "INCR",
1743 addr, nbytes, sd->r_cnt, sd->t_cnt));
1744 }
1745
1746 sd_trace(("%s cmd_arg = 0x%x\n", __FUNCTION__, cmd_arg));
1747 sd_data(("%s: %s func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
1748 __FUNCTION__, write ? "Wd" : "Rd", func, "INCR",
1749 addr, nbytes, sd->r_cnt, sd->t_cnt));
1750
1751 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, nbytes)) != SUCCESS) {
1752 sd_err(("%s: cmd_issue failed for %s\n", __FUNCTION__,
1753 (write ? "write" : "read")));
1754 return status;
1755 }
1756
1757 /* gSPI expects that hw-header-len is equal to spi-command-len */
1758 if ((func == 2) && (rw == SDIOH_WRITE) && (sd->dwordmode == FALSE)) {
1759 ASSERT((uint16)sd->data_xfer_count == (uint16)(*data & 0xffff));
1760 ASSERT((uint16)sd->data_xfer_count == (uint16)(~((*data & 0xffff0000) >> 16)));
1761 }
1762
1763 if ((nbytes > 2000) && !write) {
1764 sd_trace((">2KB read: F2 rd of %d bytes\n", nbytes));
1765 }
1766
1767 return SUCCESS;
1768 }
1769
1770 /* Reset and re-initialize the device */
1771 int
sdioh_sdio_reset(sdioh_info_t * si)1772 sdioh_sdio_reset(sdioh_info_t *si)
1773 {
1774 si->card_init_done = FALSE;
1775 return bcmspi_client_init(si);
1776 }
1777
1778 SDIOH_API_RC
sdioh_gpioouten(sdioh_info_t * sd,uint32 gpio)1779 sdioh_gpioouten(sdioh_info_t *sd, uint32 gpio)
1780 {
1781 return SDIOH_API_RC_FAIL;
1782 }
1783
1784 SDIOH_API_RC
sdioh_gpioout(sdioh_info_t * sd,uint32 gpio,bool enab)1785 sdioh_gpioout(sdioh_info_t *sd, uint32 gpio, bool enab)
1786 {
1787 return SDIOH_API_RC_FAIL;
1788 }
1789
1790 bool
sdioh_gpioin(sdioh_info_t * sd,uint32 gpio)1791 sdioh_gpioin(sdioh_info_t *sd, uint32 gpio)
1792 {
1793 return FALSE;
1794 }
1795
1796 SDIOH_API_RC
sdioh_gpio_init(sdioh_info_t * sd)1797 sdioh_gpio_init(sdioh_info_t *sd)
1798 {
1799 return SDIOH_API_RC_FAIL;
1800 }
1801