1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: Provides v151 uart register \n 16 * 17 * History: \n 18 * 2023-02-17, Create file. \n 19 */ 20 #ifndef HAL_UART_V151_REGS_DEF_H 21 #define HAL_UART_V151_REGS_DEF_H 22 23 #include <stdint.h> 24 #include "uart_porting.h" 25 26 #define UART_SHADOW_RECIEVE_BUFFER_REG_LEN 16 27 #define UART_SHADOW_TRANSMIT_HOLDING_REG_LEN 16 28 #define UART_LCR_EXT_RESERVE_LEN 9 29 30 #ifdef __cplusplus 31 #if __cplusplus 32 extern "C" { 33 #endif /* __cplusplus */ 34 #endif /* __cplusplus */ 35 36 /** 37 * @defgroup drivers_hal_uart_v151_regs_def UART V151 Regs Definition 38 * @ingroup drivers_hal_uart 39 * @{ 40 */ 41 42 typedef union uart_id { 43 uint32_t d32; 44 struct { 45 uint32_t uart_id : 8; /* !< RO, UART ID */ 46 } uart_id; 47 } uart_id_t; 48 49 typedef union data { 50 uint32_t d32; 51 struct { 52 uint32_t data : 8; /* !< RW, For Write(WO): 53 If the FIFOs are enabled, data written to this location is pushed onto the transmit 54 FIFO;If the FIFOs are not enabled, data is stored in the transmitter holding register (the 55 bottom word of the transmit FIFO); For Read(RO): This register contains the data byte 56 received on the serial input port (sin).If FIFOs are disabled, the data in the RX_DATA 57 must be read before the next data arrives, otherwise it will be overwritten, resulting in 58 an over-run error. If FIFOs are enabled, this register accesses the head of the receive 59 FIFO. If the receive FIFO is full and this register is not read before the next data 60 character arrives, then the data already in the FIFO will be preserved but any incoming 61 data will be lost and an over-run error occurs. */ 62 } data; 63 } data_t; 64 65 typedef union uart_ctl { 66 uint32_t d32; 67 struct { 68 uint32_t div_en : 1; /* !< RW, UART Divisor enable register. 69 0x0 (DISABLED): DIV_L/DIV_H register is writable only when UART Not BUSY 70 0x1 (ENABLED): Divisor Latch register is always readable and writable */ 71 uint32_t xbreak : 1; /* !< RW, Break Control Bit 72 0x0 (DISABLED): Serial output is released for data transmission 73 0x1 (ENABLED): Serial output is forced to spacing state */ 74 uint32_t dlen : 2; /* !< RW, Data Length 75 0x0 : 5 data bits per character 76 0x1 : 6 data bits per character 77 0x2 : 7 data bits per character 78 0x3 : 8 data bits per character */ 79 uint32_t eps : 1; /* !< RW, Even Parity Select 80 0x0 : an odd parity is transmitted or checked 81 0x1 : an even parity is transmitted or checked */ 82 uint32_t pen : 1; /* !< RW, Parity Enable 83 0x0 (DISABLED): disable parity 84 0x1 (ENABLED) : enable parity */ 85 uint32_t sps : 1; /* !< RW, Stick Parity Select 86 0x0 (DISABLED): Stick parity disabled 87 0x1 (ENABLED) : Stick parity enabled */ 88 uint32_t stp : 1; /* !< RW, Number of stop bits. 89 0x0 : 1 stop bit 90 0x1 : 1.5 stop bits when DLEN is zero, else 2 stop bit */ 91 } uart_ctl; 92 } uart_ctl_t; 93 94 typedef union div_h { 95 uint32_t d32; 96 struct { 97 uint32_t div_h : 8; /* !< RW, Divisor Latch register that contains the baud rate divisor for the UART. This 98 register can be accessed only when the DIV_EN bit (CTL[7]) is set and the UART is not 99 busy */ 100 } div_h; 101 } div_h_t; 102 103 typedef union div_l { 104 uint32_t d32; 105 struct { 106 uint32_t div_l : 8; /* !< RW, Divisor Latch register that contains the baud rate divisor for the UART. This 107 register can be accessed only when the DIV_EN bit (CTL[7]) is set and the UART is not 108 busy */ 109 } div_l; 110 } div_l_t; 111 112 typedef union div_fra { 113 uint32_t d32; 114 struct { 115 uint32_t div_fra : 6; /* !< RW, Fractional part of divisor.The fractional value is added to integer value set by 116 DIV_L,DIV_H. Fractional value is determined by (Divisor Fraction value)/(2^6). */ 117 } div_fra; 118 } div_fra_t; 119 120 typedef union intr_en { 121 uint32_t d32; 122 struct { 123 uint32_t rece_line_stat_intr_en : 1; /* !< RW, Receiver Line Status Interrupt enable. 124 0x0: Disable Receiver Line Status Interrupt 125 0x1: Enable Receiver Line Status Interrupt */ 126 uint32_t modem_intr_en : 1; /* !< RW, Enable Modem Status Interrupt. 127 0x0 (DISABLED): Disable Modem Status Interrupt 128 0x1 (ENABLED): Enable Modem Status Interrupt */ 129 uint32_t rece_data_intr_en : 1; /* !< RW, Enable Received Data Available Interrupt. 130 0x0: Disable Receive data Interrupt 131 0x1: Enable Receive data Interrupt */ 132 uint32_t tran_em_intr_en : 1; /* !< RW, Transmit empty interrupt enable. 133 0x0: Disable Transmit empty interrupt 134 0x1: Enable Transmit empty interrupt */ 135 uint32_t ptim_en : 1; /* !< RW, Programmable THRE Interrupt Mode Enable 136 0x0: Disable Programmable THRE Interrupt Mode 137 0x1: Enable Programmable THRE Interrupt Mode */ 138 } intr_en; 139 } intr_en_t; 140 141 typedef union intr_status { 142 uint32_t d32; 143 struct { 144 uint32_t busy_det_intr : 1; /* !< RO, busy detect */ 145 uint32_t modem_intr_status : 1; /* !< RO, modem status */ 146 uint32_t thre_intr_status : 1; /* !< RO, THR empty */ 147 uint32_t char_to_intr_status : 1; /* !< RO, character timeout */ 148 uint32_t data_avail_intr_status : 1; /* !< RO, received data available */ 149 uint32_t line_intr_status : 1; /* !< RO, receiver line status */ 150 } intr_status; 151 } intr_status_t; 152 153 typedef union intr_id { 154 uint32_t d32; 155 struct { 156 uint32_t intr_id : 4; /* !< RO, Interrupt ID. 157 Values: 158 0x0: modem status 159 0x1: no interrupt pending 160 0x2: THR empty 161 0x4: received data available 162 0x6: receiver line status 163 0xc: character timeout */ 164 uint32_t fifo_en_s : 1; /* !< RO, FIFO Enable 165 0x0: FIFO disabled 166 0x1: FIFO enabled */ 167 } intr_id; 168 } intr_id_t; 169 170 typedef union fifo_ctl { 171 uint32_t d32; 172 struct { 173 uint32_t tx_empty_trig : 2; /* !< WO, TX Empty Trigger 174 0x0: FIFO Empty 175 0x1: 2 characters in FIFO 176 0x2: FIFO 1/4 full 177 0x3: FIFO 1/2 full */ 178 uint32_t rx_empty_trig : 2; /* !< WO, RCVR Trigger 179 0x0: 1 character in FIFO 180 0x1: FIFO 1/4 full 181 0x2: FIFO 1/2 full 182 0x3: FIFO 2 less than full */ 183 uint32_t fifo_en : 1; /* !< WO, FIFO Enable 184 0x0: FIFO disabled 185 0x1: FIFO enabled */ 186 uint32_t tx_fifo_rst : 1; /* !< WO, Transmit FIFO Reset. 187 Values: 188 0x1 (RESET): Transmit FIFO reset */ 189 uint32_t rx_fifo_rst : 1; /* !< WO, Receive FIFO Reset. 190 Values: 191 0x1 (RESET): Receive FIFO reset */ 192 #if defined(CONFIG_UART_IP_VERSION_V151_PRO) 193 uint32_t rx_empty_trig_h : 2; /* !< WO, RX Empty HIGH Trigger 194 0x0: 1 character in FIFO 195 0x1: FIFO 1/4 full 196 0x2: FIFO 1/2 full 197 0x3: FIFO 2 less than full */ 198 #endif 199 } fifo_ctl; 200 } fifo_ctl_t; 201 202 typedef union far { 203 uint32_t d32; 204 struct { 205 uint32_t far : 1; /* !< RW, This register is use to enable a FIFO access mode for testing, so that the receive 206 FIFO can be written by the master and the transmit FIFO can be read by the master when 207 FIFO's are implemented and enabled. 0x0 (DISABLED): FIFO access mode disabled 0x1 208 (ENABLED): FIFO access mode enabled */ 209 } far; 210 } far_t; 211 212 typedef union modem_ctl { 213 uint32_t d32; 214 struct { 215 uint32_t afc_en : 1; /* !< RW, Auto Flow Control Enable 216 0x0 (DISABLED): Auto Flow Control Mode disabled 217 0x1 (ENABLED): Auto Flow Control Mode enabled */ 218 uint32_t lb_mode : 1; /* !< RW, LoopBack Mode 219 0x0 (DISABLED): Loopback mode disabled 220 0x1 (ENABLED) : Loopback mode enabled */ 221 uint32_t rts : 1; /* !< RW, Request to Send 222 0x0 (INACTIVE): dtr_n de-asserted (logic1) 223 0x1 (ACTIVE): dtr_n asserted (logic 0) */ 224 uint32_t dtr : 1; /* !< RW, Data Terminal Ready.Values: 225 0x0 (INACTIVE): dtr_n de-asserted (logic1) 226 0x1 (ACTIVE): dtr_n asserted (logic 0) */ 227 uint32_t out1 : 1; /* !< RW, Values: 228 0x0 (OUT1_0): out1_n de-asserted (logic 1) 229 0x1 (OUT1_1): out1_n asserted (logic 0) */ 230 uint32_t out2 : 1; /* !< RW, Values: 231 0x0 (OUT2_0): out2_n de-asserted (logic 1) 232 0x1 (OUT2_1): out2_n asserted (logic 0) */ 233 } modem_ctl; 234 } modem_ctl_t; 235 236 typedef union modem_status { 237 uint32_t d32; 238 struct { 239 uint32_t dcts : 1; /* !< RO, This is used to indicate that the modem control line cts_n has changed since the 240 last time the MODEM_STATUS was read. Values: 0x0 (NO_CHANGE): no change on cts_n since 241 last read of MSR 0x1 (CHANGE): change on cts_n since last read of MSR */ 242 uint32_t cts : 1; /* !< RO, CTS status 243 Values: 244 0x0 (DEASSERTED): cts_n input is de-asserted (logic 1) 245 0x1 (ASSERTED): cts_n input is asserted (logic 0) */ 246 uint32_t ddcd : 1; /* !< RO, Values: 247 0x0 (NO_CHANGE): No change on dcd_n since last read of MSR 248 0x1 (CHANGE): change on dcd_n since last read of MSR */ 249 uint32_t dcd : 1; /* !< RO, Values: 250 0x0 (DEASSERTED): dcd_n input is de-asserted (logic 1) 251 0x1 (ASSERTED): dcd_n input is asserted (logic 0) */ 252 uint32_t teri : 1; /* !< RO, Values: 253 0x0 (NO_CHANGE): no change on ri_n since last read of MSR 254 0x1 (CHANGE): change on ri_n since last read of MSR */ 255 uint32_t ri : 1; /* !< RO, Values: 256 0x0 (DEASSERTED): ri_n input is de-asserted (logic 1) 257 0x1 (ASSERTED): ri_n input is asserted (logic 0) */ 258 uint32_t ddsr : 1; /* !< RO, Values: 259 0x0 (NO_CHANGE): no change on dsr_n since last read of MSR 260 0x1 (CHANGE): change on dsr_n since last read of MSR */ 261 uint32_t dsr : 1; /* !< RO, Values: 262 0x0 (DEASSERTED): dsr_n input is de-asserted (logic 1) 263 0x1 (ASSERTED): dsr_n input is asserted (logic 0) */ 264 } modem_status; 265 } modem_status_t; 266 267 typedef union line_status { 268 uint32_t d32; 269 struct { 270 uint32_t rx_fifo_err : 1; /* !< RO, Receiver FIFO Error bit.This bit is only relevant when FIFO's are enabled 271 (FIFO_CTL[4] set to one). This bit is cleared when the LSR is read and the 272 character with the error is at the top of the receiver FIFO and there are no 273 subsequent errors in the FIFO. Values: 274 0x0 (NO_RX_FIFO_ERROR): No error in RX FIFO 275 0x1 (RX_FIFO_ERROR): Error in RX FIFO */ 276 uint32_t frame_err : 1; /* !< RO, Frame error bit.Reading the LINE_STATUS clears this bit. 277 Values: 278 0x0 (NO_FRAMING_ERROR): no framing error 279 0x1 (FRAMING_ERROR): framing error */ 280 uint32_t parity_err : 1; /* !< RO, Parity Error bit.Reading the LINE_STATUS clears this bit. 281 Values: 282 0x0 (NO_PARITY_ERROR): no parity error 283 0x1 (PARITY_ERROR): parity error */ 284 uint32_t overrun_err : 1; /* !< RO, Overrun error bit.Reading the LINE_STATUS clears this bit. 285 Values: 286 0x0 (NO_PARITY_ERROR): no parity error 287 0x1 (PARITY_ERROR): parity error */ 288 uint32_t break_intr : 1; /* !< RO, This is used to indicate the detection of a break sequence on 289 the serial input data. 290 Values: 291 0x0 (NO_BREAK): No break sequence detected 292 0x1 (BREAK): Break sequence detected */ 293 uint32_t data_available : 1; /* !< RO, This is used to indicate that the receiver contains at least one 294 character in the RBR or the receiver FIFO. This bit is cleared 295 when the RBR is read in the non-FIFO mode, or when the 296 receiver FIFO is empty, in the FIFO mode. 297 Values: 298 0x0 (NOT_READY): data not ready 299 0x1 (READY): data ready */ 300 uint32_t thre_s : 1; /* !< RO, Transmit Holding Register Empty bit.If INTR_EN[4] is enabled, then if FIFO 301 FIFO_CTL[4] is enabled, this bit will be asserted when the TX FIFO is full. If 302 FIFO_CTL[4] is not enabled, it will be asserted then the THR register is empty. 303 Otherwise it will be asserted when THR empty is asserted. 304 Values: 0x0 (DISABLED): THRE interrupt control is disabled 305 0x1 (ENABLED): THRE interrupt control is enabled */ 306 uint32_t tx_empty_s : 1; /* !< RO, Transmitter Empty bit. 307 If in FIFO mode and FIFO's enabled , this bit is set whenever the Transmitter 308 Shift Register and the FIFO are both empty. If in the non-FIFO mode or FIFO's are 309 disabled, this bit is set whenever the Transmitter Holding Register and the 310 Transmitter Shift Register are both empty. Reset Value: 0x1 Values: 0x0 (DISABLED): 311 Transmitter not empty 0x1 (ENABLED): Transmitter empty */ 312 } line_status; 313 } line_status_t; 314 315 typedef union uart_gp_reg { 316 uint32_t d32; 317 struct { 318 uint32_t uart_gp_reg : 8; /* !< RW, This register is for programmers to use as a temporary storage space. */ 319 } uart_gp_reg; 320 } uart_gp_reg_t; 321 322 typedef union tx_fifo_read { 323 uint32_t d32; 324 struct { 325 uint32_t tx_fifo_read : 8; /* !< RO, When FIFO's are implemented and enabled, reading this register gives the 326 data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO 327 and gives the next data value that is currently at the top of the FIFO. When 328 FIFO's are not implemented or not enabled, reading this register gives the data in 329 the DR. */ 330 } tx_fifo_read; 331 } tx_fifo_read_t; 332 333 typedef union rx_fifo_write { 334 uint32_t d32; 335 struct { 336 uint32_t rx_fifo_write : 8; /* !< WO, Receive FIFO Write Data. 337 These bits are only valid when FIFO access mode is enabled. When FIFO's are 338 implemented and enabled, the data that is written to the rx_fifo_write is pushed 339 into the receive FIFO. Each consecutive write pushes the new data to the next 340 write location in the receive FIFO. When FIFO's are not implemented or not 341 enabled, the data that is written to the rx_fifo_write is pushed into the DR. */ 342 uint32_t rx_fifo_pe : 1; /* !< WO, Receive FIFO Parity Error. */ 343 uint32_t rx_fifo_fe : 1; /* !< WO, Receive FIFO Framing Error. */ 344 } rx_fifo_write; 345 } rx_fifo_write_t; 346 347 typedef union fifo_status { 348 uint32_t d32; 349 struct { 350 uint32_t tx_fifo_full : 1; /* !< RO, Transmit FIFO Full. 351 Values: 352 0x0 (NOT_FULL): Transmit FIFO is not full 353 0x1 (FULL): Transmit FIFO is full */ 354 uint32_t tx_fifo_empty : 1; /* !< RO, Transmit FIFO Empty. 355 Values: 356 0x0 (NOT_EMPTY): Transmit FIFO is not empty 357 0x1 (EMPTY): Transmit FIFO is empty */ 358 uint32_t rx_fifo_full : 1; /* !< RO, Receive FIFO Not Empty. 359 Values: 360 0x0 (EMPTY): Receive FIFO is empty 361 0x1 (NOT_EMPTY): Receive FIFO is not empty */ 362 uint32_t rx_fifo_empty : 1; /* !< RO, Receive FIFO Full. 363 Values: 364 0x0 (NOT_FULL): Receive FIFO not full 365 0x1 (FULL): Receive FIFO full */ 366 #if defined(CONFIG_UART_IP_VERSION_V151_PRO) 367 uint32_t uart_busy : 1; /* !< RO, Uart busy. 368 Values: 369 0x0 (IDLE): uart is idle or inactive 370 0x1 (BUSY): uart is busy (actively transferring data */ 371 #endif 372 } fifo_status; 373 } fifo_status_t; 374 375 typedef union tx_fifo_cnt { 376 uint32_t d32; 377 struct { 378 uint32_t tx_fifo_level : 7; /* !< RO, Transmit FIFO Data Counter. This indicates the number of data entries in 379 the transmit FIFO.The width depends on the Transmit FIFO depth.(current width 7 380 for TX FIFO 64) */ 381 } tx_fifo_cnt; 382 } tx_fifo_cnt_t; 383 384 typedef union rx_fifo_cnt { 385 uint32_t d32; 386 struct { 387 uint32_t rx_fifo_level : 7; /* !< RO, Receive FIFO Data Counter. This indicates the number of data entries in 388 the receive FIFO.The width depends on the receive FIFO depth.(current width 7 for 389 RX FIFO 64) */ 390 } rx_fifo_cnt; 391 } rx_fifo_cnt_t; 392 393 typedef union halt_tx { 394 uint32_t d32; 395 struct { 396 uint32_t halt_tx : 1; /* !< RW, Halt TX. 397 Values: 398 0x0 (DISABLED): Halt Transmission disabled 399 0x1 (ENABLED): Halt Transmission enabled */ 400 } halt_tx; 401 } halt_tx_t; 402 403 typedef union dma_sw_ack { 404 uint32_t d32; 405 struct { 406 uint32_t dma_sw_ack : 1; /* !< WC, DMA Software Acknowledge. 407 Values: 408 0x1 (SOFT_ACK): DMA software acknowledge */ 409 } dma_sw_ack; 410 } dma_sw_ack_t; 411 412 typedef union baud_ctl { 413 uint32_t d32; 414 struct { 415 uint32_t baud_div : 4; /* !< RW, Sample baud rate 416 Values: 417 0x7:baud rate is 8; 418 0xF:baud rate is 16; */ 419 uint32_t sample_phase : 4; /* !< RW, RX sample phase */ 420 } baud_ctl; 421 } baud_ctl_t; 422 423 typedef union stp_ctl { 424 uint32_t d32; 425 struct { 426 uint32_t rx_sp : 1; /* !< RW, Rx width control. 427 Only when stp_mode is asserted, this bit is valid. 428 Values: 429 0:1 stop bit. 430 1:1.5 stop bits when DLEN is zero, else 2 stop bit. */ 431 uint32_t tx_sp : 1; /* !< RW, Tx width control. 432 Only when stp_mode is asserted, this bit is valid. 433 Values: 434 0:1 stop bit. 435 1:1.5 stop bits when DLEN is zero, else 2 stop bit. */ 436 uint32_t stp_mode : 1; /* !< RW, Stop mode.When stp_mode is asserted,the stop width of TX and RX is controled 437 by CTL[7]. Else, the stop width of TX is controled by tx_sp, the stop width of RX is 438 controled by rx_sp. Value: 0:the stop width of TX and RX is controled by CTL[7]. 439 1:the stop width of TX is controled by tx_sp, the stop width of RX is controled 440 by rx_sp. */ 441 } stp_ctl; 442 } stp_ctl_t; 443 444 typedef union uart_parameter { 445 uint32_t d32; 446 struct { 447 uint32_t fifo_depth : 8; /* !< RO, UART TX/RX FIFO DEPTH.Values: 448 0x0 (FIFO_MODE_0): FIFO mode is 0 449 0x1 (FIFO_MODE_16): FIFO mode is 16 450 0x2 (FIFO_MODE_32): FIFO mode is 32 451 0x4 (FIFO_MODE_64): FIFO mode is 64 452 0x8 (FIFO_MODE_128): FIFO mode is 128 453 0x10 (FIFO_MODE_256): FIFO mode is 256 454 0x20 (FIFO_MODE_512): FIFO mode is 512 455 0x40 (FIFO_MODE_1024): FIFO mode is 1024 456 0x80 (FIFO_MODE_2048): FIFO mode is 2048 */ 457 uint32_t apb_data_width : 2; /* !< RO, Encoding of APB_DATA_WIDTH configuration parameter 458 value. 459 Values: 460 0x0 : APB data width is 8 bits 461 0x1 : APB data width is 16 bits 462 0x2 : APB data width is 32 bits */ 463 uint32_t afce_mode : 1; /* !< RO, Encoding of AFCE_MODE configuration parameter value. 464 Values: 465 0x0 (DISABLED): AFCE mode disabled 466 0x1 (ENABLED): AFCE mode enabled */ 467 uint32_t dma_mode : 1; /* !< RO, DMA_EXTRA 468 Values: 469 0x0 (DISABLED): DMA_EXTRA disabled 470 0x1 (ENABLED): DMA_EXTRA enabled */ 471 uint32_t shadow : 1; /* !< RO, Encoding of SHADOW configuration parameter value. 472 Values: 473 0x0 (DISABLED): SHADOW disabled 474 0x1 (ENABLED): SHADOW enabled */ 475 } uart_parameter; 476 } uart_parameter_t; 477 478 typedef union lp_ctl { 479 uint32_t d32; 480 struct { 481 uint32_t lp_req_en : 1; /* !< RW, Low power request enable.If this bit is set to 1, 482 uart_autocg_bypass must be set to 0; If this bit is 483 set to 0,uart_autocg_bypass must be set to 1. 484 Values: 485 0x0 (DISABLED): low power request disable 486 0x1 (ENABLED): low power request enable */ 487 } lp_ctl; 488 } lp_ctl_t; 489 490 typedef union receive_ctl { 491 uint32_t d32; 492 struct { 493 uint32_t receive_enable : 1; /* !< RW, This register is use to data reception while 494 FIFO_ACCESS equals to zero.Configrate this register 495 in the end of configuration process. 496 Values: 497 0x0 (DISABLED): data reception disable 498 0x1 (ENABLED): data reception enable */ 499 } receive_ctl; 500 } receive_ctl_t; 501 502 typedef struct uart_regs { 503 volatile uint32_t intr_id; 504 volatile uint32_t data; 505 volatile uint32_t uart_ctl; 506 volatile uint32_t div_h; 507 volatile uint32_t div_l; 508 volatile uint32_t div_fra; 509 volatile uint32_t intr_en; 510 volatile uint32_t intr_status; 511 volatile uint32_t reserved_20; 512 volatile uint32_t fifo_ctl; 513 volatile uint32_t far; 514 volatile uint32_t modem_ctl; 515 volatile uint32_t modem_status; 516 volatile uint32_t line_status; 517 volatile uint32_t uart_gp_reg; 518 volatile uint32_t tx_fifo_read; 519 volatile uint32_t rx_fifo_write; 520 volatile uint32_t fifo_status; 521 volatile uint32_t tx_fifo_cnt; 522 volatile uint32_t rx_fifo_cnt; 523 volatile uint32_t halt_tx; 524 volatile uint32_t dma_sw_ack; 525 volatile uint32_t baud_ctl; 526 volatile uint32_t stp_ctl; 527 volatile uint32_t uart_parameter; 528 #if defined(CONFIG_UART_IP_VERSION_V151_PRO) 529 volatile uint32_t lp_ctl; 530 volatile uint32_t receive_ctl; 531 #endif 532 } uart_reg_t; 533 534 535 typedef struct uart_regs1 { 536 volatile intr_id_t intr_id; 537 volatile data_t data; 538 volatile uart_ctl_t uart_ctl; 539 volatile div_h_t div_h; 540 volatile div_l_t div_l; 541 volatile div_fra_t div_fra; 542 volatile intr_en_t intr_en; 543 volatile intr_status_t intr_status; 544 volatile uint32_t reserved_20; 545 volatile fifo_ctl_t fifo_ctl; 546 volatile far_t far; 547 volatile modem_ctl_t modem_ctl; 548 volatile modem_status_t modem_status; 549 volatile line_status_t line_status; 550 volatile uart_gp_reg_t uart_gp_reg; 551 volatile tx_fifo_read_t tx_fifo_read; 552 volatile rx_fifo_write_t rx_fifo_write; 553 volatile fifo_status_t fifo_status; 554 volatile tx_fifo_cnt_t tx_fifo_cnt; 555 volatile rx_fifo_cnt_t rx_fifo_cnt; 556 volatile halt_tx_t halt_tx; 557 volatile dma_sw_ack_t dma_sw_ack; 558 volatile baud_ctl_t baud_ctl; 559 volatile stp_ctl_t stp_ctl; 560 volatile uart_parameter_t uart_parameter; 561 #if defined(CONFIG_UART_IP_VERSION_V151_PRO) 562 volatile lp_ctl_t lp_ctl; 563 volatile receive_ctl_t receive_ctl; 564 #endif 565 } uart_reg_1_t; 566 567 568 extern uart_reg_t *g_hal_uart_reg[UART_BUS_MAX_NUMBER]; 569 570 /** 571 * @brief Resets the uarts on the protocol and apps cores using the RESET_REG register 572 * The security core does not have that register, this function does nothing on 573 * the security core 574 * @param uart index 575 */ 576 void hal_uart_specific_reset_uart(uart_bus_t uart); 577 578 /** 579 * @brief Specific priority of IRQ associated with a UART 580 * @param uart Uart index 581 */ 582 void hal_uart_specific_priority_irq(uart_bus_t uart); 583 584 /** 585 * @brief Enable IRQ associated with a UART 586 * @param uart Uart index 587 */ 588 void hal_uart_specific_enable_irq(uart_bus_t uart); 589 590 /** 591 * @brief Disable IRQ associated with a UART 592 * @param uart Uart index 593 */ 594 void hal_uart_specific_disable_irq(uart_bus_t uart); 595 596 /** 597 * @brief Set IRQ associated with a UART pending 598 * @param uart Uart index 599 */ 600 void hal_uart_specific_set_pending_irq(uart_bus_t uart); 601 602 /** 603 * @} end of group DRIVER_HAL_UART 604 */ 605 606 #ifdef __cplusplus 607 #if __cplusplus 608 } 609 #endif /* __cplusplus */ 610 #endif /* __cplusplus */ 611 612 #endif 613