1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19 #include "drv_ifep_rsa_v100.h"
20 #include "drv_srsa.h"
21 #include "drv_trng.h"
22 #include "drv_klad.h"
23 #include "securec.h"
24
25 #ifdef CHIP_IFEP_RSA_VER_V100
26
27 /* Define the time out */
28 #define RSA_TIME_OUT 5000
29
30 /* rsa support rand mask or not */
31 #define RSA_SUB_VER_RAND_MASK 0x20160907
32 #define RSA_SUB_VER_NORMAL 0x00
33
34 /* crc 16 */
35 #define CRC16_TABLE_SIZE 256
36 #define U16_MSB 0x8000
37 #define BYTE_MASK 0xFF
38 #define CRC16_POLYNOMIAL 0x1021
39 #define BLOCK_BYTES 0x08
40
41 /* rsa work mode */
42 #define RSA_MODE_EXP 0x00
43 #define RSA_MODE_CLEAR_RAM 0x02
44
45 /* rsa already initialize or not */
46 static hi_u32 g_rsa_initialize = HI_FALSE;
47
48 /* Define the context of rsa */
49 typedef struct {
50 hi_u32 rsa_sub_ver;
51 hi_u32 done; /* calculation finish flag. */
52 CRYPTO_QUEUE_HEAD queue; /* queue list */
53 } rsa_hard_context;
54
55 static rsa_hard_context g_rsa_info;
56 /* ****************************** API Declaration **************************** */
57 #ifdef RSA_RAND_MASK
58
59 static hi_u16 g_crc_table[CRC16_TABLE_SIZE] = {0};
60
drv_rsa_crc16_init(hi_void)61 static hi_void drv_rsa_crc16_init(hi_void)
62 {
63 hi_u16 remainder;
64 hi_u16 n, m;
65 hi_u16 *local_crc_table = g_crc_table;
66
67 for (n = 0; n < CRC16_TABLE_SIZE; n++) {
68 remainder = (hi_u16)n << BITS_IN_BYTE;
69 for (m = BITS_IN_BYTE; m > 0; m--) {
70 if (remainder & U16_MSB) {
71 remainder = (remainder << 1) ^ CRC16_POLYNOMIAL;
72 } else {
73 remainder = (remainder << 1);
74 }
75 }
76 *(local_crc_table + n) = remainder;
77 }
78 }
79
drv_rsa_crc16_block(hi_u16 crc,const hi_u8 block[BLOCK_BYTES],const hi_u8 rand_num[BLOCK_BYTES])80 static hi_u16 drv_rsa_crc16_block(hi_u16 crc,
81 const hi_u8 block[BLOCK_BYTES], const hi_u8 rand_num[BLOCK_BYTES])
82 {
83 hi_u8 i, j;
84 hi_u8 val;
85
86 for (i = 0; i < BLOCK_BYTES / WORD_WIDTH; i++) {
87 for (j = 0; j < WORD_WIDTH; j++) {
88 val = block[i * WORD_WIDTH + WORD_IDX_3 - j] ^ rand_num[i * WORD_WIDTH + WORD_IDX_3 - j];
89 crc = (crc << BITS_IN_BYTE) ^ g_crc_table[((crc >> BITS_IN_BYTE) ^ val) & BYTE_MASK];
90 }
91 }
92 return crc;
93 }
94
drv_rsa_key_crc(const hi_u8 * n,const hi_u8 * k,hi_u32 klen,const hi_u32 randnum[MUL_VAL_2])95 static hi_u16 drv_rsa_key_crc(const hi_u8 *n, const hi_u8 *k, hi_u32 klen, const hi_u32 randnum[MUL_VAL_2])
96 {
97 hi_u32 i;
98 hi_u16 crc = 0;
99
100 for (i = 0; i < klen; i += BLOCK_BYTES) {
101 crc = drv_rsa_crc16_block(crc, n + i, (hi_u8 *)randnum);
102 }
103 for (i = 0; i < klen; i += BLOCK_BYTES) {
104 crc = drv_rsa_crc16_block(crc, k + i, (hi_u8 *)randnum);
105 }
106 return crc;
107 }
108 #endif
109
110 #ifdef CRYPTO_OS_INT_SUPPORT
111
112 /* set interrupt */
rsa_set_interrupt(hi_void)113 static hi_void rsa_set_interrupt(hi_void)
114 {
115 hi_u32 int_valid = 0;
116 hi_u32 int_num = 0;
117 sec_rsa_int_en int_en;
118
119 module_get_attr(CRYPTO_MODULE_ID_IFEP_RSA, &int_valid, &int_num, HI_NULL);
120 if (int_valid == HI_FALSE) {
121 return;
122 }
123 if (g_rsa_info.rsa_sub_ver != RSA_SUB_VER_RAND_MASK) {
124 return;
125 }
126
127 int_en.u32 = ifep_rsa_read(REG_SEC_RSA_INT_EN);
128
129 /* The top interrupt switch only can be enable/disable by secure CPU. */
130 int_en.bits.rsa_int_en = 1;
131 int_en.bits.int_en = 1;
132 ifep_rsa_write(REG_SEC_RSA_INT_EN, int_en.u32);
133 hi_log_info("RSA_INT_EN: 0x%x\n", int_en.u32);
134
135 return;
136 }
137
drv_rsa_done_notify(hi_void)138 static hi_void drv_rsa_done_notify(hi_void)
139 {
140 sec_rsa_int_status int_st;
141 sec_rsa_int_raw int_raw;
142
143 int_st.u32 = ifep_rsa_read(REG_SEC_RSA_INT_STATUS);
144 int_raw.u32 = 0x00;
145
146 hi_log_debug("REG_SEC_RSA_INT_STATUS: 0x%x\n", int_st.u32);
147 crypto_unused(int_st.u32);
148
149 /* Clean raw interrupt. */
150 int_raw.bits.rsa_int_raw = RSA_INT_RAW_CLR;
151 ifep_rsa_write(REG_SEC_RSA_INT_RAW, int_raw.u32);
152
153 /* Clean error interrupt. */
154 ifep_rsa_write(REG_SEC_RSA_INT_ERR_CLR, RSA_INT_ERR_CLR);
155 }
156
157 /* rsa interrupt process function */
drv_rsa_interrupt_isr(hi_s32 irq,hi_void * dev_id)158 static CRYPTO_IRQRETURN_T drv_rsa_interrupt_isr(hi_s32 irq, hi_void *dev_id)
159 {
160 crypto_unused(irq);
161 crypto_unused(dev_id);
162
163 drv_rsa_done_notify();
164
165 g_rsa_info.done = HI_TRUE;
166 hi_log_debug("rsa wake up\n");
167 crypto_queue_wait_up(&g_rsa_info.queue);
168
169 return IRQ_HANDLED;
170 }
171
172 /* rsa register interrupt process function */
drv_rsa_register_interrupt(hi_void)173 static hi_s32 drv_rsa_register_interrupt(hi_void)
174 {
175 hi_s32 ret;
176 hi_u32 int_valid = 0;
177 hi_u32 int_num = 0;
178 const char *name = HI_NULL;
179
180 hi_log_func_enter();
181
182 module_get_attr(CRYPTO_MODULE_ID_IFEP_RSA, &int_valid, &int_num, &name);
183 if (int_valid == HI_FALSE) {
184 return HI_SUCCESS;
185 }
186 if (g_rsa_info.rsa_sub_ver != RSA_SUB_VER_RAND_MASK) {
187 return HI_SUCCESS;
188 }
189
190 /* request irq */
191 ret = crypto_request_irq(int_num, drv_rsa_interrupt_isr, name);
192 if (ret != HI_SUCCESS) {
193 hi_log_error("Irq request failure, irq = %u", int_num);
194 hi_log_print_err_code(HI_ERR_CIPHER_REGISTER_IRQ);
195 return ret;
196 }
197
198 /* initialize queue list. */
199 crypto_queue_init(&g_rsa_info.queue);
200
201 hi_log_func_exit();
202 return HI_SUCCESS;
203 }
204
205 /* rsa unregister interrupt process function */
drv_rsa_unregister_interrupt(hi_void)206 static hi_void drv_rsa_unregister_interrupt(hi_void)
207 {
208 hi_u32 int_valid = 0;
209 hi_u32 int_num = 0;
210 const char *name = HI_NULL;
211
212 hi_log_func_enter();
213
214 module_get_attr(CRYPTO_MODULE_ID_IFEP_RSA, &int_valid, &int_num, &name);
215
216 if (int_valid == HI_FALSE) {
217 return;
218 }
219
220 if (g_rsa_info.rsa_sub_ver != RSA_SUB_VER_RAND_MASK) {
221 return;
222 }
223
224 /* free irq */
225 hi_log_info("rsa free irq, num %u, name %s\n", int_num, name);
226 crypto_free_irq(int_num, name);
227
228 hi_log_func_exit();
229 }
230 #endif
231
drv_rsa_init(hi_void)232 hi_s32 drv_rsa_init(hi_void)
233 {
234 hi_log_func_enter();
235
236 hi_log_info("enable rsa\n");
237
238 if (g_rsa_initialize == HI_TRUE) {
239 return HI_SUCCESS;
240 }
241
242 #ifdef RSA_RAND_MASK
243 drv_rsa_crc16_init();
244 #endif
245
246 module_enable(CRYPTO_MODULE_ID_IFEP_RSA);
247
248 /* RSA request the TRNG must valid */
249 module_enable(CRYPTO_MODULE_ID_TRNG);
250
251 g_rsa_info.rsa_sub_ver = ifep_rsa_read(REG_SEC_RSA_VERSION_ID);
252 hi_log_info("rsa version 0x%x\n", g_rsa_info.rsa_sub_ver);
253 module_disable(CRYPTO_MODULE_ID_IFEP_RSA);
254
255 #ifdef CRYPTO_OS_INT_SUPPORT
256 {
257 hi_s32 ret;
258
259 hi_log_info("rsa register interrupt function\n");
260 ret = drv_rsa_register_interrupt();
261 if (ret != HI_SUCCESS) {
262 hi_log_error("error, register interrupt failed\n");
263 hi_log_print_func_err(drv_rsa_register_interrupt, ret);
264 return ret;
265 }
266 }
267 #endif
268
269 g_rsa_initialize = HI_TRUE;
270
271 hi_log_func_exit();
272 return HI_SUCCESS;
273 }
274
drv_rsa_deinit(hi_void)275 hi_s32 drv_rsa_deinit(hi_void)
276 {
277 hi_log_func_enter();
278
279 if (g_rsa_initialize == HI_FALSE) {
280 return HI_SUCCESS;
281 }
282
283 #ifdef CRYPTO_OS_INT_SUPPORT
284 drv_rsa_unregister_interrupt();
285 #endif
286
287 g_rsa_initialize = HI_FALSE;
288
289 hi_log_func_exit();
290 return HI_SUCCESS;
291 }
292
drv_rsa_resume(hi_void)293 static hi_void drv_rsa_resume(hi_void)
294 {
295 hi_log_func_enter();
296
297 module_enable(CRYPTO_MODULE_ID_IFEP_RSA);
298
299 #ifdef CRYPTO_OS_INT_SUPPORT
300 hi_log_info("RSA interrupt configure\n");
301 rsa_set_interrupt();
302 #endif
303
304 hi_log_func_exit();
305 return;
306 }
307
drv_rsa_suspend(hi_void)308 static hi_void drv_rsa_suspend(hi_void)
309 {
310 hi_log_func_enter();
311
312 module_disable(CRYPTO_MODULE_ID_IFEP_RSA);
313
314 hi_log_func_exit();
315 return;
316 }
317
drv_rsa_set_width(rsa_key_width width)318 static hi_void drv_rsa_set_width(rsa_key_width width)
319 {
320 sec_rsa_mod_reg ctrl;
321
322 ctrl.u32 = 0x00;
323 ctrl.bits.sec_rsa_mod_sel = RSA_MODE_EXP;
324 ctrl.bits.sec_rsa_key_width = width;
325 ifep_rsa_write(REG_SEC_RSA_MOD_REG, ctrl.u32);
326 hi_log_info("REG_SEC_RSA_MOD_REG 0x%x\n", ctrl.u32);
327 return;
328 }
329
drv_rsa_set_key(hi_u32 ca_type,const hi_u8 * n,const hi_u8 * d,hi_u32 klen,const hi_u32 random[MUL_VAL_2])330 static hi_s32 drv_rsa_set_key(hi_u32 ca_type,
331 const hi_u8 *n, const hi_u8 *d, hi_u32 klen, const hi_u32 random[MUL_VAL_2])
332 {
333 hi_u32 i;
334 hi_u32 id = 0;
335 hi_u32 val = 0x00;
336 hi_s32 ret;
337
338 /*
339 * The even word shell XOR with even random[0]
340 * The odd word shell XOR with odd random[1]
341 * The random may be zero.
342 * Must set N before set E.
343 * The E must padding with zero.
344 */
345 for (i = 0; i < klen; i += WORD_WIDTH) {
346 /* Set N */
347 if (memcpy_s(&val, sizeof(hi_u32), n + i, WORD_WIDTH) != EOK) {
348 hi_log_print_func_err(memcpy_s, HI_ERR_CIPHER_MEMCPY_S_FAILED);
349 return HI_ERR_CIPHER_MEMCPY_S_FAILED;
350 }
351 val ^= random[id];
352 ifep_rsa_write(REG_SEC_RSA_WSEC_REG, val);
353
354 /* switch between even and odd */
355 id ^= 0x01;
356 }
357
358 /* Set D */
359 if (ca_type != HI_CIPHER_KEY_SRC_USER) {
360 ret = drv_cipher_klad_load_key(0, ca_type, HI_CIPHER_KLAD_TARGET_RSA, d, klen);
361 if (ret != HI_SUCCESS) {
362 hi_log_print_func_err(drv_cipher_klad_load_key, ret);
363 return ret;
364 }
365 } else {
366 for (i = 0; i < klen; i += WORD_WIDTH) {
367 if (memcpy_s(&val, sizeof(hi_u32), d + i, WORD_WIDTH) != EOK) {
368 hi_log_print_func_err(memcpy_s, HI_ERR_CIPHER_MEMCPY_S_FAILED);
369 return HI_ERR_CIPHER_MEMCPY_S_FAILED;
370 }
371 val ^= random[id];
372 ifep_rsa_write(REG_SEC_RSA_WSEC_REG, val);
373
374 /* switch between even and odd */
375 id ^= 0x01;
376 }
377 }
378 return HI_SUCCESS;
379 }
380
drv_rsa_set_input(const hi_u8 * in,hi_u32 klen)381 static hi_void drv_rsa_set_input(const hi_u8 *in, hi_u32 klen)
382 {
383 hi_u32 i;
384 hi_u32 val = 0x00;
385
386 for (i = 0; i < klen; i += WORD_WIDTH) {
387 if (memcpy_s(&val, sizeof(hi_u32), in + i, WORD_WIDTH) != EOK) {
388 hi_log_print_func_err(memcpy_s, HI_ERR_CIPHER_MEMCPY_S_FAILED);
389 return;
390 }
391 ifep_rsa_write(REG_SEC_RSA_WDAT_REG, val);
392 }
393 return;
394 }
395
drv_rsa_get_output(hi_u8 * out,hi_u32 klen)396 static hi_void drv_rsa_get_output(hi_u8 *out, hi_u32 klen)
397 {
398 hi_u32 i;
399 hi_u32 val;
400
401 for (i = 0; i < klen; i += WORD_WIDTH) {
402 val = ifep_rsa_read(REG_SEC_RSA_RRSLT_REG);
403 if (memcpy_s(out + i, sizeof(hi_u32), &val, sizeof(hi_u32)) != EOK) {
404 hi_log_print_func_err(memcpy_s, HI_ERR_CIPHER_MEMCPY_S_FAILED);
405 return;
406 }
407 }
408 }
409
drv_rsa_get_klen(rsa_key_width width)410 static hi_u32 drv_rsa_get_klen(rsa_key_width width)
411 {
412 hi_u32 klen;
413
414 /* nonsupport rsa 3072, can compute it as 4096 */
415 switch (width) {
416 case RSA_KEY_WIDTH_1024: {
417 klen = RSA_KEY_LEN_1024;
418 break;
419 }
420 case RSA_KEY_WIDTH_2048: {
421 klen = RSA_KEY_LEN_2048;
422 break;
423 }
424 case RSA_KEY_WIDTH_3072: {
425 klen = RSA_KEY_LEN_3072;
426 break;
427 }
428 case RSA_KEY_WIDTH_4096: {
429 klen = RSA_KEY_LEN_4096;
430 break;
431 }
432 default: {
433 hi_log_error("error, nonsupport RSA width %d\n", width);
434 klen = 0;
435 break;
436 }
437 }
438
439 return klen;
440 }
441
drv_rsa_start(hi_void)442 static hi_void drv_rsa_start(hi_void)
443 {
444 sec_rsa_start_reg start;
445
446 hi_log_func_enter();
447
448 g_rsa_info.done = HI_FALSE;
449
450 start.u32 = 0x00;
451
452 if (g_rsa_info.rsa_sub_ver == RSA_SUB_VER_RAND_MASK) {
453 start.bits.sec_rsa_start_reg = 0x05;
454 } else {
455 start.bits.sec_rsa_start_reg = 0x01;
456 }
457
458 ifep_rsa_write(REG_SEC_RSA_START_REG, start.u32);
459 hi_log_info("REG_SEC_RSA_START_REG 0x%x\n", start.u32);
460
461 hi_log_func_exit();
462
463 return;
464 }
465
drv_rsa_wait_done(hi_void)466 static hi_s32 drv_rsa_wait_done(hi_void)
467 {
468 hi_u32 int_valid = 0;
469 hi_u32 int_num = 0;
470 hi_u32 i;
471 sec_rsa_busy_reg ready;
472 const char *name = HI_NULL;
473
474 hi_log_func_enter();
475
476 module_get_attr(CRYPTO_MODULE_ID_IFEP_RSA, &int_valid, &int_num, &name);
477
478 #ifdef CRYPTO_OS_INT_SUPPORT
479 /* interrupt support, wait irq. */
480 if ((g_rsa_info.rsa_sub_ver == RSA_SUB_VER_RAND_MASK) && (int_valid == HI_TRUE)) {
481 hi_s32 ret;
482
483 /* wait interrupt */
484 ret = crypto_queue_wait_timeout(g_rsa_info.queue, &g_rsa_info.done, RSA_TIME_OUT);
485 if ((ret <= 0x00) && (ret != -ERESTARTSYS)) {
486 hi_log_error("wait done timeout\n");
487 hi_log_print_func_err(crypto_queue_wait_timeout, ret);
488 return HI_ERR_CIPHER_TIMEOUT;
489 }
490 } else {
491 /* wait ready */
492 for (i = 0; i < RSA_TIME_OUT; i++) {
493 ready.u32 = ifep_rsa_read(REG_SEC_RSA_BUSY_REG);
494 if (!ready.bits.sec_rsa_busy_reg) {
495 break;
496 }
497 crypto_msleep(1);
498 }
499
500 if (i >= RSA_TIME_OUT) {
501 hi_log_error("error, rsa wait free timeout\n");
502 hi_log_print_err_code(HI_ERR_CIPHER_TIMEOUT);
503 return HI_ERR_CIPHER_TIMEOUT;
504 }
505 }
506 #else
507 /* wait ready */
508 for (i = 0; i < RSA_TIME_OUT; i++) {
509 ready.u32 = ifep_rsa_read(REG_SEC_RSA_BUSY_REG);
510 if (!ready.bits.sec_rsa_busy_reg) {
511 break;
512 }
513 crypto_msleep(1);
514 }
515
516 if (i >= RSA_TIME_OUT) {
517 hi_log_error("error, rsa wait free timeout\n");
518 hi_log_print_err_code(HI_ERR_CIPHER_TIMEOUT);
519 return HI_ERR_CIPHER_TIMEOUT;
520 }
521 #endif
522 hi_log_func_exit();
523 return HI_SUCCESS;
524 }
525
drv_rsa_randnum(const hi_u8 * n,const hi_u8 * k,hi_u32 klen,hi_u32 random[MUL_VAL_2])526 static hi_void drv_rsa_randnum(const hi_u8 *n, const hi_u8 *k, hi_u32 klen, hi_u32 random[MUL_VAL_2])
527 {
528 hi_log_func_enter();
529
530 #ifdef RSA_RAND_MASK
531 if (g_rsa_info.rsa_sub_ver == RSA_SUB_VER_RAND_MASK) {
532 hi_u16 crc16;
533
534 random[0] = get_rand();
535 random[1] = get_rand();
536
537 crc16 = drv_rsa_key_crc(n, k, klen, random);
538 hi_log_info("random 0x%x 0x%x, CRC16: 0x%x\n", random[WORD_IDX_0], random[WORD_IDX_1], crc16);
539 ifep_rsa_write(REG_SEC_RSA_KEY_RANDOM_1, random[WORD_IDX_0]);
540 ifep_rsa_write(REG_SEC_RSA_KEY_RANDOM_2, random[WORD_IDX_1]);
541 ifep_rsa_write(REG_SEC_RSA_CRC16_REG, crc16);
542 } else {
543 random[WORD_IDX_0] = 0x00;
544 random[WORD_IDX_1] = 0x00;
545 }
546 #else
547 crypto_unused(n);
548 crypto_unused(k);
549 crypto_unused(klen);
550 random[WORD_IDX_0] = 0x00;
551 random[WORD_IDX_1] = 0x00;
552 #endif
553 hi_log_func_exit();
554 }
555
drv_rsa_clean_ram(hi_void)556 static hi_s32 drv_rsa_clean_ram(hi_void)
557 {
558 hi_s32 ret;
559 sec_rsa_mod_reg ctrl;
560
561 ctrl.u32 = ifep_rsa_read(REG_SEC_RSA_MOD_REG);
562 ctrl.bits.sec_rsa_mod_sel = RSA_MODE_CLEAR_RAM;
563 ctrl.bits.sec_rsa_data0_clr = RSA_CLR_RAM_STORED_KEY;
564 ctrl.bits.sec_rsa_data1_clr = RSA_CLR_RAM_STORED_MSG;
565 ctrl.bits.sec_rsa_data2_clr = RSA_CLR_RAM_STORED_RESULT;
566 ifep_rsa_write(REG_SEC_RSA_MOD_REG, ctrl.u32);
567
568 /* start */
569 drv_rsa_start();
570
571 /* wait done */
572 ret = drv_rsa_wait_done();
573 if (ret != HI_SUCCESS) {
574 hi_log_print_func_err(drv_rsa_wait_done, ret);
575 return ret;
576 }
577
578 return HI_SUCCESS;
579 }
580
drv_rsa_error_code(hi_void)581 static hi_s32 drv_rsa_error_code(hi_void)
582 {
583 hi_log_func_enter();
584
585 if (g_rsa_info.rsa_sub_ver == RSA_SUB_VER_RAND_MASK) {
586 hi_u32 code;
587
588 code = ifep_rsa_read(REG_SEC_RSA_ERROR_REG);
589 if (code != 0) {
590 hi_log_error("rsa error code: 0x%x.\n", code);
591 hi_log_print_err_code(HI_ERR_CIPHER_HARD_STATUS);
592 return HI_ERR_CIPHER_HARD_STATUS;
593 }
594 }
595
596 hi_log_func_exit();
597 return HI_SUCCESS;
598 }
599
drv_ifep_rsa_exp_mod(hi_u32 ca_type,const hi_u8 * n,const hi_u8 * k,const hi_u8 * in,hi_u8 * out,rsa_key_width width)600 hi_s32 drv_ifep_rsa_exp_mod(hi_u32 ca_type, const hi_u8 *n, const hi_u8 *k,
601 const hi_u8 *in, hi_u8 *out, rsa_key_width width)
602 {
603 hi_s32 ret, ret_exit;
604 hi_u32 klen;
605 hi_u32 random[MUL_VAL_2] = {0, 0};
606
607 hi_log_func_enter();
608
609 hi_log_chk_init_err_return(g_rsa_initialize);
610
611 klen = drv_rsa_get_klen(width);
612 if (klen == 0) {
613 return HI_ERR_CIPHER_INVALID_PARAM;
614 }
615
616 drv_rsa_resume();
617
618 /* set rsa width */
619 drv_rsa_set_width(width);
620
621 /* config randnum */
622 drv_rsa_randnum(n, k, klen, random);
623
624 /* set rsa key */
625 ret = drv_rsa_set_key(ca_type, n, k, klen, random);
626 if (ret != HI_SUCCESS) {
627 hi_log_print_func_err(drv_rsa_set_key, ret);
628 ret = HI_ERR_CIPHER_ILLEGAL_KEY;
629 goto exit;
630 }
631
632 /* set input data */
633 drv_rsa_set_input(in, klen);
634
635 /* start */
636 drv_rsa_start();
637
638 /* wait done */
639 ret = drv_rsa_wait_done();
640 if (ret != HI_SUCCESS) {
641 hi_log_print_func_err(drv_rsa_wait_done, ret);
642 ret = HI_ERR_CIPHER_TIMEOUT;
643 goto exit;
644 }
645
646 /* get input data */
647 drv_rsa_get_output(out, klen);
648
649 ret = drv_rsa_error_code();
650 exit:
651 /* clean key and data */
652 ret_exit = drv_rsa_clean_ram();
653 if (ret_exit != HI_SUCCESS) {
654 hi_log_print_func_err(drv_rsa_clean_ram, ret_exit);
655 }
656
657 drv_rsa_suspend();
658
659 hi_log_func_exit();
660
661 return ret;
662 }
663
drv_ifep_rsa_get_capacity(rsa_capacity * capacity)664 hi_void drv_ifep_rsa_get_capacity(rsa_capacity *capacity)
665 {
666 (hi_void)memset_s(capacity, sizeof(rsa_capacity), 0, sizeof(rsa_capacity));
667
668 capacity->rsa = CRYPTO_CAPACITY_SUPPORT;
669
670 return;
671 }
672 #endif /* End of CHIP_RSA_VER_V100 */
673