1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19 #include "hifb_graphic_hal.h"
20 #include "hi_osal.h"
21 #include "hi_debug.h"
22 #include "hifb_coef.h"
23 #include "mddrc_reg.h"
24 #include "hi_math.h"
25 #include "hifb_def.h"
26
27 /* MACRO DEFINITION */
28 #define HAL_PRINT HI_PRINT
29
30 #define DDRC_BASE_ADDR 0x04605000
31 #define VOU_REGS_ADDR 0x11440000
32 #define VOU_REGS_SIZE 0x40000
33
34 /* For CMP and DCMP */
35 #define CMP_SEG_OFFSET (0x80 / 4)
36 #define DCMP_SEG_OFFSET (0x20 / 4)
37
38 /* EXTERN VARIABLES */
39 #ifdef CONFIG_HIFB_SOFT_IRQ_SUPPORT
40 #define SYS_REGS_ADDR 0X12020000
41
42 typedef union {
43 struct {
44 unsigned int software_int : 1; /* [0] */
45 unsigned int reserved : 31; /* [1 ~31] */
46 } bits;
47 unsigned int u32;
48 } u_sys_reg;
49
50 typedef struct {
51 volatile hi_u32 reserved[7]; /* 0x0~0x18, reserved 7 num register */
52 volatile u_sys_reg soft_int; /* 0x1c */
53 volatile hi_u32 reserved1; /* 0x20 */
54 } s_sys_regs_type;
55
56 volatile s_sys_regs_type *g_sys_reg = HI_NULL;
57 #endif
58
59 volatile s_vdp_regs_type *g_hifb_reg = HI_NULL;
60 volatile mddrc_regs *g_mddrc_reg = HI_NULL;
61
fb_hal_vou_init(hi_void)62 hi_s32 fb_hal_vou_init(hi_void)
63 {
64 if (g_hifb_reg == HI_NULL) {
65 g_hifb_reg = (volatile s_vdp_regs_type *)osal_ioremap(VOU_REGS_ADDR, (hi_u32)VOU_REGS_SIZE);
66 }
67 #ifdef CONFIG_HIFB_SOFT_IRQ_SUPPORT
68 if (g_sys_reg == HI_NULL) {
69 g_sys_reg = (volatile s_sys_regs_type *)osal_ioremap(SYS_REGS_ADDR, (hi_u32)sizeof(s_sys_regs_type));
70 }
71 #endif
72 if (g_hifb_reg == HI_NULL) {
73 osal_printk("ioremap_nocache failed\n");
74 return HI_FAILURE;
75 }
76 #ifdef CONFIG_HIFB_SOFT_IRQ_SUPPORT
77 if (g_sys_reg == HI_NULL) {
78 osal_printk("ioremap_nocache failed\n");
79 return HI_FAILURE;
80 }
81 #endif
82 return HI_SUCCESS;
83 }
84
fb_hal_vou_exit(hi_void)85 hi_void fb_hal_vou_exit(hi_void)
86 {
87 if (g_hifb_reg != HI_NULL) {
88 osal_iounmap((void *)g_hifb_reg, VOU_REGS_SIZE);
89 g_hifb_reg = HI_NULL;
90 }
91 #ifdef CONFIG_HIFB_SOFT_IRQ_SUPPORT
92 if (g_sys_reg != HI_NULL) {
93 osal_iounmap((void *)g_sys_reg, sizeof(s_sys_regs_type));
94 g_sys_reg = HI_NULL;
95 }
96 #endif
97 }
98
fb_hal_write_reg(hi_u32 * address,hi_u32 value)99 hi_void fb_hal_write_reg(hi_u32 *address, hi_u32 value)
100 {
101 if (address == HI_NULL) {
102 return;
103 }
104 *(volatile hi_u32 *)address = value;
105 return;
106 }
107
fb_hal_read_reg(hi_u32 * address)108 hi_u32 fb_hal_read_reg(hi_u32 *address)
109 {
110 if (address == HI_NULL) {
111 return 0;
112 }
113 return *(volatile hi_u32 *)(address);
114 }
115
116 /*
117 * Prototype : fb_vou_get_abs_addr
118 * Description : Get the absolute address of the layer (video layer and graphics layer)
119 */
fb_vou_get_abs_addr(hal_disp_layer layer,hi_ulong reg)120 hi_ulong fb_vou_get_abs_addr(hal_disp_layer layer, hi_ulong reg)
121 {
122 hi_ulong reg_abs_addr;
123
124 switch (layer) {
125 case HAL_DISP_LAYER_VHD0:
126 case HAL_DISP_LAYER_VHD1:
127 case HAL_DISP_LAYER_VHD2:
128 reg_abs_addr = (reg) + (layer - HAL_DISP_LAYER_VHD0) * VHD_REGS_LEN;
129 break;
130 case HAL_DISP_LAYER_GFX0:
131 case HAL_DISP_LAYER_GFX1:
132 case HAL_DISP_LAYER_GFX3:
133 reg_abs_addr = (reg) + (layer - HAL_DISP_LAYER_GFX0) * GFX_REGS_LEN;
134 break;
135 /* one wbc dev */
136 case HAL_DISP_LAYER_WBC:
137 reg_abs_addr = (reg);
138 break;
139 default:
140 HAL_PRINT("Error channel id found in %s: L%d\n", __FUNCTION__, __LINE__);
141 return 0;
142 }
143
144 return reg_abs_addr;
145 }
146
147 /*
148 * Prototype : fb_vou_get_chn_abs_addr
149 * Description : Get the absolute address of the video channel
150 */
fb_vou_get_chn_abs_addr(hal_disp_outputchannel chan,hi_ulong reg)151 hi_ulong fb_vou_get_chn_abs_addr(hal_disp_outputchannel chan, hi_ulong reg)
152 {
153 volatile hi_ulong reg_abs_addr;
154
155 switch (chan) {
156 case HAL_DISP_CHANNEL_DHD0:
157 case HAL_DISP_CHANNEL_DHD1:
158 reg_abs_addr = reg + (chan - HAL_DISP_CHANNEL_DHD0) * DHD_REGS_LEN;
159 break;
160 default:
161 HAL_PRINT("Error channel id found in %s: L%d\n", __FUNCTION__, __LINE__);
162 return 0;
163 }
164
165 return reg_abs_addr;
166 }
167
hal_get_addr_chnabs(hal_disp_outputchannel chan,volatile hi_u32 * value)168 static hi_u32 hal_get_addr_chnabs(hal_disp_outputchannel chan, volatile hi_u32 *value)
169 {
170 volatile hi_ulong addr_reg;
171 addr_reg = fb_vou_get_chn_abs_addr(chan, (hi_ulong)(uintptr_t)value);
172 return fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
173 }
174
hal_get_addr_abs(volatile hi_ulong * addr_reg,hal_disp_layer layer,volatile hi_u32 * value)175 static hi_u32 hal_get_addr_abs(volatile hi_ulong *addr_reg, hal_disp_layer layer, volatile hi_u32 *value)
176 {
177 *addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)value);
178 return fb_hal_read_reg ((hi_u32 *)(uintptr_t)(*addr_reg));
179 }
180
fb_vou_get_gfx_abs_addr(hal_disp_layer layer,hi_ulong reg)181 hi_ulong fb_vou_get_gfx_abs_addr(hal_disp_layer layer, hi_ulong reg)
182 {
183 volatile hi_ulong reg_abs_addr;
184
185 switch (layer) {
186 case HAL_DISP_LAYER_GFX0:
187 case HAL_DISP_LAYER_GFX1:
188 case HAL_DISP_LAYER_GFX3:
189 reg_abs_addr = reg + (layer - HAL_DISP_LAYER_GFX0) * GRF_REGS_LEN;
190 break;
191
192 default:
193 HAL_PRINT("Error layer id found in FUNC:%s,LINE:%d\n", __FUNCTION__, __LINE__);
194 return 0;
195 }
196
197 return reg_abs_addr;
198 }
199
200 /*
201 * Name : fb_hal_disp_get_intf_enable
202 * Desc : Get the status (enable,disable status) of display interface.
203 */
fb_hal_disp_get_intf_enable(hal_disp_outputchannel chan,hi_bool * intf_en)204 hi_bool fb_hal_disp_get_intf_enable(hal_disp_outputchannel chan, hi_bool *intf_en)
205 {
206 volatile u_dhd0_ctrl dhd0_ctrl;
207 volatile hi_ulong addr_reg;
208
209 switch (chan) {
210 case HAL_DISP_CHANNEL_DHD0:
211 case HAL_DISP_CHANNEL_DHD1:
212 addr_reg = fb_vou_get_chn_abs_addr(chan, (hi_ulong)(uintptr_t)&(g_hifb_reg->dhd0_ctrl.u32));
213 dhd0_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
214 *intf_en = dhd0_ctrl.bits.intf_en;
215 break;
216 default:
217 HAL_PRINT("Error channel id found in %s: L%d\n", __FUNCTION__, __LINE__);
218 return HI_FALSE;
219 }
220
221 return HI_TRUE;
222 }
223
hal_disp_get_intf_sync(hal_disp_outputchannel chan,hal_disp_syncinfo * sync_info)224 hi_bool hal_disp_get_intf_sync(hal_disp_outputchannel chan, hal_disp_syncinfo *sync_info)
225 {
226 volatile u_dhd0_ctrl dhd0_ctrl;
227 volatile u_dhd0_vsync1 dhd0_vsync1;
228 volatile u_dhd0_vsync2 dhd0_vsync2;
229 volatile u_dhd0_hsync1 dhd0_hsync1;
230 volatile u_dhd0_hsync2 dhd0_hsync2;
231 volatile u_dhd0_vplus1 dhd0_vplus1;
232 volatile u_dhd0_vplus2 dhd0_vplus2;
233 volatile u_dhd0_pwr dhd0_pwr;
234 switch (chan) {
235 case HAL_DISP_CHANNEL_DHD0:
236 case HAL_DISP_CHANNEL_DHD1: {
237 dhd0_ctrl.u32 = hal_get_addr_chnabs(chan, &(g_hifb_reg->dhd0_ctrl.u32));
238 sync_info->iop = dhd0_ctrl.bits.iop;
239
240 dhd0_hsync1.u32 = hal_get_addr_chnabs(chan, &(g_hifb_reg->dhd0_hsync1.u32));
241 sync_info->hact = dhd0_hsync1.bits.hact + 1;
242 sync_info->hbb = dhd0_hsync1.bits.hbb + 1;
243
244 dhd0_hsync2.u32 = hal_get_addr_chnabs(chan, &(g_hifb_reg->dhd0_hsync2.u32));
245 sync_info->hmid = (dhd0_hsync2.bits.hmid == 0) ? 0 : dhd0_hsync2.bits.hmid + 1;
246 sync_info->hfb = dhd0_hsync2.bits.hfb + 1;
247
248 /* Config VHD interface vertical timing */
249 dhd0_vsync1.u32 = hal_get_addr_chnabs(chan, &(g_hifb_reg->dhd0_vsync1.u32));
250 sync_info->vact = dhd0_vsync1.bits.vact + 1;
251 sync_info->vbb = dhd0_vsync1.bits.vbb + 1;
252
253 dhd0_vsync2.u32 = hal_get_addr_chnabs(chan, &(g_hifb_reg->dhd0_vsync2.u32));
254 sync_info->vfb = dhd0_vsync2.bits.vfb + 1;
255
256 /* Config VHD interface vertical bottom timing,no use in progressive mode */
257 dhd0_vplus1.u32 = hal_get_addr_chnabs(chan, &(g_hifb_reg->dhd0_vplus1.u32));
258 sync_info->bvact = dhd0_vplus1.bits.bvact + 1;
259 sync_info->bvbb = dhd0_vplus1.bits.bvbb + 1;
260
261 dhd0_vplus2.u32 = hal_get_addr_chnabs(chan, &(g_hifb_reg->dhd0_vplus2.u32));
262 sync_info->bvfb = dhd0_vplus2.bits.bvfb + 1;
263
264 /* Config VHD interface vertical bottom timing, */
265 dhd0_pwr.u32 = hal_get_addr_chnabs(chan, &(g_hifb_reg->dhd0_pwr.u32));
266 sync_info->hpw = dhd0_pwr.bits.hpw + 1;
267 sync_info->vpw = dhd0_pwr.bits.vpw + 1;
268 break;
269 }
270 default: {
271 HAL_PRINT("Error channel id found in %s: L%d\n", __FUNCTION__, __LINE__);
272 return HI_FALSE;
273 }
274 }
275 return HI_TRUE;
276 }
277
hal_disp_get_intf_mux_sel(hal_disp_outputchannel chan,VO_INTF_TYPE_E * intf_type)278 hi_bool hal_disp_get_intf_mux_sel(hal_disp_outputchannel chan, VO_INTF_TYPE_E *intf_type)
279 {
280 volatile u_vo_mux vo_mux;
281 if (chan > HAL_DISP_CHANNEL_DHD1) {
282 HAL_PRINT("Error channel id found in %s: L%d\n", __FUNCTION__, __LINE__);
283 return HI_FALSE;
284 }
285
286 vo_mux.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->vo_mux.u32));
287
288 switch (vo_mux.bits.digital_sel) {
289 case 0: { /* 0 is Type */
290 *intf_type = HAL_DISP_INTF_BT1120;
291 break;
292 }
293 case 1: { /* 1 is Type */
294 *intf_type = HAL_DISP_INTF_BT656;
295 break;
296 }
297 case 2: { /* 2 is Type */
298 *intf_type = HAL_DISP_INTF_LCD;
299 break;
300 }
301 default: {
302 return HI_FALSE;
303 }
304 }
305
306 return HI_TRUE;
307 }
308
fb_hal_disp_get_int_state(hal_disp_outputchannel chan,hi_bool * bottom)309 hi_bool fb_hal_disp_get_int_state(hal_disp_outputchannel chan, hi_bool *bottom)
310 {
311 volatile u_dhd0_state dhd0_state;
312 volatile hi_ulong addr_reg;
313
314 switch (chan) {
315 case HAL_DISP_CHANNEL_DHD0:
316 case HAL_DISP_CHANNEL_DHD1:
317 addr_reg = fb_vou_get_chn_abs_addr(chan, (hi_ulong)(uintptr_t)&(g_hifb_reg->dhd0_state.u32));
318 dhd0_state.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
319 *bottom = dhd0_state.bits.bottom_field;
320 break;
321 default:
322 HAL_PRINT("Error channel id found in %s: L%d\n", __FUNCTION__, __LINE__);
323 return HI_FALSE;
324 }
325
326 return HI_TRUE;
327 }
328
329 /*
330 * Prototype : fb_hal_disp_get_disp_iop
331 * Description : Interlace or Progressive
332 */
fb_hal_disp_get_disp_iop(hal_disp_outputchannel chan,hi_bool * iop)333 hi_bool fb_hal_disp_get_disp_iop(hal_disp_outputchannel chan, hi_bool *iop)
334 {
335 u_dhd0_ctrl dhd0_ctrl;
336 volatile hi_ulong addr_reg;
337
338 switch (chan) {
339 case HAL_DISP_CHANNEL_DHD0:
340 case HAL_DISP_CHANNEL_DHD1:
341 addr_reg = fb_vou_get_chn_abs_addr(chan, (hi_ulong)(uintptr_t)&(g_hifb_reg->dhd0_ctrl.u32));
342 dhd0_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
343 *iop = dhd0_ctrl.bits.iop;
344 break;
345 default:
346 HAL_PRINT("Error channel id found in %s: L%d\n", __FUNCTION__, __LINE__);
347 return HI_FALSE;
348 }
349
350 return HI_TRUE;
351 }
352
hal_disp_get_vt_thd_mode(hal_disp_outputchannel chan,hi_bool * field_mode)353 hi_bool hal_disp_get_vt_thd_mode(hal_disp_outputchannel chan, hi_bool *field_mode)
354 {
355 volatile u_dhd0_vtthd dhd0_vtthd;
356 volatile hi_ulong addr_reg;
357
358 switch (chan) {
359 case HAL_DISP_CHANNEL_DHD0:
360 case HAL_DISP_CHANNEL_DHD1:
361 addr_reg = fb_vou_get_chn_abs_addr(chan, (hi_ulong)(uintptr_t)&(g_hifb_reg->dhd0_vtthd.u32));
362 dhd0_vtthd.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
363 *field_mode = dhd0_vtthd.bits.thd1_mode;
364 break;
365 default:
366 HAL_PRINT("Error channel id found in %s: L%d\n", __FUNCTION__, __LINE__);
367 return HI_FALSE;
368 }
369
370 return HI_TRUE;
371 }
372
373 /*
374 * Name : fb_hal_disp_set_int_mask
375 * Desc : Set interrupt mask to open or close interrupt.
376 */
fb_hal_disp_set_int_mask(hi_u32 mask_en)377 hi_bool fb_hal_disp_set_int_mask(hi_u32 mask_en)
378 {
379 volatile u_vointmsk1 vointmsk1;
380 /* Display interrupt mask enable */
381 vointmsk1.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->vointmsk1.u32));
382 vointmsk1.u32 = vointmsk1.u32 | mask_en;
383 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->vointmsk1.u32), vointmsk1.u32);
384 vointmsk1.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->vointmsk1.u32));
385 return HI_TRUE;
386 }
387
388 /* Name : fb_hal_disp_clr_int_mask */
fb_hal_disp_clr_int_mask(hi_u32 mask_en)389 hi_bool fb_hal_disp_clr_int_mask(hi_u32 mask_en)
390 {
391 volatile u_vointmsk1 vointmsk1;
392
393 /* Display interrupt mask enable */
394 vointmsk1.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->vointmsk1.u32));
395 vointmsk1.u32 = vointmsk1.u32 & (~mask_en);
396 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->vointmsk1.u32), vointmsk1.u32);
397
398 return HI_TRUE;
399 }
400
401 /* Get interrupt status */
fb_hal_disp_get_int_status(hi_u32 int_msk)402 hi_u32 fb_hal_disp_get_int_status(hi_u32 int_msk)
403 {
404 volatile u_vomskintsta1 vomskintsta1;
405
406 /* read interrupt status */
407 vomskintsta1.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->vomskintsta1.u32));
408
409 return (vomskintsta1.u32 & int_msk);
410 }
411
412 /* Get the original interrupt status */
fb_hal_disp_get_ori_int_status(hi_u32 int_status)413 hi_u32 fb_hal_disp_get_ori_int_status(hi_u32 int_status)
414 {
415 volatile u_vointsta vointsta;
416
417 /* read original interrupt status */
418 vointsta.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)&(g_hifb_reg->vointsta.u32));
419
420 return (vointsta.u32 & int_status);
421 }
422
423 /*
424 * Name : fb_hal_disp_clear_int_status
425 * Desc : Clear interrupt status.
426 */
fb_hal_disp_clear_int_status(hi_u32 int_msk)427 hi_bool fb_hal_disp_clear_int_status(hi_u32 int_msk)
428 {
429 /* read interrupt status */
430 fb_hal_write_reg((hi_u32 *)(uintptr_t)&(g_hifb_reg->vomskintsta.u32), int_msk);
431 return HI_TRUE;
432 }
433
hal_disp_get_raw_int_status(hi_u32 int_msk)434 hi_u32 hal_disp_get_raw_int_status(hi_u32 int_msk)
435 {
436 volatile u_vointsta vointsta;
437
438 /* read interrupt status */
439 vointsta.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)&(g_hifb_reg->vointsta.u32));
440
441 return (vointsta.u32 & int_msk);
442 }
443
hal_disp_get_raw_int_status1(hi_u32 int_msk)444 hi_u32 hal_disp_get_raw_int_status1(hi_u32 int_msk)
445 {
446 volatile u_vointsta1 vointsta1;
447
448 /* read interrupt status */
449 vointsta1.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)&(g_hifb_reg->vointsta1.u32));
450
451 return (vointsta1.u32 & int_msk);
452 }
453
454 /*
455 * Name : hal_disp_set_clk_gate_enable
456 * Desc : Set VO Clock gate enable
457 */
hal_disp_set_clk_gate_enable(hi_u32 data)458 hi_bool hal_disp_set_clk_gate_enable(hi_u32 data)
459 {
460 volatile u_voctrl voctrl;
461
462 voctrl.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->voctrl.u32));
463 voctrl.bits.vo_ck_gt_en = data;
464 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->voctrl.u32), voctrl.u32);
465
466 return HI_TRUE;
467 }
468
469 /*
470 * Name : fb_hal_disp_set_reg_up
471 * Desc : Set device register update.
472 */
fb_hal_disp_set_reg_up(hal_disp_outputchannel chan)473 hi_void fb_hal_disp_set_reg_up(hal_disp_outputchannel chan)
474 {
475 volatile u_dhd0_ctrl dhd0_ctrl;
476 volatile hi_ulong addr_reg;
477
478 if (chan > HAL_DISP_CHANNEL_DHD1) {
479 HI_PRINT("Error,fb_hal_disp_set_reg_up Select Wrong CHANNEL ID\n");
480 return;
481 }
482
483 /* If DHD0 or DHD1 */
484 addr_reg = fb_vou_get_chn_abs_addr(chan, (hi_ulong)(uintptr_t)&(g_hifb_reg->dhd0_ctrl.u32));
485 dhd0_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
486 dhd0_ctrl.bits.regup = 0x1;
487 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, dhd0_ctrl.u32);
488 return;
489 }
490
491 /*
492 * Name : fb_hal_disp_set_reg_up
493 * Desc : Get device register update.
494 */
fb_hal_disp_get_reg_up(hal_disp_outputchannel chan)495 hi_u32 fb_hal_disp_get_reg_up(hal_disp_outputchannel chan)
496 {
497 hi_u32 data;
498 volatile u_dhd0_ctrl dhd0_ctrl;
499 volatile hi_ulong addr_reg;
500
501 addr_reg = fb_vou_get_chn_abs_addr(chan, (hi_ulong)(uintptr_t)&(g_hifb_reg->dhd0_ctrl.u32));
502 dhd0_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
503 data = dhd0_ctrl.bits.regup;
504 return data & 0x1;
505 }
506
fb_hal_video_set_layer_disp_rect(hal_disp_layer layer,HIFB_RECT * rect)507 hi_bool fb_hal_video_set_layer_disp_rect(hal_disp_layer layer, HIFB_RECT *rect)
508 {
509 volatile u_g0_dfpos g0_dfpos;
510 volatile u_g0_dlpos g0_dlpos;
511 volatile hi_ulong addr_reg;
512
513 switch (layer) {
514 case HAL_DISP_LAYER_GFX0:
515 case HAL_DISP_LAYER_GFX1:
516 case HAL_DISP_LAYER_GFX3:
517 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_dfpos.u32));
518 g0_dfpos.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
519 g0_dfpos.bits.disp_xfpos = rect->x;
520 g0_dfpos.bits.disp_yfpos = rect->y;
521 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_dfpos.u32);
522
523 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_dlpos.u32));
524 g0_dlpos.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
525 g0_dlpos.bits.disp_xlpos = rect->x + rect->w - 1;
526 g0_dlpos.bits.disp_ylpos = rect->y + rect->h - 1;
527 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_dlpos.u32);
528 break;
529 default:
530 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
531 return HI_FALSE;
532 }
533
534 return HI_TRUE;
535 }
536
537 /* Set the video image display area window */
fb_hal_video_set_layer_video_rect(hal_disp_layer layer,HIFB_RECT * rect)538 hi_bool fb_hal_video_set_layer_video_rect(hal_disp_layer layer, HIFB_RECT *rect)
539 {
540 volatile u_g0_vfpos g0_vfpos;
541 volatile u_g0_vlpos g0_vlpos;
542 volatile hi_ulong addr_reg;
543
544 switch (layer) {
545 case HAL_DISP_LAYER_GFX0:
546 case HAL_DISP_LAYER_GFX1:
547 case HAL_DISP_LAYER_GFX3:
548 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_vfpos.u32));
549 g0_vfpos.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
550 g0_vfpos.bits.video_xfpos = rect->x;
551 g0_vfpos.bits.video_yfpos = rect->y;
552 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_vfpos.u32);
553
554 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_vlpos.u32));
555 g0_vlpos.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
556 g0_vlpos.bits.video_xlpos = rect->x + rect->w - 1;
557 g0_vlpos.bits.video_ylpos = rect->y + rect->h - 1;
558 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_vlpos.u32);
559 break;
560 default:
561 HAL_PRINT("Error layer id %d# found in %s,%s: L%d\n", layer, __FILE__, __FUNCTION__, __LINE__);
562 return HI_FALSE;
563 }
564
565 return HI_TRUE;
566 }
567
568 /*
569 * Name : fb_hal_layer_enable_layer
570 * Desc : Set layer enable
571 */
fb_hal_layer_enable_layer(hal_disp_layer layer,hi_u32 enable)572 hi_bool fb_hal_layer_enable_layer(hal_disp_layer layer, hi_u32 enable)
573 {
574 volatile u_v0_ctrl v0_ctrl;
575 volatile u_g0_ctrl g0_ctrl;
576 volatile hi_ulong addr_reg;
577
578 switch (layer) {
579 case HAL_DISP_LAYER_VHD0:
580 case HAL_DISP_LAYER_VHD1:
581 case HAL_DISP_LAYER_VHD2:
582 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->v0_ctrl.u32));
583 v0_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
584 v0_ctrl.bits.surface_en = enable;
585 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, v0_ctrl.u32);
586 break;
587 case HAL_DISP_LAYER_GFX0:
588 case HAL_DISP_LAYER_GFX1:
589 case HAL_DISP_LAYER_GFX3:
590 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_ctrl.u32));
591 g0_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
592 g0_ctrl.bits.surface_en = enable;
593 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_ctrl.u32);
594 break;
595 default:
596 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
597 return HI_FALSE;
598 }
599
600 return HI_TRUE;
601 }
602
fb_hal_layer_get_layer_enable(hal_disp_layer layer,hi_u32 * enable)603 hi_bool fb_hal_layer_get_layer_enable(hal_disp_layer layer, hi_u32 *enable)
604 {
605 volatile u_v0_ctrl v0_ctrl;
606 volatile u_g0_ctrl g0_ctrl;
607
608 volatile hi_ulong addr_reg;
609
610 switch (layer) {
611 case HAL_DISP_LAYER_VHD0:
612 case HAL_DISP_LAYER_VHD1:
613 case HAL_DISP_LAYER_VHD2:
614 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->v0_ctrl.u32));
615 v0_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
616 *enable = v0_ctrl.bits.surface_en;
617 break;
618 case HAL_DISP_LAYER_GFX0:
619 case HAL_DISP_LAYER_GFX1:
620 case HAL_DISP_LAYER_GFX3:
621 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_ctrl.u32));
622 g0_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
623 *enable = g0_ctrl.bits.surface_en;
624 break;
625 default:
626 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
627 return HI_FALSE;
628 }
629
630 return HI_TRUE;
631 }
632
633 /* Desc : Set layer data type */
fb_hal_layer_set_layer_data_fmt(hal_disp_layer layer,hal_disp_pixel_format data_fmt)634 hi_bool fb_hal_layer_set_layer_data_fmt(hal_disp_layer layer, hal_disp_pixel_format data_fmt)
635 {
636 volatile u_gfx_src_info gfx_src_info;
637 volatile hi_ulong addr_reg;
638
639 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
640 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_src_info.u32));
641 gfx_src_info.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
642 gfx_src_info.bits.ifmt = data_fmt;
643 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_src_info.u32);
644 } else {
645 HAL_PRINT("Error layer id%d found in %s: L%d\n", layer, __FUNCTION__, __LINE__);
646 return HI_FALSE;
647 }
648
649 return HI_TRUE;
650 }
651
fb_hal_layer_get_layer_data_fmt(hal_disp_layer layer,hi_u32 * fmt)652 hi_bool fb_hal_layer_get_layer_data_fmt(hal_disp_layer layer, hi_u32 *fmt)
653 {
654 volatile u_gfx_src_info gfx_src_info;
655 volatile hi_ulong addr_reg;
656
657 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
658 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_src_info.u32));
659 gfx_src_info.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
660 *fmt = gfx_src_info.bits.ifmt;
661 } else {
662 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
663 return HI_FALSE;
664 }
665 return HI_TRUE;
666 }
667
fb_hal_layer_csc_set_enable(hal_disp_layer layer,hi_bool csc_en)668 hi_void fb_hal_layer_csc_set_enable(hal_disp_layer layer, hi_bool csc_en)
669 {
670 u_g0_hipp_csc_ctrl g0_hipp_csc_ctrl;
671
672 volatile hi_ulong addr_reg;
673
674 if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) {
675 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_hipp_csc_ctrl.u32));
676 g0_hipp_csc_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
677 g0_hipp_csc_ctrl.bits.hipp_csc_en = csc_en;
678 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_ctrl.u32);
679 }
680 }
681
fb_hal_layer_csc_set_ck_gt_en(hal_disp_layer layer,hi_bool ck_gt_en)682 hi_void fb_hal_layer_csc_set_ck_gt_en(hal_disp_layer layer, hi_bool ck_gt_en)
683 {
684 u_g0_hipp_csc_ctrl g0_hipp_csc_ctrl;
685
686 volatile hi_ulong addr_reg;
687
688 if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) {
689 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_hipp_csc_ctrl.u32));
690 g0_hipp_csc_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
691 g0_hipp_csc_ctrl.bits.hipp_csc_ck_gt_en = ck_gt_en;
692 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_ctrl.u32);
693 }
694 }
695
fb_hal_layer_csc_set_coef(hal_disp_layer layer,vdp_csc_coef * coef)696 hi_void fb_hal_layer_csc_set_coef(hal_disp_layer layer, vdp_csc_coef *coef)
697 {
698 u_g0_hipp_csc_coef00 g0_hipp_csc_coef00;
699 u_g0_hipp_csc_coef01 g0_hipp_csc_coef01;
700 u_g0_hipp_csc_coef02 g0_hipp_csc_coef02;
701 u_g0_hipp_csc_coef10 g0_hipp_csc_coef10;
702 u_g0_hipp_csc_coef11 g0_hipp_csc_coef11;
703 u_g0_hipp_csc_coef12 g0_hipp_csc_coef12;
704 u_g0_hipp_csc_coef20 g0_hipp_csc_coef20;
705 u_g0_hipp_csc_coef21 g0_hipp_csc_coef21;
706 u_g0_hipp_csc_coef22 g0_hipp_csc_coef22;
707 volatile hi_ulong addr_reg;
708
709 if ((layer >= HAL_DISP_LAYER_GFX0) && (layer <= HAL_DISP_LAYER_GFX3)) {
710 g0_hipp_csc_coef00.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_hifb_reg->g0_hipp_csc_coef00.u32));
711 g0_hipp_csc_coef00.bits.hipp_csc_coef00 = coef->csc_coef00;
712 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_coef00.u32);
713
714 g0_hipp_csc_coef01.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_hifb_reg->g0_hipp_csc_coef01.u32));
715 g0_hipp_csc_coef01.bits.hipp_csc_coef01 = coef->csc_coef01;
716 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_coef01.u32);
717
718 g0_hipp_csc_coef02.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_hifb_reg->g0_hipp_csc_coef02.u32));
719 g0_hipp_csc_coef02.bits.hipp_csc_coef02 = coef->csc_coef02;
720 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_coef02.u32);
721
722 g0_hipp_csc_coef10.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_hifb_reg->g0_hipp_csc_coef10.u32));
723 g0_hipp_csc_coef10.bits.hipp_csc_coef10 = coef->csc_coef10;
724 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_coef10.u32);
725
726 g0_hipp_csc_coef11.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_hifb_reg->g0_hipp_csc_coef11.u32));
727 g0_hipp_csc_coef11.bits.hipp_csc_coef11 = coef->csc_coef11;
728 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_coef11.u32);
729
730 g0_hipp_csc_coef12.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_hifb_reg->g0_hipp_csc_coef12.u32));
731 g0_hipp_csc_coef12.bits.hipp_csc_coef12 = coef->csc_coef12;
732 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_coef12.u32);
733
734 g0_hipp_csc_coef20.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_hifb_reg->g0_hipp_csc_coef20.u32));
735 g0_hipp_csc_coef20.bits.hipp_csc_coef20 = coef->csc_coef20;
736 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_coef20.u32);
737
738 g0_hipp_csc_coef21.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_hifb_reg->g0_hipp_csc_coef21.u32));
739 g0_hipp_csc_coef21.bits.hipp_csc_coef21 = coef->csc_coef21;
740 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_coef21.u32);
741
742 g0_hipp_csc_coef22.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_hifb_reg->g0_hipp_csc_coef22.u32));
743 g0_hipp_csc_coef22.bits.hipp_csc_coef22 = coef->csc_coef22;
744 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_coef22.u32);
745 } else {
746 HAL_PRINT("Error layer id found in %s, %s, %d\n", __FILE__, __FUNCTION__, __LINE__);
747 }
748 return;
749 }
750
fb_hal_layer_csc_set_dc_coef(hal_disp_layer layer,vdp_csc_dc_coef * csc_dc_coef)751 hi_void fb_hal_layer_csc_set_dc_coef(hal_disp_layer layer, vdp_csc_dc_coef *csc_dc_coef)
752 {
753 u_g0_hipp_csc_idc0 g0_hipp_csc_idc0;
754 u_g0_hipp_csc_idc1 g0_hipp_csc_idc1;
755 u_g0_hipp_csc_idc2 g0_hipp_csc_idc2;
756 u_g0_hipp_csc_odc0 g0_hipp_csc_odc0;
757 u_g0_hipp_csc_odc1 g0_hipp_csc_odc1;
758 u_g0_hipp_csc_odc2 g0_hipp_csc_odc2;
759 volatile hi_ulong addr_reg;
760
761 if (layer == HAL_DISP_LAYER_GFX0) {
762 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_hipp_csc_idc0.u32));
763 g0_hipp_csc_idc0.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
764 g0_hipp_csc_idc0.bits.hipp_csc_idc0 = csc_dc_coef->csc_in_dc0;
765 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_idc0.u32);
766
767 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_hipp_csc_idc1.u32));
768 g0_hipp_csc_idc1.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
769 g0_hipp_csc_idc1.bits.hipp_csc_idc1 = csc_dc_coef->csc_in_dc1;
770 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_idc1.u32);
771
772 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_hipp_csc_idc2.u32));
773 g0_hipp_csc_idc2.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
774 g0_hipp_csc_idc2.bits.hipp_csc_idc2 = csc_dc_coef->csc_in_dc2;
775 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_idc2.u32);
776
777 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_hipp_csc_odc0.u32));
778 g0_hipp_csc_odc0.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
779 g0_hipp_csc_odc0.bits.hipp_csc_odc0 = csc_dc_coef->csc_out_dc0;
780 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_odc0.u32);
781
782 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_hipp_csc_odc1.u32));
783 g0_hipp_csc_odc1.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
784 g0_hipp_csc_odc1.bits.hipp_csc_odc1 = csc_dc_coef->csc_out_dc1;
785 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_odc1.u32);
786
787 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_hipp_csc_odc2.u32));
788 g0_hipp_csc_odc2.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
789 g0_hipp_csc_odc2.bits.hipp_csc_odc2 = csc_dc_coef->csc_out_dc2;
790 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_odc2.u32);
791 } else {
792 HAL_PRINT("Error layer id found in %s, %s, %d\n", __FILE__, __FUNCTION__, __LINE__);
793 }
794 }
795
fb_hal_layer_csc_set_param(hal_disp_layer layer,csc_coef_param * coef_param)796 hi_void fb_hal_layer_csc_set_param(hal_disp_layer layer, csc_coef_param *coef_param)
797 {
798 u_g0_hipp_csc_scale g0_hipp_csc_scale;
799 u_g0_hipp_csc_min_y g0_hipp_csc_min_y;
800 u_g0_hipp_csc_min_c g0_hipp_csc_min_c;
801 u_g0_hipp_csc_max_y g0_hipp_csc_max_y;
802 u_g0_hipp_csc_max_c g0_hipp_csc_max_c;
803
804 volatile hi_ulong addr_reg;
805
806 if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) {
807 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_hipp_csc_scale.u32));
808 g0_hipp_csc_scale.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
809 g0_hipp_csc_scale.bits.hipp_csc_scale = coef_param->csc_scale2p;
810 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_scale.u32);
811
812 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_hipp_csc_min_y.u32));
813 g0_hipp_csc_min_y.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
814 g0_hipp_csc_min_y.bits.hipp_csc_min_y = coef_param->csc_clip_min;
815 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_min_y.u32);
816
817 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_hipp_csc_min_c.u32));
818 g0_hipp_csc_min_c.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
819 g0_hipp_csc_min_c.bits.hipp_csc_min_c = coef_param->csc_clip_min;
820 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_min_c.u32);
821
822 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_hipp_csc_max_y.u32));
823 g0_hipp_csc_max_y.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
824 g0_hipp_csc_max_y.bits.hipp_csc_max_y = coef_param->csc_clip_max;
825 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_max_y.u32);
826
827 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_hipp_csc_max_c.u32));
828 g0_hipp_csc_max_c.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
829 g0_hipp_csc_max_c.bits.hipp_csc_max_c = coef_param->csc_clip_max;
830 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_hipp_csc_max_c.u32);
831 }
832 }
833
fb_hal_layer_set_csc_coef(hal_disp_layer layer,csc_coef * coef)834 hi_bool fb_hal_layer_set_csc_coef(hal_disp_layer layer, csc_coef *coef)
835 {
836 if ((layer < HAL_DISP_LAYER_VHD0) || (layer > HAL_DISP_LAYER_GFX3)) {
837 HAL_PRINT("Error, Wrong layer ID!%d\n", __LINE__);
838 return HI_FALSE;
839 }
840
841 fb_hal_layer_csc_set_dc_coef(layer, (vdp_csc_dc_coef *)(&coef->csc_in_dc0));
842 fb_hal_layer_csc_set_coef(layer, (vdp_csc_coef *)(&coef->csc_coef00));
843 fb_hal_layer_csc_set_param(layer, (csc_coef_param *)(&coef->new_csc_scale2p));
844
845 return HI_TRUE;
846 }
847
fb_hal_layer_set_csc_mode(hal_disp_layer layer,hi_bool is_hc_mode)848 hi_bool fb_hal_layer_set_csc_mode(hal_disp_layer layer, hi_bool is_hc_mode)
849 {
850 hi_unused(is_hc_mode);
851 if ((layer < HAL_DISP_LAYER_VHD0) || (layer > HAL_DISP_LAYER_GFX3)) {
852 HAL_PRINT("Error, Wrong layer ID!%d\n", __LINE__);
853 return HI_FALSE;
854 }
855
856 return HI_TRUE;
857 }
858
fb_hal_layer_set_csc_en(hal_disp_layer layer,hi_bool csc_en)859 hi_bool fb_hal_layer_set_csc_en(hal_disp_layer layer, hi_bool csc_en)
860 {
861 if ((layer < HAL_DISP_LAYER_VHD0) || (layer > HAL_DISP_LAYER_GFX3)) {
862 HAL_PRINT("Error, Wrong layer ID!%d\n", __LINE__);
863 return HI_FALSE;
864 }
865
866 fb_hal_layer_csc_set_ck_gt_en(layer, csc_en);
867 fb_hal_layer_csc_set_enable(layer, csc_en);
868
869 return HI_TRUE;
870 }
871
fb_hal_layer_set_src_resolution(hal_disp_layer layer,HIFB_RECT * rect)872 hi_bool fb_hal_layer_set_src_resolution(hal_disp_layer layer, HIFB_RECT *rect)
873 {
874 u_gfx_src_reso gfx_src_reso;
875 volatile hi_ulong addr_reg;
876
877 if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) {
878 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_src_reso.u32));
879 gfx_src_reso.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
880 gfx_src_reso.bits.src_w = rect->w - 1;
881 gfx_src_reso.bits.src_h = rect->h - 1;
882 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_src_reso.u32);
883 } else {
884 HAL_PRINT("Error:layer id not found in %s: L%d\n", __FUNCTION__, __LINE__);
885 return HI_FALSE;
886 }
887
888 return HI_TRUE;
889 }
890
fb_hal_layer_set_layer_in_rect(hal_disp_layer layer,HIFB_RECT * rect)891 hi_bool fb_hal_layer_set_layer_in_rect(hal_disp_layer layer, HIFB_RECT *rect)
892 {
893 u_gfx_ireso gfx_ireso;
894 volatile hi_ulong addr_reg;
895
896 if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) {
897 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_ireso.u32));
898 gfx_ireso.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
899 gfx_ireso.bits.ireso_w = rect->w - 1;
900 gfx_ireso.bits.ireso_h = rect->h - 1;
901 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_ireso.u32);
902 } else {
903 HAL_PRINT("Error layer id found in %s, %s, %d\n", __FILE__, __FUNCTION__, __LINE__);
904 return HI_FALSE;
905 }
906
907 return HI_TRUE;
908 }
909
fb_hal_layer_set_layer_out_rect(hal_disp_layer layer,HIFB_RECT * rect)910 hi_bool fb_hal_layer_set_layer_out_rect(hal_disp_layer layer, HIFB_RECT *rect)
911 {
912 hi_unused(rect);
913 if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) {
914 return HI_TRUE;
915 } else {
916 HAL_PRINT("Error:layer id not found in %s: L%d\n", __FUNCTION__, __LINE__);
917 return HI_FALSE;
918 }
919 }
920
921 /*
922 * Name : hal_layer_set_layer_galpha
923 * Desc : Set video/graphic layer's global alpha
924 */
hal_layer_set_layer_galpha(hal_disp_layer layer,hi_u8 alpha0)925 hi_bool hal_layer_set_layer_galpha(hal_disp_layer layer, hi_u8 alpha0)
926 {
927 volatile u_v0_ctrl v0_ctrl;
928 volatile u_g0_ctrl g0_ctrl;
929
930 volatile hi_ulong addr_reg;
931
932 switch (layer) {
933 case HAL_DISP_LAYER_VHD0:
934 case HAL_DISP_LAYER_VHD1:
935 case HAL_DISP_LAYER_VHD2:
936 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->v0_ctrl.u32));
937 v0_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
938 v0_ctrl.bits.galpha = alpha0;
939 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, v0_ctrl.u32);
940 break;
941 case HAL_DISP_LAYER_GFX0:
942 case HAL_DISP_LAYER_GFX1:
943 case HAL_DISP_LAYER_GFX3:
944 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_ctrl.u32));
945 g0_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
946 g0_ctrl.bits.galpha = alpha0;
947 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_ctrl.u32);
948 break;
949 default:
950 HAL_PRINT("Error layer id %d found in %s: L%d\n", layer, __FUNCTION__, __LINE__);
951 return HI_FALSE;
952 }
953
954 return HI_TRUE;
955 }
956
hal_layer_get_layer_galpha(hal_disp_layer layer,hi_u8 * alpha0)957 hi_bool hal_layer_get_layer_galpha(hal_disp_layer layer, hi_u8 *alpha0)
958 {
959 volatile u_v0_ctrl v0_ctrl;
960 volatile u_g0_ctrl g0_ctrl;
961 volatile hi_ulong addr_reg;
962
963 switch (layer) {
964 case HAL_DISP_LAYER_VHD0:
965 case HAL_DISP_LAYER_VHD1:
966 case HAL_DISP_LAYER_VHD2:
967 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->v0_ctrl.u32));
968 v0_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
969 *alpha0 = v0_ctrl.bits.galpha;
970 break;
971 case HAL_DISP_LAYER_GFX0:
972 case HAL_DISP_LAYER_GFX1:
973 case HAL_DISP_LAYER_GFX3:
974 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_ctrl.u32));
975 g0_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
976 *alpha0 = g0_ctrl.bits.galpha;
977 break;
978 default:
979 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
980 return HI_FALSE;
981 }
982
983 return HI_TRUE;
984 }
985
hal_layer_set_hor_ratio(hal_disp_layer layer,hi_u32 ratio)986 hi_bool hal_layer_set_hor_ratio(hal_disp_layer layer, hi_u32 ratio)
987 {
988 volatile u_g0_zme_hsp g0_zme_hsp;
989 volatile hi_ulong addr_reg;
990
991 if (layer == HAL_DISP_LAYER_GFX0) {
992 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_zme_hsp.u32));
993 g0_zme_hsp.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
994 g0_zme_hsp.bits.hratio = ratio;
995 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_zme_hsp.u32);
996 } else {
997 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
998 return HI_FALSE;
999 }
1000 return HI_TRUE;
1001 }
1002
1003 /*
1004 * Name : fb_hal_layer_set_reg_up
1005 * Desc : Set layer(video or graphic) register update.
1006 */
fb_hal_layer_set_reg_up(hal_disp_layer layer)1007 hi_bool fb_hal_layer_set_reg_up(hal_disp_layer layer)
1008 {
1009 u_g0_upd g0_upd;
1010 volatile hi_ulong addr_reg;
1011
1012 switch (layer) {
1013 case HAL_DISP_LAYER_GFX0:
1014 case HAL_DISP_LAYER_GFX1:
1015 case HAL_DISP_LAYER_GFX3: {
1016 addr_reg = fb_vou_get_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->g0_upd.u32));
1017 g0_upd.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1018 /* graphic layer register update */
1019 g0_upd.bits.regup = 0x1;
1020 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, g0_upd.u32);
1021 break;
1022 }
1023 default: {
1024 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
1025 return HI_FALSE;
1026 }
1027 }
1028
1029 return HI_TRUE;
1030 }
1031
1032 /* set layer addr */
hal_graphic_set_gfx_addr(hal_disp_layer layer,hi_u64 laddr)1033 hi_bool hal_graphic_set_gfx_addr(hal_disp_layer layer, hi_u64 laddr)
1034 {
1035 volatile hi_ulong gfx_addr_h;
1036 volatile hi_ulong gfx_addr_l;
1037
1038 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
1039 /* Write low address to register. */
1040 gfx_addr_l = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_addr_l));
1041 fb_hal_write_reg((hi_u32 *)(uintptr_t)gfx_addr_l, GetLowAddr(laddr));
1042
1043 /* Write high address to register. */
1044 gfx_addr_h = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_addr_h));
1045 fb_hal_write_reg((hi_u32 *)(uintptr_t)gfx_addr_h, GetHighAddr(laddr));
1046 } else {
1047 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
1048 return HI_FALSE;
1049 }
1050 return HI_TRUE;
1051 }
1052
1053 /*
1054 * Name : hal_graphic_get_gfx_addr
1055 * Desc : get layer addr.
1056 */
hal_graphic_get_gfx_addr(hal_disp_layer layer,hi_u64 * gfx_addr)1057 hi_bool hal_graphic_get_gfx_addr(hal_disp_layer layer, hi_u64 *gfx_addr)
1058 {
1059 volatile hi_ulong addr_reg;
1060 hi_u64 addr_h = 0x0;
1061 hi_u32 addr_l = 0x0;
1062
1063 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
1064 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_addr_l));
1065 addr_l = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1066 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_addr_h));
1067 addr_h = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1068 } else {
1069 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
1070 return HI_FALSE;
1071 }
1072
1073 *gfx_addr = addr_l + (addr_h << 32); /* 32 max address */
1074 return HI_TRUE;
1075 }
1076
1077 /* layer stride */
hal_graphic_set_gfx_stride(hal_disp_layer layer,hi_u16 pitch)1078 hi_bool hal_graphic_set_gfx_stride(hal_disp_layer layer, hi_u16 pitch)
1079 {
1080 volatile u_gfx_stride gfx_stride;
1081 volatile hi_ulong addr_reg;
1082
1083 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
1084 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_stride.u32));
1085 gfx_stride.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1086 gfx_stride.bits.surface_stride = pitch;
1087 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_stride.u32);
1088 } else {
1089 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
1090 return HI_FALSE;
1091 }
1092
1093 return HI_TRUE;
1094 }
1095
1096 /* get layer stride */
hal_graphic_get_gfx_stride(hal_disp_layer layer,hi_u32 * gfx_stride)1097 hi_bool hal_graphic_get_gfx_stride(hal_disp_layer layer, hi_u32 *gfx_stride)
1098 {
1099 volatile hi_ulong addr_reg;
1100 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
1101 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_stride.u32));
1102 } else {
1103 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
1104 return HI_FALSE;
1105 }
1106
1107 *gfx_stride = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1108
1109 return HI_TRUE;
1110 }
1111
1112 /* layer bit ext. */
hal_graphic_set_gfx_ext(hal_disp_layer layer,hal_gfx_bitextend mode)1113 hi_bool hal_graphic_set_gfx_ext(hal_disp_layer layer, hal_gfx_bitextend mode)
1114 {
1115 u_gfx_out_ctrl gfx_out_ctrl;
1116
1117 volatile hi_ulong addr_reg;
1118
1119 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
1120 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_out_ctrl.u32));
1121 gfx_out_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1122 gfx_out_ctrl.bits.bitext = mode;
1123 fb_hal_write_reg ((hi_u32 *)(uintptr_t)addr_reg, gfx_out_ctrl.u32);
1124 } else {
1125 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
1126 return HI_FALSE;
1127 }
1128 return HI_TRUE;
1129 }
1130
hal_graphic_set_gfx_pre_mult(hal_disp_layer layer,hi_u32 enable)1131 hi_bool hal_graphic_set_gfx_pre_mult(hal_disp_layer layer, hi_u32 enable)
1132 {
1133 u_gfx_out_ctrl gfx_out_ctrl;
1134
1135 volatile hi_ulong addr_reg;
1136
1137 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
1138 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_out_ctrl.u32));
1139 gfx_out_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1140 gfx_out_ctrl.bits.premulti_en = enable;
1141 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_out_ctrl.u32);
1142 } else {
1143 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
1144 return HI_FALSE;
1145 }
1146 return HI_TRUE;
1147 }
1148
hal_graphic_get_gfx_premult(hal_disp_layer layer,hi_u32 * enable)1149 hi_bool hal_graphic_get_gfx_premult(hal_disp_layer layer, hi_u32 *enable)
1150 {
1151 u_gfx_out_ctrl gfx_out_ctrl;
1152
1153 volatile hi_ulong addr_reg;
1154
1155 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
1156 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_out_ctrl.u32));
1157 gfx_out_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1158 *enable = gfx_out_ctrl.bits.premulti_en;
1159 } else {
1160 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
1161 return HI_FALSE;
1162 }
1163
1164 return HI_TRUE;
1165 }
1166
hal_graphic_set_gfx_palpha(hal_disp_layer layer,hi_u32 alpha_en,hi_u32 arange,hi_u8 alpha0,hi_u8 alpha1)1167 hi_bool hal_graphic_set_gfx_palpha(hal_disp_layer layer, hi_u32 alpha_en, hi_u32 arange, hi_u8 alpha0,
1168 hi_u8 alpha1)
1169 {
1170 u_gfx_out_ctrl gfx_out_ctrl;
1171 u_gfx_1555_alpha gfx_1555_alpha;
1172 volatile hi_ulong addr_reg;
1173 hi_unused(arange);
1174
1175 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
1176 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_out_ctrl.u32));
1177 gfx_out_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1178 gfx_out_ctrl.bits.palpha_en = alpha_en;
1179 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_out_ctrl.u32);
1180
1181 if (alpha_en == HI_TRUE) {
1182 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_1555_alpha.u32));
1183 gfx_1555_alpha.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1184 gfx_1555_alpha.bits.alpha_1 = alpha1;
1185 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_1555_alpha.u32);
1186
1187 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_1555_alpha.u32));
1188 gfx_1555_alpha.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1189 gfx_1555_alpha.bits.alpha_0 = alpha0;
1190 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_1555_alpha.u32);
1191 } else {
1192 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_1555_alpha.u32));
1193 gfx_1555_alpha.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1194 gfx_1555_alpha.bits.alpha_1 = 0xff; /* 0xff alpha_1 flag */
1195 fb_hal_write_reg ((hi_u32 *)(uintptr_t)addr_reg, gfx_1555_alpha.u32);
1196
1197 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_1555_alpha.u32));
1198 gfx_1555_alpha.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1199 gfx_1555_alpha.bits.alpha_0 = 0xff; /* 0xff alpha_0 flag */
1200 fb_hal_write_reg ((hi_u32 *)(uintptr_t)addr_reg, gfx_1555_alpha.u32);
1201 }
1202 } else {
1203 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
1204 return HI_FALSE;
1205 }
1206 return HI_TRUE;
1207 }
1208
1209 /*
1210 * Name : hal_graphic_set_gfx_palphaRange
1211 * Desc : alpha range setting
1212 */
hal_graphic_set_gfx_palpha_range(hal_disp_layer layer,hi_u32 arange)1213 hi_bool hal_graphic_set_gfx_palpha_range(hal_disp_layer layer, hi_u32 arange)
1214 {
1215 u_gfx_out_ctrl gfx_out_ctrl;
1216 volatile hi_ulong addr_reg;
1217 switch (layer) {
1218 case HAL_DISP_LAYER_GFX0:
1219 case HAL_DISP_LAYER_GFX1:
1220 case HAL_DISP_LAYER_GFX3:
1221 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_out_ctrl.u32));
1222 gfx_out_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1223 gfx_out_ctrl.bits.palpha_range = arange;
1224 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_out_ctrl.u32);
1225 break;
1226 default:
1227 HAL_PRINT("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__);
1228 return HI_FALSE;
1229 }
1230
1231 return HI_TRUE;
1232 }
1233
hal_graphic_set_gfx_key_en(hal_disp_layer layer,hi_u32 key_enable)1234 hi_bool hal_graphic_set_gfx_key_en(hal_disp_layer layer, hi_u32 key_enable)
1235 {
1236 u_gfx_out_ctrl gfx_out_ctrl;
1237 volatile hi_ulong addr_reg;
1238
1239 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
1240 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_out_ctrl.u32));
1241 gfx_out_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1242 gfx_out_ctrl.bits.key_en = key_enable;
1243 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_out_ctrl.u32);
1244 } else {
1245 HAL_PRINT("Error layer id %d not support colorkey in %s: L%d\n", (hi_s32)layer, __FUNCTION__, __LINE__);
1246 return HI_FALSE;
1247 }
1248 return HI_TRUE;
1249 }
1250
hal_graphic_set_gfx_key_mode(hal_disp_layer layer,hi_u32 key_out)1251 hi_bool hal_graphic_set_gfx_key_mode(hal_disp_layer layer, hi_u32 key_out)
1252 {
1253 u_gfx_out_ctrl gfx_out_ctrl;
1254 volatile hi_ulong addr_reg;
1255
1256 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
1257 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_out_ctrl.u32));
1258 gfx_out_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1259 gfx_out_ctrl.bits.key_mode = key_out;
1260 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_out_ctrl.u32);
1261 } else {
1262 HAL_PRINT("Error layer id %d not support colorkey mode in %s: L%d\n", (hi_s32)layer, __FUNCTION__, __LINE__);
1263 return HI_FALSE;
1264 }
1265 return HI_TRUE;
1266 }
1267
hal_graphic_set_color_key_value(hal_disp_layer layer,hal_gfx_key_max key_max,hal_gfx_key_min key_min)1268 hi_bool hal_graphic_set_color_key_value(hal_disp_layer layer, hal_gfx_key_max key_max, hal_gfx_key_min key_min)
1269 {
1270 u_gfx_ckey_max gfx_ckey_max;
1271 u_gfx_ckey_min gfx_ckey_min;
1272 volatile hi_ulong addr_reg;
1273
1274 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
1275 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_ckey_max.u32));
1276 gfx_ckey_max.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1277 gfx_ckey_max.bits.key_r_max = key_max.key_max_r;
1278 gfx_ckey_max.bits.key_g_max = key_max.key_max_g;
1279 gfx_ckey_max.bits.key_b_max = key_max.key_max_b;
1280 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_ckey_max.u32);
1281
1282 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_ckey_min.u32));
1283 gfx_ckey_min.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1284 gfx_ckey_min.bits.key_r_min = key_min.key_min_r;
1285 gfx_ckey_min.bits.key_g_min = key_min.key_min_g;
1286 gfx_ckey_min.bits.key_b_min = key_min.key_min_b;
1287 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_ckey_min.u32);
1288 } else {
1289 HAL_PRINT("Error layer id %d not support colorkey in %s: L%d\n", (hi_s32)layer, __FUNCTION__, __LINE__);
1290 return HI_FALSE;
1291 }
1292 return HI_TRUE;
1293 }
1294
hal_graphic_set_color_key_mask(hal_disp_layer layer,hal_gfx_mask msk)1295 hi_bool hal_graphic_set_color_key_mask(hal_disp_layer layer, hal_gfx_mask msk)
1296 {
1297 u_gfx_ckey_mask gfx_ckey_mask;
1298 volatile hi_ulong addr_reg;
1299
1300 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
1301 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_ckey_mask.u32));
1302 gfx_ckey_mask.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1303 gfx_ckey_mask.bits.key_r_msk = msk.mask_r;
1304 gfx_ckey_mask.bits.key_g_msk = msk.mask_g;
1305 gfx_ckey_mask.bits.key_b_msk = msk.mask_b;
1306 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_ckey_mask.u32);
1307 } else {
1308 HAL_PRINT("Error layer id %d not support colorkey mask in %s: L%d\n", (hi_s32)layer, __FUNCTION__, __LINE__);
1309 return HI_FALSE;
1310 }
1311
1312 return HI_TRUE;
1313 }
1314
1315 /* for gfx decompress */
hal_graphic_set_gfx_dcmp_enable(hal_disp_layer layer,hi_u32 enable)1316 hi_bool hal_graphic_set_gfx_dcmp_enable(hal_disp_layer layer, hi_u32 enable)
1317 {
1318 volatile u_gfx_src_info gfx_src_info;
1319 volatile hi_ulong addr_reg;
1320
1321 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1) || (layer == HAL_DISP_LAYER_GFX3)) {
1322 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_src_info.u32));
1323
1324 gfx_src_info.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1325 gfx_src_info.bits.dcmp_en = enable;
1326 fb_hal_write_reg((hi_u32 *)(uintptr_t)addr_reg, gfx_src_info.u32);
1327 } else {
1328 HAL_PRINT("Error layer id %d not support dcmp in %s: L%d\n", (hi_s32)layer, __FUNCTION__, __LINE__);
1329 return HI_FALSE;
1330 }
1331
1332 return HI_TRUE;
1333 }
1334
hal_graphic_get_gfx_dcmp_enable_state(hal_disp_layer layer,hi_bool * enable)1335 hi_bool hal_graphic_get_gfx_dcmp_enable_state(hal_disp_layer layer, hi_bool *enable)
1336 {
1337 volatile u_gfx_src_info gfx_src_info;
1338 volatile hi_ulong addr_reg;
1339 if ((layer == HAL_DISP_LAYER_GFX0) || (layer == HAL_DISP_LAYER_GFX1)) {
1340 addr_reg = fb_vou_get_gfx_abs_addr(layer, (hi_ulong)(uintptr_t)&(g_hifb_reg->gfx_src_info.u32));
1341 gfx_src_info.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg);
1342 *enable = gfx_src_info.bits.dcmp_en;
1343 } else {
1344 HAL_PRINT("Error layer id %d not support dcmp in %s: L%d\n", (hi_s32)layer, __FUNCTION__, __LINE__);
1345 return HI_FALSE;
1346 }
1347 return HI_TRUE;
1348 }
1349
1350 #ifdef MDDRDETECT
hal_mddrc_init_mddr_detect(hi_void)1351 hi_bool hal_mddrc_init_mddr_detect(hi_void)
1352 {
1353 volatile hi_u32 addr_reg;
1354
1355 addr_reg = (hi_u32) & (g_mddrc_reg->clk_cfg);
1356
1357 fb_hal_write_reg((hi_u32 *)addr_reg, 0x3); /* 0x3 address */
1358
1359 return HI_TRUE;
1360 }
1361
hal_mddrc_get_status(hi_u32 * status)1362 hi_void hal_mddrc_get_status(hi_u32 *status)
1363 {
1364 volatile hi_u32 addr_reg;
1365 if (status == NULL) {
1366 HAL_PRINT("Input args is NULL\n");
1367 return;
1368 }
1369
1370 addr_reg = (hi_u32)(hi_ulong)&(g_mddrc_reg->awaddr_srvlnc_status);
1371 *status = fb_hal_read_reg((hi_u32 *)addr_reg);
1372 return;
1373 }
1374
hal_mddrc_clear_status(hi_u32 status)1375 hi_void hal_mddrc_clear_status(hi_u32 status)
1376 {
1377 volatile hi_u32 addr_reg;
1378
1379 addr_reg = (hi_u32)&(g_mddrc_reg->awaddr_srvlnc_status);
1380 fb_hal_write_reg((hi_u32 *)addr_reg, status);
1381 }
1382 #endif
1383
hal_para_set_para_addr_vhd_chn06(hi_u64 para_addr_vhd_chn06)1384 hi_void hal_para_set_para_addr_vhd_chn06(hi_u64 para_addr_vhd_chn06)
1385 {
1386 volatile hi_u64 addr_vhd_chn06;
1387
1388 addr_vhd_chn06 = para_addr_vhd_chn06;
1389 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->para_haddr_vhd_chn06), GetHighAddr(addr_vhd_chn06));
1390 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->para_addr_vhd_chn06), GetLowAddr(addr_vhd_chn06));
1391
1392 return;
1393 }
1394
hal_para_set_para_up_vhd_chn(hi_u32 chn_num)1395 hi_void hal_para_set_para_up_vhd_chn(hi_u32 chn_num)
1396 {
1397 u_para_up_vhd para_up_vhd;
1398
1399 para_up_vhd.u32 = (1 << chn_num);
1400 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->para_up_vhd.u32), para_up_vhd.u32);
1401
1402 return;
1403 }
1404
hal_g0_zme_set_ck_gt_en(hi_u32 ck_gt_en)1405 hi_void hal_g0_zme_set_ck_gt_en(hi_u32 ck_gt_en)
1406 {
1407 u_g0_zme_hinfo g0_zme_hinfo;
1408
1409 g0_zme_hinfo.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hinfo.u32));
1410 g0_zme_hinfo.bits.ck_gt_en = ck_gt_en;
1411 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hinfo.u32), g0_zme_hinfo.u32);
1412
1413 return;
1414 }
1415
hal_g0_zme_set_out_width(hi_u32 out_width)1416 hi_void hal_g0_zme_set_out_width(hi_u32 out_width)
1417 {
1418 u_g0_zme_hinfo g0_zme_hinfo;
1419
1420 g0_zme_hinfo.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hinfo.u32));
1421 g0_zme_hinfo.bits.out_width = out_width - 1;
1422 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hinfo.u32), g0_zme_hinfo.u32);
1423
1424 return;
1425 }
1426
hal_g0_zme_set_hfir_en(hi_u32 hfir_en)1427 hi_void hal_g0_zme_set_hfir_en(hi_u32 hfir_en)
1428 {
1429 u_g0_zme_hsp g0_zme_hsp;
1430
1431 g0_zme_hsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32));
1432 g0_zme_hsp.bits.hfir_en = hfir_en;
1433 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32), g0_zme_hsp.u32);
1434
1435 return;
1436 }
1437
hal_g0_zme_set_ahfir_mid_en(hi_u32 ahfir_mid_en)1438 hi_void hal_g0_zme_set_ahfir_mid_en(hi_u32 ahfir_mid_en)
1439 {
1440 u_g0_zme_hsp g0_zme_hsp;
1441
1442 g0_zme_hsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32));
1443 g0_zme_hsp.bits.ahfir_mid_en = ahfir_mid_en;
1444 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32), g0_zme_hsp.u32);
1445
1446 return;
1447 }
1448
hal_g0_zme_set_lhfir_mid_en(hi_u32 lhfir_mid_en)1449 hi_void hal_g0_zme_set_lhfir_mid_en(hi_u32 lhfir_mid_en)
1450 {
1451 u_g0_zme_hsp g0_zme_hsp;
1452
1453 g0_zme_hsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32));
1454 g0_zme_hsp.bits.lhfir_mid_en = lhfir_mid_en;
1455 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32), g0_zme_hsp.u32);
1456
1457 return;
1458 }
1459
hal_g0_zme_set_chfir_mid_en(hi_u32 chfir_mid_en)1460 hi_void hal_g0_zme_set_chfir_mid_en(hi_u32 chfir_mid_en)
1461 {
1462 u_g0_zme_hsp g0_zme_hsp;
1463
1464 g0_zme_hsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32));
1465 g0_zme_hsp.bits.chfir_mid_en = chfir_mid_en;
1466 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32), g0_zme_hsp.u32);
1467
1468 return;
1469 }
1470
hal_g0_zme_set_lhfir_mode(hi_u32 lhfir_mode)1471 hi_void hal_g0_zme_set_lhfir_mode(hi_u32 lhfir_mode)
1472 {
1473 u_g0_zme_hsp g0_zme_hsp;
1474
1475 g0_zme_hsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32));
1476 g0_zme_hsp.bits.lhfir_mode = lhfir_mode;
1477 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32), g0_zme_hsp.u32);
1478
1479 return;
1480 }
1481
hal_g0_zme_set_ahfir_mode(hi_u32 ahfir_mode)1482 hi_void hal_g0_zme_set_ahfir_mode(hi_u32 ahfir_mode)
1483 {
1484 u_g0_zme_hsp g0_zme_hsp;
1485
1486 g0_zme_hsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32));
1487 g0_zme_hsp.bits.ahfir_mode = ahfir_mode;
1488 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32), g0_zme_hsp.u32);
1489
1490 return;
1491 }
1492
hal_g0_zme_set_hfir_order(hi_u32 hfir_order)1493 hi_void hal_g0_zme_set_hfir_order(hi_u32 hfir_order)
1494 {
1495 u_g0_zme_hsp g0_zme_hsp;
1496
1497 g0_zme_hsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32));
1498 g0_zme_hsp.bits.hfir_order = hfir_order;
1499 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32), g0_zme_hsp.u32);
1500
1501 return;
1502 }
1503
hal_g0_zme_set_hratio(hi_u32 hratio)1504 hi_void hal_g0_zme_set_hratio(hi_u32 hratio)
1505 {
1506 u_g0_zme_hsp g0_zme_hsp;
1507
1508 g0_zme_hsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32));
1509 g0_zme_hsp.bits.hratio = hratio;
1510 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hsp.u32), g0_zme_hsp.u32);
1511
1512 return;
1513 }
1514
hal_g0_zme_set_lhfir_offset(hi_u32 lhfir_offset)1515 hi_void hal_g0_zme_set_lhfir_offset(hi_u32 lhfir_offset)
1516 {
1517 u_g0_zme_hloffset g0_zme_hloffset;
1518
1519 g0_zme_hloffset.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hloffset.u32));
1520 g0_zme_hloffset.bits.lhfir_offset = lhfir_offset;
1521 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hloffset.u32), g0_zme_hloffset.u32);
1522
1523 return;
1524 }
1525
hal_g0_zme_set_chfir_offset(hi_u32 chfir_offset)1526 hi_void hal_g0_zme_set_chfir_offset(hi_u32 chfir_offset)
1527 {
1528 u_g0_zme_hcoffset g0_zme_hcoffset;
1529
1530 g0_zme_hcoffset.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hcoffset.u32));
1531 g0_zme_hcoffset.bits.chfir_offset = chfir_offset;
1532 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_hcoffset.u32), g0_zme_hcoffset.u32);
1533
1534 return;
1535 }
1536
hal_g0_zme_set_out_pro(hi_u32 out_pro)1537 hi_void hal_g0_zme_set_out_pro(hi_u32 out_pro)
1538 {
1539 u_g0_zme_vinfo g0_zme_vinfo;
1540
1541 g0_zme_vinfo.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vinfo.u32));
1542 g0_zme_vinfo.bits.out_pro = out_pro;
1543 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vinfo.u32), g0_zme_vinfo.u32);
1544
1545 return;
1546 }
1547
hal_fdr_gfx_set_dcmp_en(hi_u32 layer,hi_u32 dcmp_en)1548 hi_void hal_fdr_gfx_set_dcmp_en(hi_u32 layer, hi_u32 dcmp_en)
1549 {
1550 u_gfx_src_info gfx_src_info;
1551
1552 if (layer >= GFX_MAX) {
1553 HI_TRACE(HI_DBG_ERR, HI_ID_FB, "Error, %s(), %d Select Wrong Layer ID\n", __FUNCTION__, __LINE__);
1554 }
1555
1556 gfx_src_info.u32 = fb_hal_read_reg((hi_u32 *)((uintptr_t)(&(g_hifb_reg->gfx_src_info.u32)) +
1557 layer * FDR_GFX_OFFSET));
1558 gfx_src_info.bits.dcmp_en = dcmp_en;
1559 fb_hal_write_reg ((hi_u32 *)((uintptr_t)(&(g_hifb_reg->gfx_src_info.u32)) + layer * FDR_GFX_OFFSET),
1560 gfx_src_info.u32);
1561
1562 return;
1563 }
1564
hal_g0_zme_set_out_height(hi_u32 out_height)1565 hi_void hal_g0_zme_set_out_height(hi_u32 out_height)
1566 {
1567 u_g0_zme_vinfo g0_zme_vinfo;
1568
1569 g0_zme_vinfo.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vinfo.u32));
1570 g0_zme_vinfo.bits.out_height = out_height - 1;
1571 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vinfo.u32), g0_zme_vinfo.u32);
1572
1573 return;
1574 }
1575
hal_g0_zme_set_vfir_en(hi_u32 vfir_en)1576 hi_void hal_g0_zme_set_vfir_en(hi_u32 vfir_en)
1577 {
1578 u_g0_zme_vsp g0_zme_vsp;
1579
1580 g0_zme_vsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32));
1581 g0_zme_vsp.bits.vfir_en = vfir_en;
1582 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32), g0_zme_vsp.u32);
1583
1584 return;
1585 }
1586
hal_g0_zme_set_avfir_mid_en(hi_u32 avfir_mid_en)1587 hi_void hal_g0_zme_set_avfir_mid_en(hi_u32 avfir_mid_en)
1588 {
1589 u_g0_zme_vsp g0_zme_vsp;
1590
1591 g0_zme_vsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32));
1592 g0_zme_vsp.bits.avfir_mid_en = avfir_mid_en;
1593 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32), g0_zme_vsp.u32);
1594
1595 return;
1596 }
1597
hal_g0_zme_set_lvfir_mid_en(hi_u32 lvfir_mid_en)1598 hi_void hal_g0_zme_set_lvfir_mid_en(hi_u32 lvfir_mid_en)
1599 {
1600 u_g0_zme_vsp g0_zme_vsp;
1601
1602 g0_zme_vsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32));
1603 g0_zme_vsp.bits.lvfir_mid_en = lvfir_mid_en;
1604 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32), g0_zme_vsp.u32);
1605
1606 return;
1607 }
1608
hal_g0_zme_set_cvfir_mid_en(hi_u32 cvfir_mid_en)1609 hi_void hal_g0_zme_set_cvfir_mid_en(hi_u32 cvfir_mid_en)
1610 {
1611 u_g0_zme_vsp g0_zme_vsp;
1612
1613 g0_zme_vsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32));
1614 g0_zme_vsp.bits.cvfir_mid_en = cvfir_mid_en;
1615 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32), g0_zme_vsp.u32);
1616
1617 return;
1618 }
1619
hal_g0_zme_set_lvfir_mode(hi_u32 lvfir_mode)1620 hi_void hal_g0_zme_set_lvfir_mode(hi_u32 lvfir_mode)
1621 {
1622 u_g0_zme_vsp g0_zme_vsp;
1623
1624 g0_zme_vsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32));
1625 g0_zme_vsp.bits.lvfir_mode = lvfir_mode;
1626 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32), g0_zme_vsp.u32);
1627
1628 return;
1629 }
1630
hal_g0_zme_set_vafir_mode(hi_u32 vafir_mode)1631 hi_void hal_g0_zme_set_vafir_mode(hi_u32 vafir_mode)
1632 {
1633 u_g0_zme_vsp g0_zme_vsp;
1634
1635 g0_zme_vsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32));
1636 g0_zme_vsp.bits.vafir_mode = vafir_mode;
1637 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32), g0_zme_vsp.u32);
1638
1639 return;
1640 }
1641
hal_g0_zme_set_vratio(hi_u32 vratio)1642 hi_void hal_g0_zme_set_vratio(hi_u32 vratio)
1643 {
1644 u_g0_zme_vsp g0_zme_vsp;
1645
1646 g0_zme_vsp.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32));
1647 g0_zme_vsp.bits.vratio = vratio;
1648 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_vsp.u32), g0_zme_vsp.u32);
1649
1650 return;
1651 }
1652
hal_g0_zme_set_vtp_offset(hi_u32 vtp_offset)1653 hi_void hal_g0_zme_set_vtp_offset(hi_u32 vtp_offset)
1654 {
1655 u_g0_zme_voffset g0_zme_voffset;
1656
1657 g0_zme_voffset.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_voffset.u32));
1658 g0_zme_voffset.bits.vtp_offset = vtp_offset;
1659 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_voffset.u32), g0_zme_voffset.u32);
1660
1661 return;
1662 }
1663
hal_g0_zme_set_vbtm_offset(hi_u32 vbtm_offset)1664 hi_void hal_g0_zme_set_vbtm_offset(hi_u32 vbtm_offset)
1665 {
1666 u_g0_zme_voffset g0_zme_voffset;
1667
1668 g0_zme_voffset.u32 = fb_hal_read_reg((hi_u32 *)&(g_hifb_reg->g0_zme_voffset.u32));
1669 g0_zme_voffset.bits.vbtm_offset = vbtm_offset;
1670 fb_hal_write_reg((hi_u32 *)&(g_hifb_reg->g0_zme_voffset.u32), g0_zme_voffset.u32);
1671
1672 return;
1673 }
1674
hifb_hal_soft_int_en(hi_bool soft_int_en)1675 hi_void hifb_hal_soft_int_en(hi_bool soft_int_en)
1676 {
1677 #ifdef CONFIG_HIFB_SOFT_IRQ_SUPPORT
1678 u_sys_reg soft_int;
1679 if (g_sys_reg != HI_NULL) {
1680 soft_int.u32 = fb_hal_read_reg((hi_u32 *)&(g_sys_reg->soft_int.u32));
1681 soft_int.bits.software_int = (soft_int_en == HI_TRUE) ? 1 : 0;
1682 fb_hal_write_reg((hi_u32 *)&(g_sys_reg->soft_int.u32), soft_int.u32);
1683 }
1684 #endif
1685 return;
1686 }
1687