1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 #ifndef __HIFB_GRAPHIC_DRV_H__ 19 #define __HIFB_GRAPHIC_DRV_H__ 20 #include "hi_type.h" 21 #include "hi_common.h" 22 #include "hi_comm_vo.h" 23 #include "hifb_graphic_hal.h" 24 #include "hifb_vou_drv.h" 25 #include "hi_osal.h" 26 27 #define COEF_SIZE_G0ZME (4096 * 128 / 8) 28 /* debug print format */ 29 #define hifb_graphics_trace(level, fmt...) \ 30 do { \ 31 HI_TRACE(level, HI_ID_FB, "[Func]:%s [Line]:%d [Info]:", __FUNCTION__, __LINE__); \ 32 HI_TRACE(level, HI_ID_FB, ##fmt); \ 33 } while (0) 34 35 typedef hi_s32 (*fb_intcallback)(hi_void *, hi_void *); 36 37 #define GFX_SPIN_LOCK_S osal_spinlock_t 38 #define gfx_spin_lock_init(lock) osal_spin_lock_init(lock) 39 #define gfx_spin_lock_deinit(lock) osal_spin_lock_destroy(lock) 40 #define gfx_spin_lock_irqsave(lock, flag) osal_spin_lock_irqsave(lock, flag) 41 #define gfx_spin_unlock_irqrestore(lock, flag) osal_spin_unlock_irqrestore(lock, flag) 42 43 /* debug print format */ 44 #define graphics_drv_trace(level, fmt...) \ 45 do { \ 46 HI_TRACE(level, HI_ID_FB, "[Func]:%s [Line]:%d [Info]:", __FUNCTION__, __LINE__); \ 47 HI_TRACE(level, HI_ID_FB, ##fmt); \ 48 } while (0) 49 50 typedef struct { 51 hal_disp_layer layer_id; 52 hi_bool opened; 53 hi_bool binded; 54 hifb_vo_dev binded_dev; 55 56 fb_intcallback vo_callback; /* VSYNC interrupt callback function */ 57 hi_void *vo_callback_arg; 58 59 fb_intcallback wbc_callback; /* VSYNC interrupt callback function */ 60 hi_void *wbc_callback_arg; 61 62 fb_vo_csc gfx_csc; 63 csc_coef_param coef_param; 64 GFX_SPIN_LOCK_S spin_lock; 65 66 /* DDR detection area used in this layer */ 67 hi_u32 start_section; 68 hi_u32 zone_nums; 69 } vo_gfxlayer_context; 70 71 typedef enum { 72 VDP_G0_ZME_TYP = 0, 73 VDP_G0_ZME_TYP1, 74 VDP_G0_ZME_RAND, 75 VDP_G0_ZME_MAX, 76 VDP_G0_ZME_MIN, 77 VDP_G0_ZME_ZERO, 78 VDP_G0_ZME_BUTT 79 } gf_g0_zme_mode; 80 81 typedef struct { 82 hi_u32 ck_gt_en; 83 hi_u32 in_width; 84 hi_u32 out_width; 85 hi_u32 out_pro; 86 87 hi_u32 hfir_en; 88 hi_u32 lhmid_en; 89 hi_u32 ahmid_en; 90 hi_u32 lhfir_mode; 91 hi_u32 ahfir_mode; 92 93 hi_u32 in_height; 94 hi_u32 out_height; 95 96 hi_u32 vfir_en; 97 hi_u32 lvmid_en; 98 hi_u32 avmid_en; 99 hi_u32 lvfir_mode; 100 hi_u32 avfir_mode; 101 } gf_g0_zme_cfg; 102 103 typedef enum { 104 GF_RM_COEF_MODE_TYP = 0x0, 105 GF_RM_COEF_MODE_RAN = 0x1, 106 GF_RM_COEF_MODE_MIN = 0x2, 107 GF_RM_COEF_MODE_MAX = 0x3, 108 GF_RM_COEF_MODE_ZRO = 0x4, 109 GF_RM_COEF_MODE_CUS = 0x5, 110 GF_RM_COEF_MODE_UP = 0x6, 111 GF_RM_COEF_MODE_BUTT 112 } gf_rm_coef_mode; 113 114 typedef struct { 115 hi_u64 start_phy_addr; 116 hi_void *start_vir_addr; 117 hi_u32 size; 118 } hifb_mmz_buffer; 119 120 typedef enum { 121 HIFB_COEF_BUF_V0_HZME = 0, 122 HIFB_COEF_BUF_V0_VZME = 1, 123 HIFB_COEF_BUF_V0_HDRD = 2, 124 HIFB_COEF_BUF_V0_HDRS = 3, 125 HIFB_COEF_BUF_G0_HDR_TMAP = 4, 126 HIFB_COEF_BUF_G0_HDR_GMM = 5, 127 HIFB_COEF_BUF_G0ZME = 6, 128 HIFB_COEF_BUF_WD_HZME = 7, 129 HIFB_COEF_BUF_WD_VZME = 8, 130 HIFB_COEF_BUF_WD_HDRD = 9, 131 HIFB_COEF_BUF_WD_HDRS = 10, 132 133 HIFB_COEF_BUF_REGION_V0 = 12, 134 HIFB_COEF_BUF_REGION_V1 = 13, 135 HIFB_COEF_BUF_SHARPEN, 136 HIFB_COEF_BUF_DCI, 137 HIFB_COEF_BUF_ACM, 138 HIFB_COEF_BUF_VZME, 139 HIFB_COEF_BUF_HZME, 140 HIFB_COEF_BUF_GPZME, 141 HIFB_COEF_BUF_DIM, 142 HIFB_COEF_BUF_GMM, 143 HIFB_COEF_BUF_OD, 144 HIFB_COEF_BUF_CLUT, 145 HIFB_COEF_BUF_PCID, 146 147 HIFB_COEF_BUF_ALL = 32, 148 HIFB_COEF_BUF_BUTT = 33 149 } hifb_coef_buf; 150 151 typedef struct { 152 hifb_mmz_buffer buf_base_addr; 153 hi_u32 size; 154 155 hi_u8 *coef_vir_addr[HIFB_COEF_BUF_BUTT]; 156 hi_u64 coef_phy_addr[HIFB_COEF_BUF_BUTT]; 157 } hifb_coef_addr; 158 159 typedef struct { 160 hi_u32 data3; 161 hi_u32 data2; 162 hi_u32 data1; 163 hi_u32 data0; 164 hi_u32 depth; 165 } hifb_drv_u128; 166 167 typedef enum { 168 DRV_COEF_DATA_TYPE_U8 = 0, 169 DRV_COEF_DATA_TYPE_S8, 170 DRV_COEF_DATA_TYPE_U16, 171 DRV_COEF_DATA_TYPE_S16, 172 DRV_COEF_DATA_TYPE_U32, 173 DRV_COEF_DATA_TYPE_S32, 174 DRV_COEF_DATA_TYPE_BUTT 175 } hifb_drv_coef_data_type; 176 177 typedef struct { 178 hi_u8 *coef_addr; 179 hi_u32 lut_num; 180 hi_u32 burst_num; 181 hi_u32 cycle_num; 182 void **coef_array; 183 hi_u32 *lut_length; 184 hi_u32 *coef_bit_length; 185 hifb_drv_coef_data_type data_type; 186 } hifb_drv_coef_send_cfg; 187 188 hi_s32 graphic_drv_get_interrupt_dev(hi_u32 int_status, hifb_vo_dev *vo_dev); 189 hi_void graphic_drv_clr_int_status(hi_u32 int_status); 190 hi_u32 graphic_drv_int_get_status(hi_void); 191 hi_void graphic_drv_int_clear(hi_u32 int_clear, hi_s32 irq); 192 hi_void graphic_drv_dev_int_enable(hifb_vo_dev vo_dev, hi_bool enable); 193 hi_bool graphic_drv_enable_zme(hi_u32 layer, gf_g0_zme_cfg *zme_cfg, hi_bool enable_zme); 194 hi_void gf_vset_g0zme_coef(gf_rm_coef_mode coef_mode); 195 hi_void gf_drv_set_g0zme_coef(HI_S16 *coef_h, HI_S16 *coef_v); 196 hi_void gf_func_set_g0zme_mode(hi_u32 layer, gf_g0_zme_mode g0zme_mode, gf_g0_zme_cfg *cfg); 197 hi_s32 fb_graphic_drv_show_proc(osal_proc_entry_t *s); 198 hi_s32 fb_graphic_drv_set_csc_coef(hal_disp_layer gfx_layer, fb_vo_csc *gfx_csc, csc_coef_param *csc_coef_param); 199 hi_s32 graphic_drv_enable_layer(hal_disp_layer gfx_layer, hi_bool enabled); 200 hi_s32 graphic_drv_resource_exit(hi_void); 201 hi_s32 graphic_drv_resource_init(hi_void); 202 hi_s32 fb_graphic_drv_exit(hi_void); 203 hi_s32 graphic_drv_get_bind_dev(hi_s32 layer_id); 204 hi_s32 fb_graphic_drv_init(hi_void); 205 hi_s32 graphic_zme_coef_init(hi_void); 206 hi_bool graphic_drv_get_intf_mux_sel(hifb_vo_dev vo_dev, VO_INTF_TYPE_E *ben_intf_type); 207 hi_bool graphic_drv_get_intf_sync(hifb_vo_dev vo_dev, hal_disp_syncinfo *sync_info); 208 hi_bool graphic_drv_get_dev_enable(hifb_vo_dev vo_dev, hi_bool *intf_en); 209 hi_bool fb_graphic_drv_get_int_state(hal_disp_layer gfx_layer, hi_bool *bottom); 210 hi_bool graphic_drv_get_vt_thd_mode(hifb_vo_dev vo_dev, hi_bool *feild_update); 211 hi_bool graphic_drv_get_dcmp_enable_state(hal_disp_layer layer, hi_bool *enable); 212 hi_bool graphic_drv_enable_dcmp(hal_disp_layer layer, hi_bool enable); 213 hi_bool fb_graphic_drv_get_scan_mode(hifb_vo_dev vo_dev, hi_bool *iop); 214 hi_bool graphic_drv_get_gfx_stride(hal_disp_layer layer, hi_u32 *gfx_stride); 215 hi_bool graphic_drv_get_gfx_addr(hal_disp_layer layer, hi_u64 *gfx_addr); 216 hi_bool graphic_drv_get_layer_data_fmt(hal_disp_layer layer, hi_u32 *fmt); 217 hi_bool graphic_drv_get_layer_galpha(hal_disp_layer layer, hi_u8 *alpha0); 218 hi_bool graphic_drv_set_reg_up(hal_disp_layer layer); 219 hi_bool graphic_drv_set_gfx_key_en(hal_disp_layer layer, hi_u32 key_enable); 220 hi_bool graphic_drv_set_color_key_mask(hal_disp_layer layer, hal_gfx_mask msk); 221 hi_bool graphic_drv_set_color_key_value(hal_disp_layer layer, hal_gfx_key_max key_max, hal_gfx_key_min key_min); 222 hi_bool graphic_drv_set_layer_out_rect(hal_disp_layer layer, HIFB_RECT *rect); 223 hi_bool graphic_drv_set_src_image_resolution(hal_disp_layer layer, HIFB_RECT *rect); 224 hi_bool graphic_drv_set_layer_in_rect(hal_disp_layer layer, HIFB_RECT *rect); 225 hi_bool graphic_drv_set_layer_data_fmt(hal_disp_layer layer, hal_disp_pixel_format data_fmt); 226 hi_bool graphic_drv_set_gfx_pre_mult(hal_disp_layer layer, hi_u32 enable); 227 hi_bool graphic_drv_get_gfx_pre_mult(hal_disp_layer layer, hi_u32 *enable); 228 hi_bool graphic_drv_set_gfx_stride(hal_disp_layer layer, HI_U16 pitch); 229 hi_bool graphic_drv_set_layer_addr(hal_disp_layer layer_id, hi_u64 addr); 230 hi_bool graphic_drv_layer_set_csc_en(hal_disp_layer layer, hi_bool csc_en); 231 hi_bool graphic_drv_layer_set_layer_galpha(hal_disp_layer layer, hi_u8 alpha0); 232 hi_bool graphic_drv_set_gfx_palpha(hal_disp_layer layer, hi_u32 alpha_en, hi_u32 arange, hi_u8 alpha0, 233 hi_u8 alpha1); 234 hi_bool graphic_drv_set_gfx_ext(hal_disp_layer layer, hal_gfx_bitextend mode); 235 hi_bool graphic_drv_set_gfx_key_mode(hal_disp_layer layer, hi_u32 key_out); 236 hi_s32 fb_graphic_drv_get_layer_id(hi_u32 layer, hal_disp_layer *disp_layer); 237 hi_s32 fb_graphic_drv_get_layer_index(hal_disp_layer disp_layer, hi_u32 *layer); 238 239 #endif /* __HIFB_GRAPHIC_DRV_H__ */ 240