1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 #ifndef __HDMI_PRODUCT_DEFINE_H__ 19 #define __HDMI_PRODUCT_DEFINE_H__ 20 21 #ifndef HDMI_LITEOS_SUPPORT 22 #include <linux/kthread.h> 23 #include <linux/fs.h> 24 #else 25 #include <pthread.h> 26 #endif 27 #include "dev_ext.h" 28 #include "mod_ext.h" 29 #include "hi_osal.h" 30 #include "hi_type.h" 31 #include "drv_hdmi_common.h" 32 33 #define HDMI_CHIP_HI3516CV500 0x3516c500 34 #define HDMI_CTRL_BASE_ADDR 0x11420000 35 #define HDMI_ADDR_BASE_IO_CFG 0x114f0000 36 #define HDMI_ADDR_CRG 0x12010110 /* base addr offset is 0x110 */ 37 #define BASE_ADDR_TX_DPHY 0x11400000 38 #define HDMI_COLOR_BAR_MASK 0x70000000 39 #define HDMI_COLOR_BAR_UPDATE_MASK 0x00000001 40 #define HDMI_COLOR_BAR_BASE 0x1144d000 // VDP 41 #define HDMI_TX_BASE_ADDR 0x11400000 42 #define HDMI_TX_REG_LEN 0x40000 43 #define HDMI_TX_BASE_ADDR_CTRL 0x20000 44 #define HDMI_TX_BASE_ADDR_VIDEO 0x20800 45 #define HDMI_TX_BASE_ADDR_AUDIO 0x21000 46 #define HDMI_TX_BASE_ADDR_HDMITX 0x21800 47 #define HDMI_TX_BASE_ADDR_HDCP1X 0x22000 48 #define HDMI_TX_BASE_ADDR_AON 0x24000 49 #define HDMI_TX_BASE_ADDR_CEC 0x24800 50 #define HDMI_TX_BASE_ADDR_MCU_PRAM 0x30000 51 #define HDMI_TX_BASE_ADDR_MCU_DRAM 0x38000 52 #define HDMI_TX_BASE_ADDR_MCU 0x3c000 53 #define HDMI_TX_BASE_ADDR_DPHY 0x0 54 /* HDMI PHY */ 55 #define HDMI_TX_PHY_ADDR (HDMI_TX_BASE_ADDR + HDMI_TX_BASE_ADDR_DPHY) 56 #define BASE_ADDR_TX_CTRL_REG (HDMI_TX_BASE_ADDR | HDMI_TX_BASE_ADDR_CTRL) 57 #define BASE_ADDR_VIDEO_PATH_REG (HDMI_TX_BASE_ADDR | HDMI_TX_BASE_ADDR_VIDEO) 58 #define BASE_ADDR_AUDIO_PATH_REG (HDMI_TX_BASE_ADDR | HDMI_TX_BASE_ADDR_AUDIO) 59 #define BASE_ADDR_TX_HDMI_REG (HDMI_TX_BASE_ADDR | HDMI_TX_BASE_ADDR_HDMITX) 60 #define BASE_ADDR_TX_HDCP_REG (HDMI_TX_BASE_ADDR | HDMI_TX_BASE_ADDR_HDCP1X) 61 #define BASE_ADDR_TX_AON_REG (HDMI_TX_BASE_ADDR | HDMI_TX_BASE_ADDR_AON) 62 #define BASE_ADDR_TX_CEC_REG (HDMI_TX_BASE_ADDR | HDMI_TX_BASE_ADDR_CEC) 63 #define BASE_ADDR_MCU_CPU_REG (HDMI_TX_BASE_ADDR | HDMI_TX_BASE_ADDR_MCU) 64 #define BASE_ADDR_MCU_PARAM (HDMI_TX_BASE_ADDR | HDMI_TX_BASE_ADDR_MCU_PRAM) 65 #define BASE_ADDR_MCU_DRAM (HDMI_TX_BASE_ADDR | HDMI_TX_BASE_ADDR_MCU_DRAM) 66 #ifdef HI_ADVCA_FUNCTION_RELEASE 67 /* PROC disable */ 68 #define CONFIG_HDMI_PROC_DISABLE 69 /* LOG disable */ 70 #define CONFIG_HDMI_DEBUG_DISABLE 71 #endif 72 #define hdmi_mutex_unlock(a) osal_up((osal_semaphore_t *)&(a)) 73 #define HDMI_FILE_MODE 0755 74 #define VERSION_STRING ("[HDMI] Version: [" MPP_VERSION "], Build Time["__DATE__", "__TIME__"]") 75 #ifndef HDMI_LITEOS_SUPPORT 76 #define hdmi_get_current_id() (get_current()->tgid) 77 #else 78 #define hdmi_get_current_id() (pthread_self() + 1) 79 #endif 80 81 #define hi_err_hdmi(fmt...) \ 82 do { \ 83 HI_ERR_TRACE(HI_ID_HDMI, "[Func]:%s [Line]:%u [Info]:", __FUNCTION__, (hi_u32)__LINE__); \ 84 HI_ERR_TRACE(HI_ID_HDMI, ##fmt); \ 85 } while (0) 86 87 #define hi_warn_hdmi(fmt...) \ 88 do { \ 89 HI_WARN_TRACE(HI_ID_HDMI, "[Func]:%s [Line]:%u [Info]:", __FUNCTION__, (hi_u32)__LINE__); \ 90 HI_WARN_TRACE(HI_ID_HDMI, ##fmt); \ 91 } while (0) 92 93 #define hi_info_hdmi(fmt...) \ 94 do { \ 95 HI_INFO_TRACE(HI_ID_HDMI, "[Func]:%s [Line]:%u [Info]:", __FUNCTION__, (hi_u32)__LINE__); \ 96 HI_INFO_TRACE(HI_ID_HDMI, ##fmt); \ 97 } while (0) 98 99 #define hi_fatal_hdmi(fmt...) \ 100 do { \ 101 HI_DEBUG_TRACE(HI_ID_HDMI, fmt); \ 102 } while (0) 103 104 #define hdmi_mutex_lock(a) \ 105 do { \ 106 hi_s32 result = osal_down((osal_semaphore_t *)&(a)); \ 107 if (result != 0) { \ 108 hdmi_err("osal_down failed! ret=%d\n", result); \ 109 } \ 110 } while (0) 111 112 #ifdef HDMI_LOG_SUPPORT 113 #ifndef HI_ADVCA_FUNCTION_RELEASE 114 #define hdmi_printk(fmt, args...) osal_printk(fmt, ##args) 115 #else 116 #define hdmi_printk(fmt, args...) 117 #endif 118 #else 119 #define hdmi_printk(fmt, args...) 120 #endif 121 122 #ifdef CONFIG_HDMI_DEBUG_DISABLE 123 #define edid_info(fmt...) 124 #define edid_warn(fmt...) 125 #define edid_err(fmt...) 126 #define edid_fatal(fmt...) 127 #define hdmi_info(fmt...) 128 #define hdmi_warn(fmt...) 129 #define hdmi_err(fmt...) 130 #define hdmi_fatal(fmt...) 131 #elif defined(HDMI_LOG_SUPPORT) 132 #define edid_info(fmt...) 133 #define edid_warn(fmt...) 134 #define edid_err(fmt...) 135 #define edid_fatal(fmt...) 136 #define hdmi_info(fmt...) hi_info_hdmi(fmt); 137 #define hdmi_warn(fmt...) hi_warn_hdmi(fmt); 138 #define hdmi_err(fmt...) hi_err_hdmi(fmt); 139 #define hdmi_fatal(fmt...) hi_fatal_hdmi(fmt); 140 #else 141 #define edid_info(fmt...) hi_info_hdmi(fmt) 142 #define edid_warn(fmt...) hi_warn_hdmi(fmt) 143 #define edid_err(fmt...) hi_err_hdmi(fmt) 144 #define edid_fatal(fmt...) hi_fatal_hdmi(fmt) 145 #define hdmi_fatal(fmt...) hi_fatal_hdmi(fmt) 146 #define hdmi_err(fmt...) hi_err_hdmi(fmt) 147 #define hdmi_warn(fmt...) hi_warn_hdmi(fmt) 148 #define hdmi_info(fmt...) hi_info_hdmi(fmt) 149 #endif 150 151 typedef osal_proc_entry_t hdmi_proc_entry; 152 153 /* structure of proc item */ 154 typedef struct { 155 hi_s32 (*fn_read)(hdmi_proc_entry *file); 156 hi_s32 (*fn_write)(hdmi_proc_entry *file, const char *buf, hi_u32 count, hi_s64 *data); 157 } hdmi_proc_item; 158 159 typedef struct { 160 hi_u32 ssc_bypass_div; 161 hi_u32 tmds_clk_div; 162 } hdmi_crg_cfg; 163 164 hi_void hdmi_tx_reg_write(hi_u32 *reg_addr, hi_u32 value); 165 166 hi_u32 hdmi_tx_reg_read(const hi_u32 *reg_addr); 167 168 hi_void hdmi_reg_write_u32(hi_u32 reg_addr, hi_u32 value); 169 170 hi_u32 hdmi_reg_read_u32(hi_u32 reg_addr); 171 172 hi_void drv_hdmi_prod_io_cfg_set(hi_void); 173 174 hi_void drv_hdmi_prod_crg_all_reset_set(hi_bool enable); 175 176 hi_void drv_hdmi_prod_crg_gate_set(hi_bool enable); 177 178 hi_void drv_hdmi_prod_crg_div_set(hdmi_crg_cfg *crg_cfg); 179 180 hi_void drv_hdmi_prod_crg_phy_reset_set(hi_bool enable); 181 182 hi_void drv_hdmi_prod_crg_phy_reset_get(hi_bool *enable); 183 184 hi_void drv_hdmi_prod_crg_init(hi_void); 185 186 hi_void drv_hdmi_hardware_reset(hi_void); 187 188 hi_void drv_hdmi_low_power_set(hi_bool enable); 189 190 hdmi_chip_type drv_hdmi_prod_chip_get(hi_void); 191 192 #endif 193 194