1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: Provides V150 gpio register \n 16 * 17 * History: \n 18 * 2022-07-27, Create file. \n 19 */ 20 #ifndef HAL_GPIO_V150_REGS_H 21 #define HAL_GPIO_V150_REGS_H 22 23 #include <stdint.h> 24 25 #ifdef __cplusplus 26 #if __cplusplus 27 extern "C" { 28 #endif /* __cplusplus */ 29 #endif /* __cplusplus */ 30 31 /** 32 * @defgroup drivers_hal_gpio_v150_regs_def GPIO V150 Regs Definition 33 * @ingroup drivers_hal_gpio 34 * @{ 35 */ 36 37 #define RESERVED_MAX_NUM 2 38 39 /** 40 * @brief GPIO pin group definition. A GPIO channel contains a maximum of 8 groups of pin. 41 */ 42 typedef enum { 43 GPIO_GROUP_0 = 0, 44 GPIO_GROUP_1, 45 GPIO_GROUP_2, 46 GPIO_GROUP_3, 47 GPIO_GROUP_4, 48 GPIO_GROUP_5, 49 GPIO_GROUP_6, 50 GPIO_GROUP_7, 51 GPIO_GROUP_MAX_NUM 52 } gpio_group_t; 53 54 /** 55 * @brief GPIO pin definition in group. Each GPIO group contains a maximum of 32 pins. 56 */ 57 typedef enum { 58 GPIO_GROUP_PIN_00 = 0, 59 GPIO_GROUP_PIN_01, 60 GPIO_GROUP_PIN_02, 61 GPIO_GROUP_PIN_03, 62 GPIO_GROUP_PIN_04, 63 GPIO_GROUP_PIN_05, 64 GPIO_GROUP_PIN_06, 65 GPIO_GROUP_PIN_07, 66 GPIO_GROUP_PIN_08, 67 GPIO_GROUP_PIN_09, 68 GPIO_GROUP_PIN_10, 69 GPIO_GROUP_PIN_11, 70 GPIO_GROUP_PIN_12, 71 GPIO_GROUP_PIN_13, 72 GPIO_GROUP_PIN_14, 73 GPIO_GROUP_PIN_15, 74 GPIO_GROUP_PIN_16, 75 GPIO_GROUP_PIN_17, 76 GPIO_GROUP_PIN_18, 77 GPIO_GROUP_PIN_19, 78 GPIO_GROUP_PIN_20, 79 GPIO_GROUP_PIN_21, 80 GPIO_GROUP_PIN_22, 81 GPIO_GROUP_PIN_23, 82 GPIO_GROUP_PIN_24, 83 GPIO_GROUP_PIN_25, 84 GPIO_GROUP_PIN_26, 85 GPIO_GROUP_PIN_27, 86 GPIO_GROUP_PIN_28, 87 GPIO_GROUP_PIN_29, 88 GPIO_GROUP_PIN_30, 89 GPIO_GROUP_PIN_31, 90 GPIO_GROUP_PIN_MAX_NUM 91 } gpio_group_pin_t; 92 93 /** 94 * @brief GPIO pin idx info, including the channel, the group, and group pin number to which this pin belongs. 95 */ 96 typedef struct gpio_idx_info { 97 uint8_t channel; 98 uint8_t group; 99 uint8_t group_pin; 100 uint8_t rsv; 101 } gpio_idx_info_t; 102 103 /** 104 * @brief Register definition of each GPIO group. 105 */ 106 typedef struct gpio_info_regs { 107 volatile uint32_t gpio_sw_out; /*!< (0x00) : port A data register */ 108 volatile uint32_t gpio_sw_oen; /*!< (0x04) : port A data direction register */ 109 volatile uint32_t gpio_sw_ctl; /*!< (0x08) : Port A data source register */ 110 volatile uint32_t gpio_int_en; /*!< (0x0C) : Interrupt enable */ 111 volatile uint32_t gpio_int_mask; /*!< (0x10) : Interrupt mask */ 112 volatile uint32_t gpio_int_type; /*!< (0x14) : Interrupt type */ 113 volatile uint32_t gpio_int_polarity; /*!< (0x18) : Interrupt polarity */ 114 volatile uint32_t gpio_int_dedge; /*!< (0x1C) : Interrupt double edge type */ 115 volatile uint32_t gpio_int_debounce; /*!< (0x20) : Interrupt debounce enable */ 116 volatile uint32_t gpio_int_raw; /*!< (0x24) : Raw interrupt status */ 117 volatile uint32_t gpio_intr; /*!< (0x28) : Interrupt status */ 118 volatile uint32_t gpio_int_eoi; /*!< (0x2C) : Clear interrupt */ 119 volatile uint32_t gpio_data_set; /*!< (0x30) : Data set */ 120 volatile uint32_t gpio_data_clr; /*!< (0x34) : Data clear */ 121 volatile uint32_t reserved[RESERVED_MAX_NUM]; /*!< (0x38) : Reserved */ 122 } gpio_group_regs_t; 123 124 /** 125 * @brief Register definition of GPIO channel. 126 * A GPIO channel contains a maximum of 8 groups of pin. 127 * Each GPIO group contains a maximum of 32 pins. 128 */ 129 typedef struct gpio_v150_regs { 130 volatile gpio_group_regs_t gpio_group_cfg[GPIO_GROUP_MAX_NUM]; /*!< (0x00) : gpio config register */ 131 volatile uint32_t gpio_lock; /*!< (0x200) : gpio lock register */ 132 volatile uint32_t gpio_lp_state; /*!< (0x204) : gpio low power state */ 133 } gpio_v150_regs_t; 134 135 /** 136 * @} 137 */ 138 139 #ifdef __cplusplus 140 #if __cplusplus 141 } 142 #endif /* __cplusplus */ 143 #endif /* __cplusplus */ 144 145 #endif 146 147