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1 /**
2  * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3  * Licensed under the Apache License, Version 2.0 (the "License");
4  * you may not use this file except in compliance with the License.
5  * You may obtain a copy of the License at
6  *
7  *     http://www.apache.org/licenses/LICENSE-2.0
8  *
9  * Unless required by applicable law or agreed to in writing, software
10  * distributed under the License is distributed on an "AS IS" BASIS,
11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  * See the License for the specific language governing permissions and
13  * limitations under the License.
14  *
15  * Description: Provides V154 adc register operation api \n
16  *
17  * History: \n
18  * 2024-02-01， Create file. \n
19  */
20 
21 #ifndef HAL_ADC_V154_REGS_OP_H
22 #define HAL_ADC_V154_REGS_OP_H
23 
24 #include <stdint.h>
25 #include <stdbool.h>
26 #include "errcode.h"
27 #include "hal_adc_v154_regs_def.h"
28 #include "adc_porting.h"
29 
30 #ifdef __cplusplus
31 #if __cplusplus
32 extern "C" {
33 #endif /* __cplusplus */
34 #endif /* __cplusplus */
35 
36 extern adc_regs_t *g_adc_regs;
37 extern cldo_crg_cfg_t *g_cldo_cfg;
38 
hal_adc_reg_irg_fifo_stat_get(void)39 static inline bool hal_adc_reg_irg_fifo_stat_get(void)
40 {
41     adc_irg_data_t data;
42     data.d32 = g_adc_regs->lsadc_ctrl_2;
43     return (bool)data.b.rxris;
44 }
45 
hal_adc_reg_irg_fifo_interrupt_mask(void)46 static inline void hal_adc_reg_irg_fifo_interrupt_mask(void)
47 {
48     adc_irg_data_t data;
49     data.d32 = g_adc_regs->lsadc_ctrl_2;
50     data.b.rxim = 1;
51     g_adc_regs->lsadc_ctrl_2 = data.d32;
52 }
53 
hal_adc_reg_fifo_isnt_empty_get(void)54 static inline bool hal_adc_reg_fifo_isnt_empty_get(void)
55 {
56     adc_fifo_data_t data;
57     data.d32 = g_adc_regs->lsadc_ctrl_1;
58     return (bool)data.b.rne;
59 }
60 
hal_adc_reg_fifo_data_get(void)61 static inline uint32_t hal_adc_reg_fifo_data_get(void)
62 {
63     adc_fifo_read_data_t data;
64     data.d32 = g_adc_regs->lsadc_ctrl_9;
65     return data.b.data;
66 }
67 
hal_adc_soft_rst(uint32_t value)68 static inline void hal_adc_soft_rst(uint32_t value)
69 {
70     cldo_rst_soft_ctl_t data;
71     data.d32 = g_cldo_cfg->cldo_crg_rst_soft_cfg_1;
72     data.b.soft_rst_lsadc_n = value;
73     data.b.soft_rst_lsadc_bus_n = value;
74     g_cldo_cfg->cldo_crg_rst_soft_cfg_1 = data.d32;
75 }
76 
hal_adc_simu_cfg1(void)77 static inline void hal_adc_simu_cfg1(void)
78 {
79     uint32_t data;
80     data = 0x155240;
81     g_adc_regs->da_lsadc_rwreg_1 = data;
82 }
83 
hal_adc_simu_cfg2(void)84 static inline void hal_adc_simu_cfg2(void)
85 {
86     uint32_t data;
87     data = 0x5;
88     g_adc_regs->da_lsadc_rwreg_2 = data;
89 }
90 
hal_adc_simu_cfg3(void)91 static inline void hal_adc_simu_cfg3(void)
92 {
93     uint32_t data;
94     data = 0x100;
95     g_adc_regs->da_lsadc_rwreg_3 = data;
96 }
97 
test_hal_adc_simu_cfg3(void)98 inline uint32_t test_hal_adc_simu_cfg3(void)
99 {
100     uint32_t data;
101     data = (uintptr_t)&(g_adc_regs->da_lsadc_rwreg_3);
102     return data;
103 }
104 
hal_adc_simu_ldo_start(void)105 static inline void hal_adc_simu_ldo_start(void)
106 {
107     adc_enable_data_t data;
108     data.d32 = g_adc_regs->lsadc_ctrl_11;
109     data.b.da_lsadc_en |= 0x7000;
110     g_adc_regs->lsadc_ctrl_11 = data.d32;
111 }
112 
hal_adc_simu_cfg4(void)113 static inline void hal_adc_simu_cfg4(void)
114 {
115     adc_enable_data_t data;
116     data.d32 = g_adc_regs->lsadc_ctrl_11;
117     data.b.da_lsadc_en |= 0xE7F;
118     g_adc_regs->lsadc_ctrl_11 = data.d32;
119 }
120 
hal_adc_simu_cfg5(void)121 static inline void hal_adc_simu_cfg5(void)
122 {
123     adc_enable_data_t data;
124     data.d32 = g_adc_regs->lsadc_ctrl_11;
125     data.b.da_lsadc_en |= 0x100;
126     g_adc_regs->lsadc_ctrl_11 = data.d32;
127 }
128 
hal_adc_simu_cfg6(void)129 static inline void hal_adc_simu_cfg6(void)
130 {
131     adc_enable_data_t data;
132     data.d32 = g_adc_regs->lsadc_ctrl_11;
133     data.b.da_lsadc_en |= 0x80;
134     g_adc_regs->lsadc_ctrl_11 = data.d32;
135 }
136 
hal_adc_simu_rst_clr(void)137 static inline void hal_adc_simu_rst_clr(void)
138 {
139     adc_enable_data_t data;
140     data.d32 = g_adc_regs->lsadc_ctrl_11;
141     data.b.da_lsadc_rstn = 1;
142     g_adc_regs->lsadc_ctrl_11 = data.d32;
143 }
144 
hal_adc_offset_cali_state_clr(void)145 static inline void hal_adc_offset_cali_state_clr(void)
146 {
147     adc_offset_cali_state_clr_data_t data;
148     data.d32 = g_adc_regs->cfg_adc_offset_cali_state_clr;
149     data.b.offset_cali_finish_clr = 1;
150     g_adc_regs->cfg_adc_offset_cali_state_clr = data.d32;
151     data.d32 = g_adc_regs->cfg_adc_offset_cali_state_clr;
152     data.b.offset_cali_finish_clr = 0;
153     g_adc_regs->cfg_adc_offset_cali_state_clr = data.d32;
154 }
155 
hal_adc_offset_cali_data_spi_refresh(void)156 static inline void hal_adc_offset_cali_data_spi_refresh(void)
157 {
158     adc_offset_cali_spi_refresh_data_t data;
159     data.d32 = g_adc_regs->cfg_adc_offset_cali_data_spi_refresh;
160     data.b.offset_cali_spi_refresh = 1;
161     g_adc_regs->cfg_adc_offset_cali_data_spi_refresh = data.d32;
162     data.d32 = g_adc_regs->cfg_adc_offset_cali_data_spi_refresh;
163     data.b.offset_cali_spi_refresh = 0;
164     g_adc_regs->cfg_adc_offset_cali_data_spi_refresh = data.d32;
165 }
166 
hal_adc_offset_cali_set(void)167 static inline void hal_adc_offset_cali_set(void)
168 {
169     adc_offset_cali_data_t data;
170     data.d32 = g_adc_regs->cfg_adc_offset_cali;
171     data.b.offset_cali_mode = 1;
172     data.b.offset_cali_loop_sel = 0;
173     data.b.offset_cali_inverse = 0;
174     data.b.offset_cali_acc_cycle_sel = 1;
175     data.b.offset_cali_range_sel = 0;
176     g_adc_regs->cfg_adc_offset_cali = data.d32;
177 }
178 
hal_adc_offset_cali_enable(uint32_t value)179 static inline void hal_adc_offset_cali_enable(uint32_t value)
180 {
181     adc_offset_cali_en_data_t data;
182     data.d32 = g_adc_regs->cfg_adc_offset_cali_en;
183     data.b.offset_cali_en = value;
184     g_adc_regs->cfg_adc_offset_cali_en = data.d32;
185 }
186 
hal_adc_offset_cali_sts(void)187 static inline uint32_t hal_adc_offset_cali_sts(void)
188 {
189     adc_offset_cali_sts_data_t data;
190     data.d32 = g_adc_regs->rpt_adc_offset_cali_finish_sts;
191     return data.b.offset_cali_finish;
192 }
193 
hal_adc_auto_offset_cali_data_get(void)194 static inline uint32_t hal_adc_auto_offset_cali_data_get(void)
195 {
196     adc_rpt_offset_cali_data_t data;
197     data.d32 = g_adc_regs->rpt_adc_offset_cali_data;
198     return data.b.offset_cali_data;
199 }
200 
hal_adc_manual_offset_cali_set(uint32_t value)201 static inline void hal_adc_manual_offset_cali_set(uint32_t value)
202 {
203     adc_offset_cali_data_t data;
204     data.d32 = g_adc_regs->cfg_adc_offset_cali;
205     data.b.offset_cali_mode = 0;
206     data.b.offset_cali_data_spi = value;
207     g_adc_regs->cfg_adc_offset_cali = data.d32;
208 }
209 
hal_adc_cfg_offset_cali_data_enable(void)210 static inline void hal_adc_cfg_offset_cali_data_enable(void)
211 {
212     adc_cfg_offset_cali_en_data_t data;
213     data.d32 = g_adc_regs->cfg_adc_offset_cali_data_en;
214     data.b.offset_data_en = 1;
215     g_adc_regs->cfg_adc_offset_cali_data_en = data.d32;
216 }
217 
hal_adc_cfg_offset_cali_data_disable(void)218 static inline void hal_adc_cfg_offset_cali_data_disable(void)
219 {
220     adc_cfg_offset_cali_en_data_t data;
221     data.d32 = g_adc_regs->cfg_adc_offset_cali_data_en;
222     data.b.offset_data_en = 0;
223     g_adc_regs->cfg_adc_offset_cali_data_en = data.d32;
224 }
225 
hal_adc_cfg_cap_cali_finish_clr(void)226 static inline void hal_adc_cfg_cap_cali_finish_clr(void)
227 {
228     cfg_cap_cali_finish_clr_data_t data;
229     data.d32 = g_adc_regs->cfg_cap_cali_finish_clr;
230     data.b.finish_clr = 1;
231     g_adc_regs->cfg_cap_cali_finish_clr = data.d32;
232     data.d32 = g_adc_regs->cfg_cap_cali_finish_clr;
233     data.b.finish_clr = 0;
234     g_adc_regs->cfg_cap_cali_finish_clr = data.d32;
235 }
236 
hal_adc_cfg_intr_gain_state_clr(void)237 static inline void hal_adc_cfg_intr_gain_state_clr(void)
238 {
239     cfg_intr_gain_state_clr_data_t data;
240     data.d32 = g_adc_regs->cfg_intr_gain_state_clr;
241     data.b.gain_state_clr = 1;
242     g_adc_regs->cfg_intr_gain_state_clr = data.d32;
243     data.d32 = g_adc_regs->cfg_intr_gain_state_clr;
244     data.b.gain_state_clr = 0;
245     g_adc_regs->cfg_intr_gain_state_clr = data.d32;
246 }
247 
hal_adc_date_spi_refresh_clr(void)248 static inline void hal_adc_date_spi_refresh_clr(void)
249 {
250     cfg_cap_cali_data_spi_refresh_data_t data;
251     data.d32 = g_adc_regs->cfg_cap_cali_data_spi_refresh;
252     data.b.spi_refresh = 1;
253     g_adc_regs->cfg_cap_cali_data_spi_refresh = data.d32;
254     data.d32 = g_adc_regs->cfg_cap_cali_data_spi_refresh;
255     data.b.spi_refresh = 0;
256     g_adc_regs->cfg_cap_cali_data_spi_refresh = data.d32;
257 }
258 
hal_adc_cfg_cap_cali_set(void)259 static inline void hal_adc_cfg_cap_cali_set(void)
260 {
261     cfg_adc_cap_cali_data_t data;
262     data.d32 = g_adc_regs->cfg_adc_cap_cali;
263     data.b.mode = 1;
264     data.b.alg_sel = 0;
265     data.b.acc_cycle_sel = 0;
266     data.b.start_index = 0x3;
267     data.b.weight_sel = 1;
268     g_adc_regs->cfg_adc_cap_cali = data.d32;
269 }
270 
hal_adc_cfg_cap_cali_enable(uint32_t value)271 static inline void hal_adc_cfg_cap_cali_enable(uint32_t value)
272 {
273     cfg_adc_cap_cali_en_data_t data;
274     data.d32 = g_adc_regs->cfg_adc_cap_cali_en;
275     data.b.en = value;
276     g_adc_regs->cfg_adc_cap_cali_en = data.d32;
277 }
278 
hal_adc_rpt_cap_cali_sts(void)279 static inline uint32_t hal_adc_rpt_cap_cali_sts(void)
280 {
281     rpt_cap_cali_sts0_data_t data;
282     data.d32 = g_adc_regs->rpt_cap_cali_sts_0;
283     return data.b.finish;
284 }
285 
hal_adc_cfg_gain_cali_enable(void)286 static inline void hal_adc_cfg_gain_cali_enable(void)
287 {
288     cfg_gain_cali_en_data_t data;
289     data.d32 = g_adc_regs->cfg_gain_cali_en;
290     data.b.en = 1;
291     g_adc_regs->cfg_gain_cali_en = data.d32;
292 }
293 
hal_adc_gain_unit_get(void)294 static inline uint32_t hal_adc_gain_unit_get(void)
295 {
296     rpt_intr_gain_cali_gain_data_t data;
297     data.d32 = g_adc_regs->rpt_intr_gain_cali_gain;
298     return data.b.intr_gain_uint;
299 }
300 
hal_adc_fifo_waterline_set(void)301 static inline void hal_adc_fifo_waterline_set(void)
302 {
303     adc_fifo_data_t data;
304     data.d32 = g_adc_regs->lsadc_ctrl_1;
305     data.b.rxintsize = 0x7;
306     g_adc_regs->lsadc_ctrl_1 = data.d32;
307 }
308 
hal_adc_start_sample(void)309 static inline void hal_adc_start_sample(void)
310 {
311     adc_scan_start_and_stop_data_t data;
312     data.d32 = g_adc_regs->lsadc_ctrl_8;
313     data.b.lsadc_start = 1;
314     g_adc_regs->lsadc_ctrl_8 = data.d32;
315 }
316 
test_hal_adc_start(void)317 inline uint32_t test_hal_adc_start(void)
318 {
319     uint32_t data;
320     data = (uintptr_t)&(g_adc_regs->lsadc_ctrl_8);
321     return data;
322 }
323 
hal_adc_stop_sample(void)324 static inline void hal_adc_stop_sample(void)
325 {
326     adc_scan_start_and_stop_data_t data;
327     data.d32 = g_adc_regs->lsadc_ctrl_8;
328     data.b.lsadc_stop = 1;
329     g_adc_regs->lsadc_ctrl_8 = data.d32;
330 }
331 
332 void hal_adc_auto_scan_mode_set(adc_channel_t ch, bool en);
333 
334 #ifdef __cplusplus
335 #if __cplusplus
336 }
337 #endif /* __cplusplus */
338 #endif /* __cplusplus */
339 
340 #endif