1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #ifndef __VOU_DEF_H__ 20 #define __VOU_DEF_H__ 21 22 #include "hi_type.h" 23 24 #ifdef __cplusplus 25 #if __cplusplus 26 extern "C" { 27 #endif 28 #endif /* __cplusplus */ 29 30 #define VO_VHD_BASE_ADDR 0x1000 /* V0's base addr */ 31 #define VO_VSD_BASE_ADDR 0x2000 /* V1's base addr */ 32 #define VO_GFX_BASE_ADDR 0x7000 /* G0's base addr */ 33 #define VO_WBC0_BASE_ADDR 0xC000 /* WBC_DHD0's base addr */ 34 #define VO_DHD_BASE_ADDR 0xD000 /* DHD0's base addr */ 35 #define VO_DSD_BASE_ADDR 0xE000 /* DHD1's base addr */ 36 37 #define VHD_REGS_LEN 0x1000 /* len of V0's regs */ 38 #define VSD_REGS_LEN 0x1000 39 #define GFX_REGS_LEN 0x800 40 #define GFX2_REGS_LEN 0x1000 41 #define WBC_REGS_LEN 0x400 42 #define DHD_REGS_LEN 0x1000 43 #define DSD_REGS_LEN 0x400 44 #define INTF_REGS_LEN 0x100 45 #define VID_REGS_LEN 0x200 /* len of VID regs */ 46 #define GRF_REGS_LEN 0x200 /* len of GFX regs */ 47 #define MRG_REGS_LEN 0xc00 /* len of v0 mrg regs */ 48 49 #define MRG_OFFSET_ADDR 0x12000 50 51 /* offset define */ 52 #define FDR_VID_OFFSET (0x200 / 4) 53 #define FDR_GFX_OFFSET (0x200 / 4) 54 #define CAP_WBC_OFFSET (0x200 / 4) 55 56 /* architecture define */ 57 #define VID_MAX 3 58 #define GFX_MAX 3 59 #define WBC_MAX 1 60 #define PARA_MAX 2 61 62 /* for driver WBC resolution */ 63 #define VO_WBC_MIN_WIDTH 32 /* min WBC width */ 64 #define VO_WBC_MIN_HEIGHT 32 /* min WBC height */ 65 #define VO_WBC_MAX_WIDTH 1920 /* max WBC width */ 66 #define VO_WBC_MAX_HEIGHT 1080 /* max WBC height */ 67 /* 1920 */ /* max WBC height for mipi_tx */ 68 /* value define */ 69 #define ZME_HPREC (1 << 20) 70 #define ZME_VPREC (1 << 12) 71 72 /* defined for ZME */ 73 #define MAX_OFFSET 3 74 #define MIN_OFFSET (-1) 75 76 typedef enum { 77 VO_DEV_DHD0 = 0, /* ultra high definition device */ 78 VO_DEV_DHD1 = 1, /* high definition device */ 79 VO_DEV_BUTT 80 } vo_hal_dev; 81 82 typedef enum { 83 VO_HAL_LAYER_VHD0 = 0, /* V0 layer */ 84 VO_HAL_LAYER_VHD1 = 1, /* V1 layer */ 85 VO_HAL_LAYER_VHD2 = 2, /* V2 layer */ 86 87 VO_HAL_LAYER_G0 = 3, /* G0 layer */ 88 VO_HAL_LAYER_G1 = 4, /* G1 layer */ 89 VO_HAL_LAYER_G2 = 5, /* G2 layer */ 90 VO_HAL_LAYER_G3 = 6, /* G3 layer */ 91 92 VO_HAL_LAYER_WBC = 7, /* wbc layer */ 93 94 VO_HAL_LAYER_BUTT 95 } vo_hal_layer; 96 97 typedef enum { 98 VO_SW_LAYER_VHD0 = 0, 99 VO_SW_LAYER_VHD1 = 1, 100 VO_SW_LAYER_VHD2 = 2, 101 102 VOU_SW_LAYER_BUTT 103 } vo_sw_layer; 104 105 typedef enum { 106 HAL_DISP_CHANNEL_DHD0 = 0, 107 HAL_DISP_CHANNEL_DHD1 = 1, 108 109 HAL_DISP_CHANNEL_WBC = 2, 110 111 HAL_DISP_CHANNEL_NONE = 3, 112 113 HAL_DISP_CHANNEL_BUTT 114 } hal_disp_outputchannel; 115 116 typedef enum { 117 HAL_DISP_LAYER_VHD0 = 0, 118 HAL_DISP_LAYER_VHD1 = 1, 119 HAL_DISP_LAYER_VHD2 = 2, 120 121 HAL_DISP_LAYER_GFX0 = 3, 122 HAL_DISP_LAYER_GFX1 = 4, 123 HAL_DISP_LAYER_GFX2 = 5, /* not used */ 124 HAL_DISP_LAYER_GFX3 = 6, /* for hardware cursor */ 125 126 HAL_DISP_LAYER_WBC = 7, 127 128 HAL_DISP_LAYER_TT = 8, 129 HAL_DISP_LAYER_BUTT, 130 HAL_DISP_INVALID_LAYER = -1 131 } hal_disp_layer; 132 133 typedef enum { 134 VO_DEV_INDEX0 = 0, 135 136 VO_DEV_INDEX_BUTT, 137 }vo_dev_index; 138 139 typedef enum { 140 VO_CHANNEL_INDEX0 = 0, 141 142 VO_CHANNEL_INDEX_BUITT, 143 }vo_channel_index; 144 145 typedef enum { 146 GX_LAYER_INDEX0 = 0, 147 148 GX_LAYER_INDEX_BUTT, 149 }gx_layer_index; 150 151 typedef enum { 152 HAL_LAYER_WBC_HD0 = 0, 153 HAL_LAYER_WBC_BUTT 154 } hal_layer_wbc; 155 156 #define LAYER_VHD_START HAL_DISP_LAYER_VHD0 /* VHD0 */ 157 #define LAYER_VHD_END HAL_DISP_LAYER_VHD0 /* VHD0 */ 158 159 #define LAYER_MRG_START HAL_DISP_LAYER_VHD0 160 #define LAYER_MRG_END HAL_DISP_LAYER_VHD0 161 162 #define LAYER_GFX_START HAL_DISP_LAYER_GFX0 /* GFX0 */ 163 #define LAYER_GFX_END HAL_DISP_LAYER_GFX0 /* GFX0 */ 164 #define LAYER_WBC_START HAL_DISP_LAYER_WBC /* WBC */ 165 #define LAYER_WBC_END HAL_DISP_LAYER_WBC /* WBC */ 166 167 /* for multi area */ 168 #define MULTI_AREA_CFG_LEN (4 * 8) 169 #define MULTI_AREA_1RGN 1 170 #define MULTI_AREA_16RGN 16 171 #define MULTI_AREA_32RGN 32 172 #define MULTI_AREA_64RGN 64 173 174 typedef enum { 175 HAL_DISP_INTERLACE = 0, 176 HAL_DISP_PROGRESSIVE = 1, 177 HAL_DISP_TOP, 178 HAL_DISP_BOTTOM, 179 180 HAL_DISP_DATARMODE_BUTT 181 } hal_disp_datarmode; 182 183 typedef enum { 184 HAL_INPUTFMT_YCBCR_SEMIPLANAR_400 = 0x1, 185 /* hal_inputfmt_y_cb_cr_semiplanar_411_1_x4 = 0x2, */ 186 HAL_INPUTFMT_YCBCR_SEMIPLANAR_420 = 0x2, 187 HAL_INPUTFMT_YCBCR_SEMIPLANAR_422 = 0x3, 188 /* hal_inputfmt_y_cb_cr_semiplanar_422_1_x2 = 0x4, */ 189 HAL_INPUTFMT_YCBCR_SEMIPLANAR_444 = 0x4, 190 HAL_INPUTFMT_YCBCR_SEMIPLANAR_411_4X1 = 0x6, 191 HAL_INPUTFMT_YCBCR_SEMIPLANAR_422_2X1 = 0x7, 192 193 HAL_INPUTFMT_CBYCRY_PACKAGE_422 = 0x9, 194 HAL_INPUTFMT_YCBYCR_PACKAGE_422 = 0xa, 195 HAL_INPUTFMT_YCRYCB_PACKAGE_422 = 0xb, 196 HAL_INPUTFMT_YCBCR_PACKAGE_444 = 0x1000, 197 198 HAL_INPUTFMT_CLUT_1BPP = 0x00, 199 HAL_INPUTFMT_CLUT_2BPP = 0x10, 200 HAL_INPUTFMT_CLUT_4BPP = 0x20, 201 HAL_INPUTFMT_CLUT_8BPP = 0x30, 202 HAL_INPUTFMT_ACLUT_44 = 0x38, 203 204 HAL_INPUTFMT_RGB_444 = 0x40, 205 HAL_INPUTFMT_RGB_555 = 0x41, 206 HAL_INPUTFMT_RGB_565 = 0x42, 207 HAL_INPUTFMT_CBYCRY_PACKAGE_422_GRC = 0x43, 208 HAL_INPUTFMT_YCBYCR_PACKAGE_422_GRC = 0x44, 209 HAL_INPUTFMT_YCRYCB_PACKAGE_422_GRC = 0x45, 210 HAL_INPUTFMT_ACLUT_88 = 0x46, 211 HAL_INPUTFMT_ARGB_4444 = 0x48, 212 HAL_INPUTFMT_ARGB_1555 = 0x49, 213 214 HAL_INPUTFMT_RGB_888 = 0x50, 215 HAL_INPUTFMT_YCBCR_888 = 0x51, 216 HAL_INPUTFMT_ARGB_8565 = 0x5a, 217 HAL_INPUTFMT_ARGB_6666 = 0x5b, 218 219 HAL_INPUTFMT_KRGB_888 = 0x60, 220 HAL_INPUTFMT_ARGB_8888 = 0x68, 221 HAL_INPUTFMT_AYCBCR_8888 = 0x69, 222 223 HAL_INPUTFMT_RGBA_4444 = 0xc8, 224 HAL_INPUTFMT_RGBA_5551 = 0xc9, 225 226 HAL_INPUTFMT_RGBA_6666 = 0xd8, 227 HAL_INPUTFMT_RGBA_5658 = 0xda, 228 229 HAL_INPUTFMT_RGBA_8888 = 0xe8, 230 HAL_INPUTFMT_YCBCRA_8888 = 0xe9, 231 232 HAL_DISP_PIXELFORMAT_BUTT 233 } hal_disp_pixel_format; 234 235 typedef enum { 236 HAL_DISP_INTFDATAFMT_SPCBYCRY_422 = 0x0, 237 HAL_DISP_INTFDATAFMT_SPYCBYCR_422 = 0x1, 238 HAL_DISP_INTFDATAFMT_SPYCRYCB_422 = 0x2, 239 240 HAL_DISP_INTFDATAFMT_ARGB8888 = 0x3, 241 HAL_DISP_INTFDATAFMT_YCBCR420 = 0x4, 242 HAL_DISP_INTFDATAFMT_YCBCR422 = 0x5, 243 244 HAL_DISP_INTFDATAFMT_BUTT 245 } hal_disp_intfdatafmt; 246 247 typedef enum { 248 HAL_CS_UNKNOWN = 0, 249 HAL_CS_BT601, 250 HAL_CS_BT709, 251 HAL_CS_BT2020, 252 HAL_CS_RGB, 253 HAL_CS_BUTT 254 } hal_cs; 255 256 typedef enum { 257 HAL_CSC_MODE_NONE = 0, 258 259 HAL_CSC_MODE_BT601_TO_BT601, 260 HAL_CSC_MODE_BT709_TO_BT709, 261 HAL_CSC_MODE_RGB_TO_RGB, 262 263 HAL_CSC_MODE_BT601_TO_BT709, 264 HAL_CSC_MODE_BT709_TO_BT601, 265 266 HAL_CSC_MODE_BT601_TO_RGB_PC, 267 HAL_CSC_MODE_BT709_TO_RGB_PC, 268 HAL_CSC_MODE_BT2020_TO_RGB_PC, 269 HAL_CSC_MODE_RGB_TO_BT601_PC, 270 HAL_CSC_MODE_RGB_TO_BT709_PC, 271 HAL_CSC_MODE_RGB_TO_BT2020_PC, 272 273 HAL_CSC_MODE_BT601_TO_RGB_TV, 274 HAL_CSC_MODE_BT709_TO_RGB_TV, 275 HAL_CSC_MODE_RGB_TO_BT601_TV, 276 HAL_CSC_MODE_RGB_TO_BT709_TV, 277 278 HAL_CSC_MODE_BUTT 279 } hal_csc_mode; 280 281 typedef enum { 282 HAL_DISP_BIT_WIDTH_1 = 0x0, 283 HAL_DISP_BIT_WIDTH_2 = 0x1, 284 HAL_DISP_BIT_WIDTH_3 = 0x3, 285 HAL_DISP_BIT_WIDTH_BUTT 286 } hal_disp_bit_width; 287 288 typedef enum { 289 HAL_CCD_IMGID_INVALID, 290 HAL_CCD_IMGID_1080P60, 291 HAL_CCD_IMGID_1080P30_ODD, 292 HAL_CCD_IMGID_1080P30_EVEN, 293 } hal_ccd_imgid; 294 295 typedef enum { 296 HAL_T_FIRST = 0, 297 HAL_B_FIRST = 1, 298 299 HAL_VHD_FOD_BUTT 300 } hal_vhd_fod; 301 302 /* vou coef load mode */ 303 typedef enum { 304 HAL_DISP_COEFMODE_HORL = 0, 305 HAL_DISP_COEFMODE_HORC, 306 HAL_DISP_COEFMODE_VERL, 307 HAL_DISP_COEFMODE_VERC, 308 HAL_DISP_COEFMODE_LUT, 309 HAL_DISP_COEFMODE_GAM, 310 HAL_DISP_COEFMODE_ACC, 311 HAL_DISP_COEFMODE_ALL 312 } hal_disp_coefmode; 313 314 /* vou zoom mode */ 315 typedef enum { 316 HAL_DISP_ZMEMODE_HORL = 0, 317 HAL_DISP_ZMEMODE_HORC, 318 HAL_DISP_ZMEMODE_VERL, 319 HAL_DISP_ZMEMODE_VERC, 320 321 HAL_DISP_ZMEMODE_HOR, 322 HAL_DISP_ZMEMODE_VER, 323 HAL_DISP_ZMEMODE_ALPHA, 324 HAL_DISP_ZMEMODE_ALPHAV, 325 HAL_DISP_ZMEMODE_VERT, 326 HAL_DISP_ZMEMODE_VERB, 327 328 HAL_DISP_ZMEMODE_ALL, 329 HAL_DISP_ZMEMODE_NONL, 330 HAL_DISP_ZMEMODE_BUTT 331 } hal_disp_zmemode; 332 333 /* 334 * vou zoom format : 420 or 422 or 444 335 */ 336 typedef enum { 337 HAL_DISP_ZME_OUTFMT420 = 0, 338 HAL_DISP_ZME_OUTFMT422, 339 HAL_DISP_ZME_OUTFMT444, 340 HAL_DISP_ZME_OUTFMT_BUTT 341 } hal_disp_zme_outfmt; 342 343 /* vou CBM MIXER */ 344 typedef enum { 345 HAL_CBMMIX1 = 0, 346 HAL_CBMMIX2 = 1, 347 HAL_CBMMIX3 = 2, 348 349 HAL_CBMMIX1_BUTT 350 } hal_cbmmix; 351 352 /* vou graphic layer data extend mode */ 353 typedef enum { 354 HAL_GFX_BITEXTEND_1ST = 0, 355 HAL_GFX_BITEXTEND_2ND = 0x2, 356 HAL_GFX_BITEXTEND_3RD = 0x3, 357 358 HAL_GFX_BITEXTEND_BUTT 359 } hal_gfx_bitextend; 360 361 typedef enum { 362 HAL_DISP_SYNC_MODE_TIMING = 0x0, 363 HAL_DISP_SYNC_MODE_SIGNAL = 0x1, 364 HAL_DISP_SYNC_MODE_BUTT 365 } hal_disp_sync_mode; 366 367 /* RM frame or field information */ 368 typedef enum { 369 HAL_IFIRMODE_DISEN = 0, 370 HAL_IFIRMODE_COPY, 371 HAL_IFIRMODE_DOUBLE, 372 HAL_IFIRMODE_6TAPFIR, 373 374 HAL_IFIRMODE_BUTT 375 } hal_ifirmode; 376 377 typedef enum { 378 HAL_HFIRMODE_MEDEN = 0, /* median filtering enable */ 379 HAL_HFIRMODE_COPY, /* chroma HFIR copy */ 380 HAL_HFIRMODE_DOUBLE, /* bilinear interpolation */ 381 HAL_HFIRMODE_6TAPFIR, /* 6 order FIR */ 382 383 HAL_HFIRMODE_BUTT 384 } hal_hfirmode; 385 386 /* vou mixer prio id */ 387 typedef enum { 388 HAL_DISP_MIX_PRIO0 = 0, 389 HAL_DISP_MIX_PRIO1, 390 HAL_DISP_MIX_PRIO2, 391 HAL_DISP_MIX_PRIO3, 392 /* HAL_DISP_MIX_PRIO4, */ 393 /* HAL_DISP_MIX_PRIO5, */ 394 /* HAL_DISP_MIX_PRIO6, */ 395 HAL_DISP_MIX_BUTT 396 } hal_disp_mix_prio; 397 398 /* vou layer select ddr id */ 399 typedef enum { 400 HAL_LAYER_DDR0 = 0, 401 /* HAL_LAYER_DDR1 = 1, */ 402 HAL_LAYER_DDR_BUTT 403 } hal_layer_ddr_sel; 404 405 /* LTI/CTI mode */ 406 typedef enum { 407 HAL_DISP_TIMODE_LUM = 0, 408 HAL_DISP_TIMODE_CHM, 409 410 HAL_DISP_TIMODE_ALL, 411 HAL_DISP_TIMODE_NON, 412 HAL_DISP_TIMODE_BUTT, 413 } hal_disp_timode; 414 415 typedef struct { 416 hi_u32 synm; 417 hi_u32 iop; 418 hi_u8 intfb; 419 420 hi_u16 vact; 421 hi_u16 vbb; 422 hi_u16 vfb; 423 424 hi_u16 hact; 425 hi_u16 hbb; 426 hi_u16 hfb; 427 hi_u16 hmid; 428 429 hi_u16 bvact; 430 hi_u16 bvbb; 431 hi_u16 bvfb; 432 433 hi_u16 hpw; 434 hi_u16 vpw; 435 436 hi_u32 idv; 437 hi_u32 ihs; 438 hi_u32 ivs; 439 } hal_disp_syncinfo; 440 441 typedef enum { 442 HAL_DISP_INTF_CVBS = (0x01L << 0), 443 HAL_DISP_INTF_HDDATE = (0x01L << 1), 444 HAL_DISP_INTF_VGA = (0x01L << 2), 445 HAL_DISP_INTF_BT656 = (0x01L << 3), 446 HAL_DISP_INTF_BT1120 = (0x01L << 4), 447 HAL_DISP_INTF_HDMI = (0x01L << 5), 448 HAL_DISP_INTF_LCD = (0x01L << 6), 449 HAL_DISP_INTF_DATE = (0x01L << 7), 450 HAL_DISP_INTF_LCD_6BIT = (0x01L << 9), 451 HAL_DISP_INTF_LCD_8BIT = (0x01L << 10), 452 HAL_DISP_INTF_LCD_16BIT = (0x01L << 11), 453 HAL_DISP_INTF_LCD_18BIT = (0x01L << 12), 454 HAL_DISP_INTF_LCD_24BIT = (0x01L << 13), 455 HAL_DISP_INTF_MIPI = (0x01L << 14), 456 HAL_DISP_INTF_MIPI_SLAVE = (0x01L << 15), 457 HAL_DISP_INTF_BUTT = (0x01L << 16), 458 } hal_disp_intf; 459 460 typedef struct { 461 hi_u32 f_inv; 462 hi_u32 vs_inv; 463 hi_u32 hs_inv; 464 hi_u32 dv_inv; 465 } hal_disp_syncinv; 466 467 typedef enum { 468 HAL_MULTICHN_EN_1P1C = 0x1, /* 1 pixel / 1 cycle */ 469 HAL_MULTICHN_EN_2P1C = 0x2, /* 2 pixel / 1 cycle */ 470 } hal_multichn_en; 471 472 /* vou background color */ 473 474 typedef struct { 475 hi_u16 boundary_y[2]; 476 hi_u16 boundary_cb[2]; 477 hi_u16 boundary_cr[2]; 478 } hal_disp_boundary_color; 479 480 typedef struct { 481 hi_u16 bkg_a; 482 hi_u16 bkg_y; 483 hi_u16 bkg_cb; 484 hi_u16 bkg_cr; 485 } hal_disp_bkcolor; 486 487 typedef struct { 488 hi_u16 bkg_y; 489 hi_u16 bkg_cb; 490 hi_u16 bkg_cr; 491 } hal_video_layer_bkcolor; 492 493 typedef struct { 494 hi_u16 clip_low_y; 495 hi_u16 clip_low_cb; 496 hi_u16 clip_low_cr; 497 498 hi_u16 clip_high_y; 499 hi_u16 clip_high_cb; 500 hi_u16 clip_high_cr; 501 } hal_disp_clip; 502 503 typedef struct { 504 hi_u32 acc_multi; 505 hi_u32 thd_med_high; 506 hi_u32 thd_med_low; 507 hi_u32 thd_high; 508 hi_u32 thd_low; 509 } accthd; 510 511 typedef struct { 512 hi_s32 sx; /* source horizontal start position */ 513 hi_s32 sy; /* source vertical start position */ 514 515 hi_s32 dxs; /* display horizontal start position */ 516 hi_s32 dys; /* display vertical start position */ 517 518 hi_s32 dxl; /* display horizontal end position */ 519 hi_s32 dyl; /* display vertical end position */ 520 521 hi_s32 vx; /* video horizontal start position */ 522 hi_s32 vy; /* video vertical start position */ 523 524 hi_u32 in_width; /* input width */ 525 hi_u32 in_height; /* input height */ 526 hi_u32 out_width; /* output width */ 527 hi_u32 out_height; /* output height */ 528 } hal_disp_rect; 529 530 typedef struct { 531 hi_u32 dither_sed_y0; 532 hi_u32 dither_sed_u0; 533 hi_u32 dither_sed_v0; 534 hi_u32 dither_sed_w0; 535 536 hi_u32 dither_sed_y1; 537 hi_u32 dither_sed_u1; 538 hi_u32 dither_sed_v1; 539 hi_u32 dither_sed_w1; 540 541 hi_u32 dither_sed_y2; 542 hi_u32 dither_sed_u2; 543 hi_u32 dither_sed_v2; 544 hi_u32 dither_sed_w2; 545 546 hi_u32 dither_sed_y3; 547 hi_u32 dither_sed_u3; 548 hi_u32 dither_sed_v3; 549 hi_u32 dither_sed_w3; 550 } hal_disp_dihter_sed; 551 552 /* vou graphic layer mask */ 553 typedef struct { 554 hi_u8 mask_r; 555 hi_u8 mask_g; 556 hi_u8 mask_b; 557 } hal_gfx_mask; 558 559 typedef struct { 560 hi_u8 key_max_r; 561 hi_u8 key_max_g; 562 hi_u8 key_max_b; 563 } hal_gfx_key_max; 564 565 typedef struct { 566 hi_u8 key_min_r; 567 hi_u8 key_min_g; 568 hi_u8 key_min_b; 569 } hal_gfx_key_min; 570 571 typedef struct { 572 hi_u32 sx; 573 hi_u32 x; 574 hi_u32 y; 575 576 hi_u32 wth; 577 hi_u32 hgt; 578 } vdp_rect; 579 580 typedef enum { 581 VDP_REQ_LENGTH_16 = 0, 582 VDP_REQ_LENGTH_8 = 1, 583 VDP_REQ_LENGTH_4 = 2, 584 VDP_REQ_LENGTH_BUTT 585 } vdp_req_length; 586 587 typedef enum { 588 VDP_DATA_WTH_8 = 0, 589 VDP_DATA_WTH_10 = 1, 590 VDP_DATA_WTH_BUTT 591 } vdp_data_wth; 592 593 typedef enum { 594 VDP_LAYER_VID0 = 0, 595 VDP_LAYER_VID1 = 1, 596 VDP_LAYER_VID2 = 2, 597 VDP_LAYER_VID3 = 3, 598 VDP_LAYER_VID4 = 4, 599 VDP_LAYER_VID5 = 5, 600 VDP_LAYER_VID6 = 6, /* for FI pixel */ 601 VDP_LAYER_VID7 = 7, /* for FI info */ 602 603 VDP_LAYER_VID_BUTT 604 } vdp_layer_vid; 605 606 typedef enum { 607 VDP_VID_IFMT_SP_400 = 0x1, 608 VDP_VID_IFMT_SP_420 = 0x3, 609 VDP_VID_IFMT_SP_422 = 0x4, 610 VDP_VID_IFMT_SP_444 = 0x5, 611 VDP_VID_IFMT_SP_TILE = 0x6, 612 VDP_VID_IFMT_SP_TILE_64 = 0x7, 613 VDP_VID_IFMT_PKG_UYVY = 0x9, 614 VDP_VID_IFMT_PKG_YUYV = 0xa, 615 VDP_VID_IFMT_PKG_YVYU = 0xb, 616 VDP_VID_IFMT_PKG_12 = 0xc, 617 VDP_VID_IFMT_RGB_888 = 0x8, 618 VDP_VID_IFMT_PKG_YUV444 = 0xe, 619 VDP_VID_IFMT_ARGB_8888 = 0xf, 620 VDP_VID_IFMT_BUTT 621 } vdp_vid_ifmt; 622 623 typedef enum { 624 VDP_RMODE_INTERFACE = 0, 625 VDP_RMODE_INTERLACE = 0, 626 VDP_RMODE_PROGRESSIVE = 1, 627 VDP_RMODE_TOP = 2, 628 VDP_RMODE_BOTTOM = 3, 629 VDP_RMODE_PRO_TOP = 4, 630 VDP_RMODE_PRO_BOTTOM = 5, 631 VDP_RMODE_BUTT 632 } vdp_data_rmode; 633 634 /* graphics layer */ 635 typedef enum { 636 VDP_GFX_IFMT_CLUT_1BPP = 0x00, 637 VDP_GFX_IFMT_CLUT_2BPP = 0x10, 638 VDP_GFX_IFMT_CLUT_4BPP = 0x20, 639 VDP_GFX_IFMT_CLUT_8BPP = 0x30, 640 641 VDP_GFX_IFMT_ACLUT_44 = 0x38, 642 643 VDP_GFX_IFMT_RGB_444 = 0x40, 644 VDP_GFX_IFMT_RGB_555 = 0x41, 645 VDP_GFX_IFMT_RGB_565 = 0x42, 646 647 VDP_GFX_IFMT_PKG_UYVY = 0x43, 648 VDP_GFX_IFMT_PKG_YUYV = 0x44, 649 VDP_GFX_IFMT_PKG_YVYU = 0x45, 650 651 VDP_GFX_IFMT_ACLUT_88 = 0x46, 652 VDP_GFX_IFMT_ARGB_4444 = 0x48, 653 VDP_GFX_IFMT_ARGB_1555 = 0x49, 654 655 VDP_GFX_IFMT_RGB_888 = 0x50, /* 24bpp */ 656 VDP_GFX_IFMT_YCBCR_888 = 0x51, /* 24bpp */ 657 VDP_GFX_IFMT_ARGB_8565 = 0x5a, /* 24bpp */ 658 659 VDP_GFX_IFMT_KRGB_888 = 0x60, 660 VDP_GFX_IFMT_ARGB_8888 = 0x68, 661 VDP_GFX_IFMT_AYCBCR_8888 = 0x69, 662 663 VDP_GFX_IFMT_RGBA_4444 = 0xc8, 664 VDP_GFX_IFMT_RGBA_5551 = 0xc9, 665 VDP_GFX_IFMT_RGBA_5658 = 0xda, /* 24bpp */ 666 VDP_GFX_IFMT_RGBA_8888 = 0xe8, 667 VDP_GFX_IFMT_YCBCRA_8888 = 0xe9, 668 VDP_GFX_IFMT_ABGR_8888 = 0xef, 669 670 VDP_GFX_IFMT_STILL_888 = 0x100, /* only use by environment */ 671 672 VDP_GFX_IFMT_BUTT 673 } vdp_gfx_ifmt; 674 675 typedef enum { 676 VDP_PROC_FMT_SP_420 = 0x0, 677 VDP_PROC_FMT_SP_422 = 0x1, 678 VDP_PROC_FMT_SP_444 = 0x2, /* plannar,in YUV color domain */ 679 VDP_PROC_FMT_RGB_888 = 0x3, /* package,in RGB color domain */ 680 VDP_PROC_FMT_RGB_444 = 0x4, /* plannar,in RGB color domain */ 681 682 VDP_PROC_FMT_BUTT 683 } vdp_proc_fmt; 684 685 typedef enum { 686 VDP_CSC_YUV2YUV = 1, 687 VDP_CSC_YUV2RGB_601, 688 VDP_CSC_YUV2RGB_709, 689 VDP_CSC_YUV2YUV_709_601, 690 VDP_CSC_YUV2YUV_601_709, 691 VDP_CSC_RGB2YUV_601, 692 VDP_CSC_RGB2YUV_709, 693 VDP_CSC_YUV2YUV_MAX, 694 VDP_CSC_YUV2YUV_MIN, 695 VDP_CSC_YUV2YUV_RAND, 696 697 VDP_CSC_BUTT 698 } vdp_csc_mode; 699 700 typedef struct { 701 hi_u32 bkg_y; 702 hi_u32 bkg_u; 703 hi_u32 bkg_v; 704 705 hi_u32 bkg_a; 706 707 hi_u32 bk_type; 708 } vdp_bkg; 709 710 typedef enum { 711 ALIGN_MODE_32BURST = 0x0, 712 ALIGN_MODE_16BURST = 0x1, 713 714 ALIGN_MODE_BUTT 715 } vo_wbc_align_mode; 716 717 typedef struct { 718 hi_s32 luma; 719 hi_s32 cont; 720 hi_s32 hue; 721 hi_s32 satu; 722 } hal_csc_value; 723 724 #ifdef __cplusplus 725 #if __cplusplus 726 } 727 #endif 728 #endif /* __cplusplus */ 729 #endif /* __VOU_DEF_H__ */ 730