1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18 #include "vou_hal.h"
19 #include "hi_osal.h"
20 #include "hi_board.h"
21 #include "hi_comm_vo_adapt.h"
22 #include "vou_coef.h"
23 #include "hi_math_adapt.h"
24 #include "vou_drv.h"
25
26 #ifdef __cplusplus
27 #if __cplusplus
28 extern "C" {
29 #endif
30 #endif /* end of #ifdef __cplusplus */
31
32 #define HAL_PRINT HI_PRINT
33
34 /* for CMP and DCMP */
35 #define CMP_SEG_OFFSET (0x80 / 4)
36 #define DCMP_SEG_OFFSET (0x20 / 4)
37
38 #define REG_BYTES 4
39
40 volatile S_VDP_REGS_TYPE *g_vo_reg = HI_NULL;
41
hal_vou_init(hi_void)42 hi_void hal_vou_init(hi_void)
43 {
44 if (g_vo_reg == HI_NULL) {
45 g_vo_reg = (volatile S_VDP_REGS_TYPE *)osal_ioremap(VOU_REGS_ADDR, (hi_u32)VOU_REGS_SIZE);
46 }
47
48 if (g_vo_reg == HI_NULL) {
49 osal_printk("ioremap_nocache failed\n");
50 }
51 }
52
hal_vou_exit(hi_void)53 hi_void hal_vou_exit(hi_void)
54 {
55 }
56
hal_write_reg(hi_u32 * address,hi_u32 value)57 hi_void hal_write_reg(hi_u32 *address, hi_u32 value)
58 {
59 vo_coef_addr *coef_addr = vo_drv_get_coef_buf_addr();
60 hi_u32 addr = VOU_REGS_ADDR + (hi_ulong)(hi_uintptr_t)address - (hi_ulong)(hi_uintptr_t)(&(g_vo_reg->VOCTRL.u32));
61 hi_u32 *tmp = HI_NULL;
62 hi_u32 v0_mrg_addr = VOU_REGS_ADDR + MRG_OFFSET_ADDR;
63 hi_u32 v1_mrg_addr = v0_mrg_addr + MRG_REGS_LEN;
64
65 if ((addr >= v0_mrg_addr) && (addr < v0_mrg_addr + MRG_REGS_LEN)) {
66 tmp = (addr - v0_mrg_addr) / REG_BYTES + (hi_u32 *)coef_addr->coef_vir_addr[VO_COEF_BUF_REGION_V0];
67 *(volatile hi_u32 *)tmp = value;
68 } else if ((addr >= v1_mrg_addr) && (addr < v1_mrg_addr + MRG_REGS_LEN)) {
69 tmp = (addr - v1_mrg_addr) / REG_BYTES + (hi_u32 *)coef_addr->coef_vir_addr[VO_COEF_BUF_REGION_V1];
70 *(volatile hi_u32 *)tmp = value;
71 } else {
72 *(volatile hi_u32 *)address = value;
73 }
74
75 return;
76 }
77
hal_read_reg(const hi_u32 * address)78 hi_u32 hal_read_reg(const hi_u32 *address)
79 {
80 vo_coef_addr *coef_addr = vo_drv_get_coef_buf_addr();
81 hi_u32 addr = VOU_REGS_ADDR + (hi_ulong)(hi_uintptr_t)address - (hi_ulong)(hi_uintptr_t)(&(g_vo_reg->VOCTRL.u32));
82 hi_u32 *tmp = HI_NULL;
83
84 hi_u32 v0_mrg_addr = VOU_REGS_ADDR + MRG_OFFSET_ADDR;
85 hi_u32 v1_mrg_addr = v0_mrg_addr + MRG_REGS_LEN;
86
87 if ((addr >= v0_mrg_addr) && (addr < v0_mrg_addr + MRG_REGS_LEN)) {
88 tmp = (addr - v0_mrg_addr) / REG_BYTES + (hi_u32 *)coef_addr->coef_vir_addr[VO_COEF_BUF_REGION_V0];
89 return *(volatile hi_u32 *)tmp;
90 } else if ((addr >= v1_mrg_addr) && (addr < v1_mrg_addr + MRG_REGS_LEN)) {
91 tmp = (addr - v1_mrg_addr) / REG_BYTES + (hi_u32 *)coef_addr->coef_vir_addr[VO_COEF_BUF_REGION_V1];
92 return *(volatile hi_u32 *)tmp;
93 } else {
94 return *(volatile hi_u32 *)(address);
95 }
96 }
97
vou_get_abs_addr(hal_disp_layer layer,hi_ulong reg)98 hi_ulong vou_get_abs_addr(hal_disp_layer layer, hi_ulong reg)
99 {
100 hi_ulong reg_abs_addr;
101
102 switch (layer) {
103 case HAL_DISP_LAYER_VHD0: {
104 reg_abs_addr = (reg) + (layer - HAL_DISP_LAYER_VHD0) * VHD_REGS_LEN;
105 break;
106 }
107
108 case HAL_DISP_LAYER_GFX0: {
109 reg_abs_addr = (reg) + (layer - HAL_DISP_LAYER_GFX0) * GFX_REGS_LEN;
110 break;
111 }
112
113 default: {
114 return 0;
115 }
116 }
117
118 return reg_abs_addr;
119 }
120
vou_get_chn_abs_addr(hal_disp_outputchannel chan,hi_ulong reg)121 hi_ulong vou_get_chn_abs_addr(hal_disp_outputchannel chan, hi_ulong reg)
122 {
123 volatile hi_ulong reg_abs_addr;
124
125 switch (chan) {
126 case HAL_DISP_CHANNEL_DHD0:
127 case HAL_DISP_CHANNEL_DHD1: {
128 reg_abs_addr = reg + (chan - HAL_DISP_CHANNEL_DHD0) * DHD_REGS_LEN;
129 break;
130 }
131
132 default: {
133 return 0;
134 }
135 }
136
137 return reg_abs_addr;
138 }
139
vou_get_hdmi_or_mipi_intf_abs_addr(hal_disp_intf intf,hi_ulong reg)140 hi_ulong vou_get_hdmi_or_mipi_intf_abs_addr(hal_disp_intf intf, hi_ulong reg)
141 {
142 volatile hi_ulong reg_abs_addr;
143
144 switch (intf) {
145 case HAL_DISP_INTF_HDMI: {
146 reg_abs_addr = reg;
147 break;
148 }
149
150 case HAL_DISP_INTF_MIPI:
151 case HAL_DISP_INTF_MIPI_SLAVE: {
152 reg_abs_addr = reg + 0x80; /* 0x80: the offset of reg INTF_MIPI_CTRL */
153 break;
154 }
155 default: {
156 return 0;
157 }
158 }
159
160 return reg_abs_addr;
161 }
162
vou_get_intf_abs_addr(hal_disp_intf intf,hi_ulong reg)163 hi_ulong vou_get_intf_abs_addr(hal_disp_intf intf, hi_ulong reg)
164 {
165 volatile hi_ulong reg_abs_addr;
166 hi_u32 bt_offset = 1;
167 hi_u32 lcd_offset = 2;
168
169 switch (intf) {
170 case HAL_DISP_INTF_HDMI: {
171 reg_abs_addr = reg;
172 break;
173 }
174
175 case HAL_DISP_INTF_MIPI:
176 case HAL_DISP_INTF_MIPI_SLAVE: {
177 reg_abs_addr = reg + 0x80; /* 0x80: the offset of reg INTF_MIPI_CTRL */
178 break;
179 }
180
181 case HAL_DISP_INTF_BT656:
182 case HAL_DISP_INTF_BT1120: {
183 reg_abs_addr = reg + bt_offset * INTF_REGS_LEN;
184 break;
185 }
186
187 case HAL_DISP_INTF_LCD:
188 case HAL_DISP_INTF_LCD_6BIT:
189 case HAL_DISP_INTF_LCD_8BIT:
190 case HAL_DISP_INTF_LCD_16BIT:
191 case HAL_DISP_INTF_LCD_18BIT:
192 case HAL_DISP_INTF_LCD_24BIT: {
193 reg_abs_addr = reg + lcd_offset * INTF_REGS_LEN;
194 break;
195 }
196
197 default: {
198 return 0;
199 }
200 }
201
202 return reg_abs_addr;
203 }
204
vou_get_vid_abs_addr(hal_disp_layer layer,hi_ulong reg)205 hi_ulong vou_get_vid_abs_addr(hal_disp_layer layer, hi_ulong reg)
206 {
207 volatile hi_ulong reg_abs_addr;
208
209 switch (layer) {
210 case HAL_DISP_LAYER_VHD0: {
211 reg_abs_addr = reg + (layer - HAL_DISP_LAYER_VHD0) * VID_REGS_LEN;
212 break;
213 }
214 default: {
215 return 0;
216 }
217 }
218
219 return reg_abs_addr;
220 }
221
vou_get_gfx_abs_addr(hal_disp_layer layer,hi_ulong reg)222 hi_ulong vou_get_gfx_abs_addr(hal_disp_layer layer, hi_ulong reg)
223 {
224 volatile hi_ulong reg_abs_addr;
225
226 switch (layer) {
227 case HAL_DISP_LAYER_GFX0:
228 case HAL_DISP_LAYER_GFX1:
229 case HAL_DISP_LAYER_GFX3: {
230 reg_abs_addr = reg + (layer - HAL_DISP_LAYER_GFX0) * GRF_REGS_LEN;
231 break;
232 }
233 default: {
234 return 0;
235 }
236 }
237
238 return reg_abs_addr;
239 }
240
241 /* outstanding */
hal_sys_set_outstanding(hi_void)242 hi_void hal_sys_set_outstanding(hi_void)
243 {
244 volatile U_MAC_OUTSTANDING mac_outstanding;
245
246 mac_outstanding.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->MAC_OUTSTANDING.u32));
247 mac_outstanding.bits.mstr0_routstanding = 0xf; /* keep the default 0xf for master0 read. */
248 mac_outstanding.bits.mstr0_woutstanding = 0x4;
249
250 mac_outstanding.bits.mstr1_routstanding = 0x7; /* keep the default 0x7 for master1 read. */
251 mac_outstanding.bits.mstr1_woutstanding = 0x7;
252
253 mac_outstanding.bits.mstr2_routstanding = 0x3;
254 mac_outstanding.bits.mstr2_woutstanding = 0x3;
255 hal_write_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->MAC_OUTSTANDING.u32), mac_outstanding.u32);
256
257 return;
258 }
259
hal_disp_set_intf_enable(hal_disp_outputchannel chan,hi_bool intf)260 hi_bool hal_disp_set_intf_enable(hal_disp_outputchannel chan, hi_bool intf)
261 {
262 volatile U_DHD0_CTRL dhd0_ctrl;
263 volatile hi_ulong addr_reg;
264
265 switch (chan) {
266 case HAL_DISP_CHANNEL_DHD0:
267 case HAL_DISP_CHANNEL_DHD1: {
268 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_CTRL.u32));
269 dhd0_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
270 dhd0_ctrl.bits.intf_en = intf;
271 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, dhd0_ctrl.u32);
272
273 break;
274 }
275
276 default: {
277 return HI_FALSE;
278 }
279 }
280
281 return HI_TRUE;
282 }
283
hal_disp_get_intf_enable(hal_disp_outputchannel chan,hi_bool * intf_en)284 hi_bool hal_disp_get_intf_enable(hal_disp_outputchannel chan, hi_bool *intf_en)
285 {
286 volatile U_DHD0_CTRL dhd0_ctrl;
287 volatile hi_ulong addr_reg;
288
289 switch (chan) {
290 case HAL_DISP_CHANNEL_DHD0:
291 case HAL_DISP_CHANNEL_DHD1: {
292 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_CTRL.u32));
293 dhd0_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
294 *intf_en = dhd0_ctrl.bits.intf_en;
295 break;
296 }
297
298 default: {
299 return HI_FALSE;
300 }
301 }
302
303 return HI_TRUE;
304 }
305
hal_disp_get_int_state(hal_disp_outputchannel chan,hi_bool * bottom)306 hi_bool hal_disp_get_int_state(hal_disp_outputchannel chan, hi_bool *bottom)
307 {
308 volatile U_DHD0_STATE dhd0_state;
309 volatile hi_ulong addr_reg;
310
311 switch (chan) {
312 case HAL_DISP_CHANNEL_DHD0:
313 case HAL_DISP_CHANNEL_DHD1: {
314 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_STATE.u32));
315 dhd0_state.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
316 *bottom = dhd0_state.bits.bottom_field;
317 break;
318 }
319
320 default: {
321 return HI_FALSE;
322 }
323 }
324
325 return HI_TRUE;
326 }
327
hal_disp_get_int_state_vcnt(hal_disp_outputchannel chan,hi_u32 * vcnt)328 hi_bool hal_disp_get_int_state_vcnt(hal_disp_outputchannel chan, hi_u32 *vcnt)
329 {
330 volatile U_DHD0_STATE DHD0_STATE;
331 volatile hi_ulong addr_reg;
332
333 if (chan <= HAL_DISP_CHANNEL_DHD1) {
334 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_STATE.u32));
335 DHD0_STATE.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
336 *vcnt = DHD0_STATE.bits.vcnt;
337 } else {
338 HAL_PRINT("error channel id found in %s: L%d\n", __FUNCTION__, __LINE__);
339 return HI_FALSE;
340 }
341
342 return HI_TRUE;
343 }
344
hal_disp_set_intf_sync(hal_disp_outputchannel chan,hal_disp_syncinfo * sync_info,hal_disp_syncinv * inv)345 hi_bool hal_disp_set_intf_sync(hal_disp_outputchannel chan,
346 hal_disp_syncinfo *sync_info, hal_disp_syncinv *inv)
347 {
348 volatile U_DHD0_CTRL dhd0_ctrl;
349 volatile U_DHD0_VSYNC1 dhd0_vsync1;
350 volatile U_DHD0_VSYNC2 dhd0_vsync2;
351 volatile U_DHD0_HSYNC1 dhd0_hsync1;
352 volatile U_DHD0_HSYNC2 dhd0_hync2;
353 volatile U_DHD0_VPLUS1 dhd0_vplus1;
354 volatile U_DHD0_VPLUS2 dhd0_vplus2;
355 volatile U_DHD0_PWR dhd0_pwr;
356
357 volatile hi_ulong addr_reg;
358
359 switch (chan) {
360 case HAL_DISP_CHANNEL_DHD0:
361 case HAL_DISP_CHANNEL_DHD1: {
362 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_CTRL.u32));
363 dhd0_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
364 dhd0_ctrl.bits.iop = sync_info->iop;
365 dhd0_ctrl.bits.intf_ihs = inv->hs_inv;
366 dhd0_ctrl.bits.intf_ivs = inv->vs_inv;
367 dhd0_ctrl.bits.intf_idv = inv->dv_inv;
368 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, dhd0_ctrl.u32);
369
370 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_HSYNC1.u32));
371 dhd0_hsync1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
372 dhd0_hsync1.bits.hact = sync_info->hact - 1;
373 dhd0_hsync1.bits.hbb = (sync_info->hbb) - 1;
374 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, dhd0_hsync1.u32);
375
376 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_HSYNC2.u32));
377 dhd0_hync2.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
378 dhd0_hync2.bits.hmid = (sync_info->hmid == 0) ? 0 : sync_info->hmid - 1;
379 dhd0_hync2.bits.hfb = (sync_info->hfb) - 1;
380 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, dhd0_hync2.u32);
381
382 /* config VHD interface vertical timing */
383 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_VSYNC1.u32));
384 dhd0_vsync1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
385 dhd0_vsync1.bits.vact = sync_info->vact - 1;
386 dhd0_vsync1.bits.vbb = sync_info->vbb - 1;
387 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, dhd0_vsync1.u32);
388
389 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_VSYNC2.u32));
390 dhd0_vsync2.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
391 dhd0_vsync2.bits.vfb = sync_info->vfb - 1;
392 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, dhd0_vsync2.u32);
393
394 /* config VHD interface vertical bottom timing,no use in progressive mode */
395 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_VPLUS1.u32));
396 dhd0_vplus1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
397 dhd0_vplus1.bits.bvact = sync_info->bvact - 1;
398 dhd0_vplus1.bits.bvbb = sync_info->bvbb - 1;
399 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, dhd0_vplus1.u32);
400
401 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_VPLUS2.u32));
402 dhd0_vplus2.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
403 dhd0_vplus2.bits.bvfb = sync_info->bvfb - 1;
404 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, dhd0_vplus2.u32);
405
406 /* config VHD interface vertical bottom timing, */
407 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_PWR.u32));
408 dhd0_pwr.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
409 dhd0_pwr.bits.hpw = sync_info->hpw - 1;
410 dhd0_pwr.bits.vpw = sync_info->vpw - 1;
411 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, dhd0_pwr.u32);
412
413 break;
414 }
415
416 default: {
417 return HI_FALSE;
418 }
419 }
420
421 return HI_TRUE;
422 }
423
hal_disp_set_dev_multi_chn_en(hal_disp_outputchannel chn,hal_multichn_en multi_chn_en)424 hi_bool hal_disp_set_dev_multi_chn_en(hal_disp_outputchannel chn, hal_multichn_en multi_chn_en)
425 {
426 volatile U_DHD0_PWR dhd0_pwr;
427 volatile hi_ulong addr_reg;
428 addr_reg = vou_get_chn_abs_addr(chn, (hi_uintptr_t) & (g_vo_reg->DHD0_PWR.u32));
429 dhd0_pwr.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
430 dhd0_pwr.bits.multichn_en = multi_chn_en;
431 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, dhd0_pwr.u32);
432
433 return HI_TRUE;
434 }
435
hal_disp_set_lcd_serial_perd(hi_u32 serial_perd)436 hi_bool hal_disp_set_lcd_serial_perd(hi_u32 serial_perd)
437 {
438 U_INTF_LCD_CTRL intf_lcd_ctrl;
439 volatile hi_ulong addr_reg;
440
441 addr_reg = vou_get_intf_abs_addr(HAL_DISP_INTF_LCD_8BIT, (hi_uintptr_t) & (g_vo_reg->INTF_HDMI_CTRL.u32));
442 intf_lcd_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
443
444 intf_lcd_ctrl.bits.lcd_serial_perd = serial_perd;
445
446 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf_lcd_ctrl.u32);
447 return HI_TRUE;
448 }
449
hal_disp_set_intf_ctrl(hal_disp_intf intf,hi_u32 * ctrl_info)450 hi_bool hal_disp_set_intf_ctrl(hal_disp_intf intf, hi_u32 *ctrl_info)
451 {
452 U_INTF_HDMI_CTRL intf_hdmi_ctrl;
453 U_INTF_BT_CTRL intf_bt_ctrl;
454 U_INTF_LCD_CTRL intf_lcd_ctrl;
455 volatile hi_ulong addr_reg;
456 U_INTF_HDMI_CTRL *hdmi_ctrl = HI_NULL;
457 U_INTF_BT_CTRL *bt_ctrl = HI_NULL;
458 U_INTF_LCD_CTRL *lcd_ctrl = HI_NULL;
459
460 if ((intf == VO_INTF_BT1120) ||
461 (intf == VO_INTF_BT656)) {
462 bt_ctrl = (U_INTF_BT_CTRL *)ctrl_info;
463 addr_reg = vou_get_intf_abs_addr(intf, (hi_uintptr_t) & (g_vo_reg->INTF_HDMI_CTRL.u32));
464 intf_bt_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
465 intf_bt_ctrl.bits.hdmi_mode = bt_ctrl->bits.hdmi_mode;
466 intf_bt_ctrl.bits.lcd_serial_mode = bt_ctrl->bits.lcd_serial_mode;
467 intf_bt_ctrl.bits.lcd_parallel_order = bt_ctrl->bits.lcd_parallel_order;
468 intf_bt_ctrl.bits.lcd_data_inv = bt_ctrl->bits.lcd_data_inv;
469 intf_bt_ctrl.bits.lcd_parallel_mode = bt_ctrl->bits.lcd_parallel_mode;
470 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf_bt_ctrl.u32);
471 } else if ((intf == VO_INTF_LCD) ||
472 (intf == VO_INTF_LCD_6BIT) ||
473 (intf == VO_INTF_LCD_8BIT) ||
474 (intf == VO_INTF_LCD_16BIT) ||
475 (intf == VO_INTF_LCD_18BIT) ||
476 (intf == VO_INTF_LCD_24BIT)) {
477 lcd_ctrl = (U_INTF_LCD_CTRL *)ctrl_info;
478 addr_reg = vou_get_intf_abs_addr(intf, (hi_uintptr_t) & (g_vo_reg->INTF_HDMI_CTRL.u32));
479 intf_lcd_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
480 intf_lcd_ctrl.bits.hdmi_mode = lcd_ctrl->bits.hdmi_mode;
481 intf_lcd_ctrl.bits.lcd_serial_mode = lcd_ctrl->bits.lcd_serial_mode;
482 intf_lcd_ctrl.bits.lcd_parallel_order = lcd_ctrl->bits.lcd_parallel_order;
483 intf_lcd_ctrl.bits.lcd_data_inv = lcd_ctrl->bits.lcd_data_inv;
484 intf_lcd_ctrl.bits.lcd_parallel_mode = lcd_ctrl->bits.lcd_parallel_mode;
485 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf_lcd_ctrl.u32);
486 } else if ((intf == VO_INTF_HDMI) ||
487 (intf == VO_INTF_MIPI) ||
488 (intf == VO_INTF_MIPI_SLAVE)) {
489 hdmi_ctrl = (U_INTF_HDMI_CTRL *)ctrl_info;
490 addr_reg = vou_get_hdmi_or_mipi_intf_abs_addr(intf, (hi_uintptr_t) & (g_vo_reg->INTF_HDMI_CTRL.u32));
491 intf_hdmi_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
492 intf_hdmi_ctrl.bits.hdmi_mode = hdmi_ctrl->bits.hdmi_mode;
493 intf_hdmi_ctrl.bits.intf_420_mode = hdmi_ctrl->bits.intf_420_mode;
494 intf_hdmi_ctrl.bits.intf_420_en = hdmi_ctrl->bits.intf_420_en;
495 intf_hdmi_ctrl.bits.intf_422_en = hdmi_ctrl->bits.intf_422_en;
496 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf_hdmi_ctrl.u32);
497 } else {
498 return HI_FALSE;
499 }
500
501 return HI_TRUE;
502 }
503
hal_disp_set_intf_mux_sel(hal_disp_outputchannel chan,hal_disp_intf intf)504 hi_bool hal_disp_set_intf_mux_sel(hal_disp_outputchannel chan, hal_disp_intf intf)
505 {
506 volatile U_VO_MUX vo_mux;
507 volatile hi_ulong addr_reg;
508
509 hi_unused(chan);
510
511 addr_reg = (hi_ulong)(hi_uintptr_t) & (g_vo_reg->VO_MUX.u32);
512 vo_mux.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
513 switch (intf) {
514 case HAL_DISP_INTF_BT1120: {
515 vo_mux.bits.digital_sel = 0;
516 vo_mux.bits.bt_sel = 0;
517 break;
518 }
519
520 case HAL_DISP_INTF_BT656: {
521 vo_mux.bits.digital_sel = 1;
522 vo_mux.bits.bt_sel = 0;
523 break;
524 }
525
526 case HAL_DISP_INTF_MIPI:
527 case HAL_DISP_INTF_MIPI_SLAVE: {
528 vo_mux.bits.digital_sel = 0;
529 vo_mux.bits.mipi_sel = 0;
530 break;
531 }
532 case HAL_DISP_INTF_LCD:
533 case HAL_DISP_INTF_LCD_6BIT:
534 case HAL_DISP_INTF_LCD_8BIT:
535 case HAL_DISP_INTF_LCD_16BIT:
536 case HAL_DISP_INTF_LCD_18BIT:
537 case HAL_DISP_INTF_LCD_24BIT: {
538 vo_mux.bits.digital_sel = 2;
539 vo_mux.bits.lcd_sel = 0;
540 break;
541 }
542
543 default: {
544 vo_mux.bits.digital_sel = 15;
545 break;
546 }
547 }
548
549 hal_write_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->VO_MUX.u32), vo_mux.u32);
550
551 return HI_TRUE;
552 }
553
hal_disp_set_intf_clip(hal_disp_intf intf,hi_bool clip,hal_disp_clip * clip_data)554 hi_bool hal_disp_set_intf_clip(hal_disp_intf intf, hi_bool clip, hal_disp_clip *clip_data)
555 {
556 volatile U_BT_CLIP0_L bt_clip0_l;
557 volatile U_BT_CLIP0_H bt_clip0_h;
558 volatile hi_ulong addr_reg;
559
560 hi_unused(intf);
561
562 addr_reg = (hi_ulong)(hi_uintptr_t) & (g_vo_reg->BT_CLIP0_L.u32);
563 bt_clip0_l.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
564 bt_clip0_l.bits.clip_en = clip;
565 bt_clip0_l.bits.clip_cl2 = clip_data->clip_low_y;
566 bt_clip0_l.bits.clip_cl1 = clip_data->clip_low_cb;
567 bt_clip0_l.bits.clip_cl0 = clip_data->clip_low_cr;
568 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, bt_clip0_l.u32);
569
570 addr_reg = (hi_ulong)(hi_uintptr_t) & (g_vo_reg->BT_CLIP0_H.u32);
571 bt_clip0_h.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
572 bt_clip0_h.bits.clip_ch2 = clip_data->clip_high_y;
573 bt_clip0_h.bits.clip_ch1 = clip_data->clip_high_cb;
574 bt_clip0_h.bits.clip_ch0 = clip_data->clip_high_cr;
575 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, bt_clip0_h.u32);
576
577 return HI_TRUE;
578 }
579
hal_disp_set_vt_thd_mode(hal_disp_outputchannel chan,hi_u32 field_mode)580 hi_bool hal_disp_set_vt_thd_mode(hal_disp_outputchannel chan, hi_u32 field_mode)
581 {
582 volatile U_DHD0_VTTHD dhd0_vtthd;
583 volatile hi_ulong addr_reg;
584
585 switch (chan) {
586 case HAL_DISP_CHANNEL_DHD0: {
587 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_VTTHD.u32));
588 dhd0_vtthd.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
589 dhd0_vtthd.bits.thd1_mode = field_mode;
590 dhd0_vtthd.bits.thd2_mode = field_mode;
591 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, dhd0_vtthd.u32);
592 break;
593 }
594 default: {
595 return HI_FALSE;
596 }
597 }
598
599 return HI_TRUE;
600 }
601
hal_disp_get_vtthd_mode(hal_disp_outputchannel chan,hi_bool * field_mode)602 hi_bool hal_disp_get_vtthd_mode(hal_disp_outputchannel chan, hi_bool *field_mode)
603 {
604 volatile U_DHD0_VTTHD dhd0_vtthd;
605 volatile hi_ulong addr_reg;
606
607 switch (chan) {
608 case HAL_DISP_CHANNEL_DHD0:
609 case HAL_DISP_CHANNEL_DHD1: {
610 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_VTTHD.u32));
611 dhd0_vtthd.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
612 *field_mode = dhd0_vtthd.bits.thd1_mode;
613 break;
614 }
615 default: {
616 return HI_FALSE;
617 }
618 }
619
620 return HI_TRUE;
621 }
622
hal_disp_set_vt_thd(hal_disp_outputchannel chan,hi_u32 vtthd,hi_u32 vtthd2)623 hi_bool hal_disp_set_vt_thd(hal_disp_outputchannel chan, hi_u32 vtthd, hi_u32 vtthd2)
624 {
625 volatile U_DHD0_VTTHD dhd0_vtthd;
626 volatile hi_ulong addr_reg;
627
628 switch (chan) {
629 case HAL_DISP_CHANNEL_DHD0: {
630 /* for vtmgthd1 and vtmgthd2 */
631 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_VTTHD.u32));
632 dhd0_vtthd.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
633 dhd0_vtthd.bits.vtmgthd1 = vtthd;
634 dhd0_vtthd.bits.vtmgthd2 = dhd0_vtthd.bits.vtmgthd1 - 1;
635 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, dhd0_vtthd.u32);
636 break;
637 }
638
639 default: {
640 return HI_FALSE;
641 }
642 }
643
644 return HI_TRUE;
645 }
hal_disp_set_int_mask(hi_u32 mask_en)646 hi_bool hal_disp_set_int_mask(hi_u32 mask_en)
647 {
648 volatile U_VOINTMSK vo_intmsk;
649 /* display interrupt mask enable */
650 vo_intmsk.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->VOINTMSK.u32));
651 vo_intmsk.u32 = vo_intmsk.u32 | mask_en;
652 hal_write_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->VOINTMSK.u32), vo_intmsk.u32);
653
654 return HI_TRUE;
655 }
656
hal_disp_clr_int_mask(hi_u32 mask_en)657 hi_bool hal_disp_clr_int_mask(hi_u32 mask_en)
658 {
659 volatile U_VOINTMSK vo_intmsk;
660
661 /* display interrupt mask enable */
662 vo_intmsk.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->VOINTMSK.u32));
663 vo_intmsk.u32 = vo_intmsk.u32 & (~mask_en);
664 hal_write_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->VOINTMSK.u32), vo_intmsk.u32);
665
666 return HI_TRUE;
667 }
668
hal_disp_set_int_mask1(hi_u32 mask_en)669 hi_bool hal_disp_set_int_mask1(hi_u32 mask_en)
670 {
671 volatile U_VOINTMSK1 vo_intmsk1;
672 /* display interrupt mask enable */
673 vo_intmsk1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->VOINTMSK1.u32));
674 vo_intmsk1.u32 = vo_intmsk1.u32 | mask_en;
675
676 hal_write_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->VOINTMSK1.u32), vo_intmsk1.u32);
677 vo_intmsk1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->VOINTMSK1.u32));
678
679 return HI_TRUE;
680 }
681
hal_disp_clr_int_mask1(hi_u32 mask_en)682 hi_bool hal_disp_clr_int_mask1(hi_u32 mask_en)
683 {
684 volatile U_VOINTMSK1 vo_intmsk1;
685
686 /* display interrupt mask enable */
687 vo_intmsk1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->VOINTMSK1.u32));
688 vo_intmsk1.u32 = vo_intmsk1.u32 & (~mask_en);
689 hal_write_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->VOINTMSK1.u32), vo_intmsk1.u32);
690
691 return HI_TRUE;
692 }
693
hal_disp_get_int_status(hi_u32 int_msk)694 hi_u32 hal_disp_get_int_status(hi_u32 int_msk)
695 {
696 volatile U_VOMSKINTSTA vo_msk_int_sta;
697
698 /* read interrupt status */
699 vo_msk_int_sta.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->VOMSKINTSTA.u32));
700
701 return (vo_msk_int_sta.u32 & int_msk);
702 }
703
hal_disp_get_ori_int_status(hi_u32 int_status)704 hi_u32 hal_disp_get_ori_int_status(hi_u32 int_status)
705 {
706 volatile U_VOINTSTA vo_int_sta;
707
708 /* read original interrupt status */
709 vo_int_sta.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->VOINTSTA.u32));
710
711 return (vo_int_sta.u32 & int_status);
712 }
713
hal_disp_clear_int_status(hi_u32 int_msk)714 hi_bool hal_disp_clear_int_status(hi_u32 int_msk)
715 {
716 /* read interrupt status */
717 hal_write_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->VOMSKINTSTA.u32), int_msk);
718 return HI_TRUE;
719 }
720
hal_intf_bt_set_dfir_en(hi_u32 dfir_en)721 hi_bool hal_intf_bt_set_dfir_en(hi_u32 dfir_en)
722 {
723 U_INTF_BT_CTRL intf_bt_ctrl;
724
725 intf_bt_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->INTF_BT_CTRL.u32));
726 intf_bt_ctrl.bits.dfir_en = dfir_en;
727 hal_write_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->INTF_BT_CTRL.u32), intf_bt_ctrl.u32);
728
729 return HI_TRUE;
730 }
731
hal_disp_set_reg_up(hal_disp_outputchannel chan)732 hi_void hal_disp_set_reg_up(hal_disp_outputchannel chan)
733 {
734 volatile U_DHD0_CTRL dhd0_ctrl;
735 volatile hi_ulong addr_reg;
736
737 if (chan > HAL_DISP_CHANNEL_DHD1) {
738 HI_PRINT("error,hal_disp_set_reg_up select wrong CHANNEL ID\n");
739 return;
740 }
741
742 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_CTRL.u32));
743 dhd0_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
744 dhd0_ctrl.bits.regup = 0x1;
745 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, dhd0_ctrl.u32);
746 return;
747 }
748
hal_disp_get_reg_up(hal_disp_outputchannel chan)749 hi_u32 hal_disp_get_reg_up(hal_disp_outputchannel chan)
750 {
751 hi_u32 data;
752 volatile U_DHD0_CTRL dhd0_ctrl;
753 volatile hi_ulong addr_reg;
754
755 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->DHD0_CTRL.u32));
756 dhd0_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
757 data = dhd0_ctrl.bits.regup;
758 return data & 0x1;
759 }
760
hal_disp_set_dither_round_unlim(hal_disp_outputchannel chan,hi_u32 dither_round_unlim)761 hi_bool hal_disp_set_dither_round_unlim(hal_disp_outputchannel chan, hi_u32 dither_round_unlim)
762 {
763 volatile U_INTF0_DITHER_CTRL intf0_dither_ctrl;
764 volatile hi_ulong addr_reg;
765
766 switch (chan) {
767 case HAL_DISP_CHANNEL_DHD0:
768 case HAL_DISP_CHANNEL_DHD1: {
769 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_CTRL.u32));
770 intf0_dither_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
771 intf0_dither_ctrl.bits.dither_round_unlim = dither_round_unlim;
772 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_ctrl.u32);
773 break;
774 }
775
776 default: {
777 return HI_FALSE;
778 }
779 }
780
781 return HI_TRUE;
782 }
783
hal_disp_set_dither_data_in_out(hal_disp_outputchannel chan,hi_u32 i_data_width_dither,hi_u32 o_data_width_dither)784 hi_bool hal_disp_set_dither_data_in_out(hal_disp_outputchannel chan, hi_u32 i_data_width_dither,
785 hi_u32 o_data_width_dither)
786 {
787 volatile U_INTF0_DITHER_CTRL intf0_dither_ctrl;
788 volatile hi_ulong addr_reg;
789
790 switch (chan) {
791 case HAL_DISP_CHANNEL_DHD0:
792 case HAL_DISP_CHANNEL_DHD1: {
793 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_CTRL.u32));
794 intf0_dither_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
795 intf0_dither_ctrl.bits.i_data_width_dither = i_data_width_dither;
796 intf0_dither_ctrl.bits.o_data_width_dither = o_data_width_dither;
797 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_ctrl.u32);
798 break;
799 }
800
801 default: {
802 return HI_FALSE;
803 }
804 }
805
806 return HI_TRUE;
807 }
808
hal_disp_set_dither_en(hal_disp_outputchannel chan,hi_u32 dither_en)809 hi_bool hal_disp_set_dither_en(hal_disp_outputchannel chan, hi_u32 dither_en)
810 {
811 volatile U_INTF0_DITHER_CTRL intf0_dither_ctrl;
812 volatile hi_ulong addr_reg;
813
814 switch (chan) {
815 case HAL_DISP_CHANNEL_DHD0:
816 case HAL_DISP_CHANNEL_DHD1: {
817 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_CTRL.u32));
818 intf0_dither_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
819 intf0_dither_ctrl.bits.dither_en = dither_en;
820 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_ctrl.u32);
821 break;
822 }
823
824 default: {
825 return HI_FALSE;
826 }
827 }
828
829 return HI_TRUE;
830 }
831
hal_disp_set_dither_mode(hal_disp_outputchannel chan,hi_u32 mode)832 hi_bool hal_disp_set_dither_mode(hal_disp_outputchannel chan, hi_u32 mode)
833 {
834 volatile U_INTF0_DITHER_CTRL intf0_dither_ctrl;
835 volatile hi_ulong addr_reg;
836
837 switch (chan) {
838 case HAL_DISP_CHANNEL_DHD0:
839 case HAL_DISP_CHANNEL_DHD1: {
840 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_CTRL.u32));
841 intf0_dither_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
842 intf0_dither_ctrl.bits.dither_mode = mode;
843 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_ctrl.u32);
844 break;
845 }
846
847 default: {
848 return HI_FALSE;
849 }
850 }
851
852 return HI_TRUE;
853 }
854
hal_disp_set_dither_round(hal_disp_outputchannel chan,hi_u32 dither_round)855 hi_bool hal_disp_set_dither_round(hal_disp_outputchannel chan, hi_u32 dither_round)
856 {
857 volatile U_INTF0_DITHER_CTRL intf0_dither_ctrl;
858 volatile hi_ulong addr_reg;
859
860 switch (chan) {
861 case HAL_DISP_CHANNEL_DHD0:
862 case HAL_DISP_CHANNEL_DHD1: {
863 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_CTRL.u32));
864 intf0_dither_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
865 intf0_dither_ctrl.bits.dither_round = dither_round;
866 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_ctrl.u32);
867 break;
868 }
869
870 default: {
871 return HI_FALSE;
872 }
873 }
874
875 return HI_TRUE;
876 }
877
hal_disp_set_dither_domain_mode(hal_disp_outputchannel chan,hi_u32 domain_mode)878 hi_bool hal_disp_set_dither_domain_mode(hal_disp_outputchannel chan, hi_u32 domain_mode)
879 {
880 volatile U_INTF0_DITHER_CTRL intf0_dither_ctrl;
881 volatile hi_ulong addr_reg;
882
883 switch (chan) {
884 case HAL_DISP_CHANNEL_DHD0:
885 case HAL_DISP_CHANNEL_DHD1: {
886 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_CTRL.u32));
887 intf0_dither_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
888 intf0_dither_ctrl.bits.dither_domain_mode = domain_mode;
889 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_ctrl.u32);
890 break;
891 }
892
893 default: {
894 return HI_FALSE;
895 }
896 }
897
898 return HI_TRUE;
899 }
900
hal_disp_set_dither_tap_mode(hal_disp_outputchannel chan,hi_u32 tap_mode)901 hi_bool hal_disp_set_dither_tap_mode(hal_disp_outputchannel chan, hi_u32 tap_mode)
902 {
903 volatile U_INTF0_DITHER_CTRL intf0_dither_ctrl;
904 volatile hi_ulong addr_reg;
905
906 switch (chan) {
907 case HAL_DISP_CHANNEL_DHD0:
908 case HAL_DISP_CHANNEL_DHD1: {
909 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_CTRL.u32));
910 intf0_dither_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
911 intf0_dither_ctrl.bits.dither_tap_mode = tap_mode;
912 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_ctrl.u32);
913 break;
914 }
915
916 default: {
917 return HI_FALSE;
918 }
919 }
920
921 return HI_TRUE;
922 }
923
hal_disp_set_dither_sed(hal_disp_outputchannel chan,hal_disp_dihter_sed * dither_sed)924 hi_bool hal_disp_set_dither_sed(hal_disp_outputchannel chan, hal_disp_dihter_sed *dither_sed)
925 {
926 volatile U_INTF0_DITHER_SED_Y0 intf0_dither_sed_y0;
927 volatile U_INTF0_DITHER_SED_U0 intf0_dither_sed_u0;
928 volatile U_INTF0_DITHER_SED_V0 intf0_dither_sed_v0;
929 volatile U_INTF0_DITHER_SED_W0 intf0_dither_sed_w0;
930
931 volatile U_INTF0_DITHER_SED_Y1 intf0_dither_sed_y1;
932 volatile U_INTF0_DITHER_SED_U1 intf0_dither_sed_u1;
933 volatile U_INTF0_DITHER_SED_V1 intf0_dither_sed_v1;
934 volatile U_INTF0_DITHER_SED_W1 intf0_dither_sed_w1;
935
936 volatile U_INTF0_DITHER_SED_Y2 intf0_dither_sed_y2;
937 volatile U_INTF0_DITHER_SED_U2 intf0_dither_sed_u2;
938 volatile U_INTF0_DITHER_SED_V2 intf0_dither_sed_v2;
939 volatile U_INTF0_DITHER_SED_W2 intf0_dither_sed_w2;
940
941 volatile U_INTF0_DITHER_SED_Y3 intf0_dither_sed_y3;
942 volatile U_INTF0_DITHER_SED_U3 intf0_dither_sed_u3;
943 volatile U_INTF0_DITHER_SED_V3 intf0_dither_sed_v3;
944 volatile U_INTF0_DITHER_SED_W3 intf0_dither_sed_w3;
945 volatile hi_ulong addr_reg;
946
947 switch (chan) {
948 case HAL_DISP_CHANNEL_DHD0:
949 case HAL_DISP_CHANNEL_DHD1: {
950 /* set sed_y0,sed_u0,sed_v0,sed_w0 */
951 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_Y0.u32));
952 intf0_dither_sed_y0.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
953 intf0_dither_sed_y0.bits.dither_sed_y0 = dither_sed->dither_sed_y0;
954 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_y0.u32);
955
956 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_U0.u32));
957 intf0_dither_sed_u0.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
958 intf0_dither_sed_u0.bits.dither_sed_u0 = dither_sed->dither_sed_u0;
959 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_u0.u32);
960
961 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_V0.u32));
962 intf0_dither_sed_v0.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
963 intf0_dither_sed_v0.bits.dither_sed_v0 = dither_sed->dither_sed_v0;
964 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_v0.u32);
965
966 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_W0.u32));
967 intf0_dither_sed_w0.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
968 intf0_dither_sed_w0.bits.dither_sed_w0 = dither_sed->dither_sed_w0;
969 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_w0.u32);
970
971 /* set sed_y1,sed_u1,sed_v1,sed_w1 */
972 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_Y1.u32));
973 intf0_dither_sed_y1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
974 intf0_dither_sed_y1.bits.dither_sed_y1 = dither_sed->dither_sed_y1;
975 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_y1.u32);
976
977 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_U1.u32));
978 intf0_dither_sed_u1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
979 intf0_dither_sed_u1.bits.dither_sed_u1 = dither_sed->dither_sed_u1;
980 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_u1.u32);
981
982 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_V1.u32));
983 intf0_dither_sed_v1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
984 intf0_dither_sed_v1.bits.dither_sed_v1 = dither_sed->dither_sed_v1;
985 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_v1.u32);
986
987 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_W1.u32));
988 intf0_dither_sed_w1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
989 intf0_dither_sed_w1.bits.dither_sed_w1 = dither_sed->dither_sed_w1;
990 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_w1.u32);
991
992 /* set sed_y2,sed_u2,sed_v2,sed_w2 */
993 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_Y2.u32));
994 intf0_dither_sed_y2.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
995 intf0_dither_sed_y2.bits.dither_sed_y2 = dither_sed->dither_sed_y2;
996 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_y2.u32);
997
998 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_U2.u32));
999 intf0_dither_sed_u2.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1000 intf0_dither_sed_u2.bits.dither_sed_u2 = dither_sed->dither_sed_u2;
1001 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_u2.u32);
1002
1003 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_V2.u32));
1004 intf0_dither_sed_v2.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1005 intf0_dither_sed_v2.bits.dither_sed_v2 = dither_sed->dither_sed_v2;
1006 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_v2.u32);
1007
1008 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_W2.u32));
1009 intf0_dither_sed_w2.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1010 intf0_dither_sed_w2.bits.dither_sed_w2 = dither_sed->dither_sed_w2;
1011 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_w2.u32);
1012
1013 /* set sed_y3,sed_u3,sed_v3,sed_w3 */
1014 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_Y3.u32));
1015 intf0_dither_sed_y3.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1016 intf0_dither_sed_y3.bits.dither_sed_y3 = dither_sed->dither_sed_y3;
1017 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_y3.u32);
1018
1019 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_U3.u32));
1020 intf0_dither_sed_u3.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1021 intf0_dither_sed_u3.bits.dither_sed_u3 = dither_sed->dither_sed_u3;
1022 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_u3.u32);
1023
1024 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_V3.u32));
1025 intf0_dither_sed_v3.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1026 intf0_dither_sed_v3.bits.dither_sed_v3 = dither_sed->dither_sed_v3;
1027 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_v3.u32);
1028
1029 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_SED_W3.u32));
1030 intf0_dither_sed_w3.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1031 intf0_dither_sed_w3.bits.dither_sed_w3 = dither_sed->dither_sed_w3;
1032 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_sed_w3.u32);
1033
1034 break;
1035 }
1036
1037 default: {
1038 return HI_FALSE;
1039 }
1040 }
1041
1042 return HI_TRUE;
1043 }
1044
hal_disp_set_dither_thr_min_max(hal_disp_outputchannel chan,hi_u32 thr_min,hi_u32 thr_max)1045 hi_bool hal_disp_set_dither_thr_min_max(hal_disp_outputchannel chan, hi_u32 thr_min, hi_u32 thr_max)
1046 {
1047 volatile U_INTF0_DITHER_THR intf0_dither_thr;
1048 volatile hi_ulong addr_reg;
1049
1050 switch (chan) {
1051 case HAL_DISP_CHANNEL_DHD0:
1052 case HAL_DISP_CHANNEL_DHD1: {
1053 addr_reg = vou_get_chn_abs_addr(chan, (hi_uintptr_t) & (g_vo_reg->INTF0_DITHER_THR.u32));
1054 intf0_dither_thr.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1055 intf0_dither_thr.bits.dither_thr_min = thr_min;
1056 intf0_dither_thr.bits.dither_thr_max = thr_max;
1057 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, intf0_dither_thr.u32);
1058 break;
1059 }
1060
1061 default: {
1062 return HI_FALSE;
1063 }
1064 }
1065
1066 return HI_TRUE;
1067 }
1068
hal_video_set_layer_up_mode(hal_disp_layer layer,hi_u32 up_mode)1069 hi_bool hal_video_set_layer_up_mode(hal_disp_layer layer, hi_u32 up_mode)
1070 {
1071 U_V0_CTRL v0_ctrl;
1072 volatile hi_ulong addr_reg;
1073
1074 switch (layer) {
1075 case HAL_DISP_LAYER_VHD0: {
1076 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_CTRL.u32));
1077 v0_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1078 v0_ctrl.bits.rgup_mode = up_mode;
1079 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_ctrl.u32);
1080 break;
1081 }
1082
1083 default: {
1084 return HI_FALSE;
1085 }
1086 }
1087
1088 return HI_TRUE;
1089 }
1090
1091 /* v0_alpha */
hal_video_set_layer_alpha(hal_disp_layer layer,hi_u32 arange)1092 hi_bool hal_video_set_layer_alpha(hal_disp_layer layer, hi_u32 arange)
1093 {
1094 volatile U_V0_ALPHA v0_alpha;
1095 volatile hi_ulong addr_reg;
1096
1097 switch (layer) {
1098 case HAL_DISP_LAYER_VHD0: {
1099 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_ALPHA.u32));
1100 v0_alpha.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1101 v0_alpha.bits.vbk_alpha = arange;
1102 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_alpha.u32);
1103 break;
1104 }
1105
1106 default: {
1107 return HI_FALSE;
1108 }
1109 }
1110
1111 return HI_TRUE;
1112 }
1113
hal_layer_enable_layer(hal_disp_layer layer,hi_u32 enable)1114 hi_bool hal_layer_enable_layer(hal_disp_layer layer, hi_u32 enable)
1115 {
1116 volatile U_V0_CTRL v0_ctrl;
1117 volatile U_G0_CTRL G0_CTRL;
1118 volatile hi_ulong addr_reg;
1119
1120 switch (layer) {
1121 case HAL_DISP_LAYER_VHD0: {
1122 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_CTRL.u32));
1123 v0_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1124 v0_ctrl.bits.surface_en = enable;
1125 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_ctrl.u32);
1126 break;
1127 }
1128
1129 case HAL_DISP_LAYER_GFX0: {
1130 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_CTRL.u32));
1131 G0_CTRL.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1132 G0_CTRL.bits.surface_en = enable;
1133 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, G0_CTRL.u32);
1134 break;
1135 }
1136
1137 default: {
1138 return HI_FALSE;
1139 }
1140 }
1141
1142 return HI_TRUE;
1143 }
1144
hal_layer_get_layer_enable(hal_disp_layer layer,hi_bool * enable)1145 hi_bool hal_layer_get_layer_enable(hal_disp_layer layer, hi_bool *enable)
1146 {
1147 volatile U_V0_CTRL v0_ctrl;
1148 volatile U_G0_CTRL G0_CTRL;
1149
1150 volatile hi_ulong addr_reg;
1151
1152 switch (layer) {
1153 case HAL_DISP_LAYER_VHD0: {
1154 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_CTRL.u32));
1155 v0_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1156 *enable = v0_ctrl.bits.surface_en;
1157 break;
1158 }
1159
1160 case HAL_DISP_LAYER_GFX0: {
1161 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_CTRL.u32));
1162 G0_CTRL.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1163 *enable = G0_CTRL.bits.surface_en;
1164 break;
1165 }
1166
1167 default: {
1168 return HI_FALSE;
1169 }
1170 }
1171
1172 return HI_TRUE;
1173 }
1174
hal_layer_set_layer_data_fmt(hal_disp_layer layer,hal_disp_pixel_format data_fmt)1175 hi_bool hal_layer_set_layer_data_fmt(hal_disp_layer layer,
1176 hal_disp_pixel_format data_fmt)
1177 {
1178 volatile U_VID_SRC_INFO VID_SRC_INFO;
1179 volatile U_GFX_SRC_INFO GFX_SRC_INFO;
1180 volatile hi_ulong addr_reg;
1181
1182 /* only for v0 and v1 */
1183 if (layer == HAL_DISP_LAYER_VHD0) {
1184 addr_reg = vou_get_vid_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->VID_SRC_INFO.u32));
1185 VID_SRC_INFO.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1186 VID_SRC_INFO.bits.data_type = data_fmt;
1187 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, VID_SRC_INFO.u32);
1188 } else if (layer == HAL_DISP_LAYER_GFX0) {
1189 addr_reg = vou_get_gfx_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->GFX_SRC_INFO.u32));
1190 GFX_SRC_INFO.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1191 GFX_SRC_INFO.bits.ifmt = data_fmt;
1192 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, GFX_SRC_INFO.u32);
1193 } else {
1194 return HI_FALSE;
1195 }
1196
1197 return HI_TRUE;
1198 }
1199
hal_layer_get_layer_data_fmt(hal_disp_layer layer,hi_u32 * fmt)1200 hi_bool hal_layer_get_layer_data_fmt(hal_disp_layer layer, hi_u32 *fmt)
1201 {
1202 volatile U_VID_SRC_INFO VID_SRC_INFO;
1203 volatile hi_ulong addr_reg;
1204
1205 if (layer == HAL_DISP_LAYER_VHD0) {
1206 addr_reg = vou_get_vid_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->VID_SRC_INFO.u32));
1207 VID_SRC_INFO.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1208 *fmt = VID_SRC_INFO.bits.data_type;
1209 } else {
1210 return HI_FALSE;
1211 }
1212
1213 return HI_TRUE;
1214 }
1215
hal_video_cvfir_set_coef(hal_disp_layer layer,cvfir_coef * coef)1216 hi_void hal_video_cvfir_set_coef(hal_disp_layer layer, cvfir_coef *coef)
1217 {
1218 U_V0_CVFIR_VCOEF0 v0_cvfir_vcoef0;
1219 U_V0_CVFIR_VCOEF1 v0_cvfir_vcoef1;
1220 U_V0_CVFIR_VCOEF2 v0_cvfir_vcoef2;
1221 volatile hi_ulong addr_reg;
1222
1223 if (layer >= LAYER_VHD_START && layer <= LAYER_VHD_END) {
1224 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_CVFIR_VCOEF0.u32));
1225 v0_cvfir_vcoef0.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1226 v0_cvfir_vcoef0.bits.vccoef00 = coef->vccoef00;
1227 v0_cvfir_vcoef0.bits.vccoef01 = coef->vccoef01;
1228 v0_cvfir_vcoef0.bits.vccoef02 = coef->vccoef02;
1229 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_cvfir_vcoef0.u32);
1230
1231 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_CVFIR_VCOEF1.u32));
1232 v0_cvfir_vcoef1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1233 v0_cvfir_vcoef1.bits.vccoef03 = coef->vccoef03;
1234 v0_cvfir_vcoef1.bits.vccoef10 = coef->vccoef10;
1235 v0_cvfir_vcoef1.bits.vccoef11 = coef->vccoef11;
1236 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_cvfir_vcoef1.u32);
1237
1238 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_CVFIR_VCOEF2.u32));
1239 v0_cvfir_vcoef2.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1240 v0_cvfir_vcoef2.bits.vccoef12 = coef->vccoef12;
1241 v0_cvfir_vcoef2.bits.vccoef13 = coef->vccoef13;
1242 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_cvfir_vcoef2.u32);
1243 }
1244
1245 return;
1246 }
1247
hal_video_hfir_set_ck_gt_en(hal_disp_layer layer,hi_u32 ck_gt_en)1248 hi_void hal_video_hfir_set_ck_gt_en(hal_disp_layer layer, hi_u32 ck_gt_en)
1249 {
1250 U_V0_HFIR_CTRL v0_hfir_ctrl;
1251 volatile hi_ulong addr_reg;
1252
1253 hi_unused(ck_gt_en);
1254
1255 if (layer >= LAYER_VHD_START && layer <= LAYER_VHD_END) {
1256 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HFIR_CTRL.u32));
1257 v0_hfir_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1258 v0_hfir_ctrl.bits.ck_gt_en = 1;
1259 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_hfir_ctrl.u32);
1260 }
1261
1262 return;
1263 }
1264
hal_video_hfir_set_mid_en(hal_disp_layer layer,hi_u32 mid_en)1265 hi_void hal_video_hfir_set_mid_en(hal_disp_layer layer, hi_u32 mid_en)
1266 {
1267 U_V0_HFIR_CTRL v0_hfir_ctrl;
1268 volatile hi_ulong addr_reg;
1269
1270 if (layer >= LAYER_VHD_START && layer <= LAYER_VHD_END) {
1271 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HFIR_CTRL.u32));
1272 v0_hfir_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1273 v0_hfir_ctrl.bits.mid_en = mid_en;
1274 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_hfir_ctrl.u32);
1275 }
1276
1277 return;
1278 }
1279
hal_video_hfir_set_hfir_mode(hal_disp_layer layer,hi_u32 hfir_mode)1280 hi_void hal_video_hfir_set_hfir_mode(hal_disp_layer layer, hi_u32 hfir_mode)
1281 {
1282 U_V0_HFIR_CTRL v0_hfir_ctrl;
1283 volatile hi_ulong addr_reg;
1284
1285 if (layer >= LAYER_VHD_START && layer <= LAYER_VHD_END) {
1286 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HFIR_CTRL.u32));
1287 v0_hfir_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1288 v0_hfir_ctrl.bits.hfir_mode = hfir_mode;
1289 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_hfir_ctrl.u32);
1290 }
1291
1292 return;
1293 }
1294
hal_video_hfir_set_coef(hal_disp_layer layer,hfir_coef * coef)1295 hi_void hal_video_hfir_set_coef(hal_disp_layer layer, hfir_coef *coef)
1296 {
1297 U_V0_HFIRCOEF01 v0_hfir_coef01;
1298 U_V0_HFIRCOEF23 v0_hfir_coef23;
1299 U_V0_HFIRCOEF45 v0_hfir_coef45;
1300 U_V0_HFIRCOEF67 v0_hfir_coef67;
1301 volatile hi_ulong addr_reg;
1302
1303 if (layer >= LAYER_VHD_START && layer <= LAYER_VHD_END) {
1304 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HFIRCOEF01.u32));
1305 v0_hfir_coef01.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1306 v0_hfir_coef01.bits.coef0 = coef->coef0;
1307 v0_hfir_coef01.bits.coef1 = coef->coef1;
1308 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_hfir_coef01.u32);
1309
1310 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HFIRCOEF23.u32));
1311 v0_hfir_coef23.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1312 v0_hfir_coef23.bits.coef2 = coef->coef2;
1313 v0_hfir_coef23.bits.coef3 = coef->coef3;
1314 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_hfir_coef23.u32);
1315
1316 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HFIRCOEF45.u32));
1317 v0_hfir_coef45.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1318 v0_hfir_coef45.bits.coef4 = coef->coef4;
1319 v0_hfir_coef45.bits.coef5 = coef->coef5;
1320 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_hfir_coef45.u32);
1321
1322 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HFIRCOEF67.u32));
1323 v0_hfir_coef67.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1324 v0_hfir_coef67.bits.coef6 = coef->coef6;
1325 v0_hfir_coef67.bits.coef7 = coef->coef7;
1326 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_hfir_coef67.u32);
1327 }
1328
1329 return;
1330 }
1331
hal_layer_csc_set_enable(hal_disp_layer layer,hi_bool csc_en)1332 hi_void hal_layer_csc_set_enable(hal_disp_layer layer, hi_bool csc_en)
1333 {
1334 U_V0_HIPP_CSC_CTRL v0_hipp_csc_ctrl;
1335
1336 volatile hi_ulong addr_reg;
1337
1338 if (layer >= LAYER_VHD_START && layer <= LAYER_VHD_END) {
1339 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_CTRL.u32));
1340 v0_hipp_csc_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1341 v0_hipp_csc_ctrl.bits.hipp_csc_en = csc_en;
1342 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_hipp_csc_ctrl.u32);
1343 } else if (layer >= HAL_DISP_LAYER_GFX0 && layer <= HAL_DISP_LAYER_GFX1) {
1344 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_CTRL.u32));
1345 v0_hipp_csc_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1346 v0_hipp_csc_ctrl.bits.hipp_csc_en = csc_en;
1347 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_hipp_csc_ctrl.u32);
1348 }
1349 }
1350
hal_layer_csc_set_ck_gt_en(hal_disp_layer layer,hi_bool ck_gt_en)1351 hi_void hal_layer_csc_set_ck_gt_en(hal_disp_layer layer, hi_bool ck_gt_en)
1352 {
1353 U_V0_HIPP_CSC_CTRL v0_hipp_csc_ctrl;
1354
1355 volatile hi_ulong addr_reg;
1356
1357 if (layer >= LAYER_VHD_START && layer <= LAYER_VHD_END) {
1358 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_CTRL.u32));
1359 v0_hipp_csc_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1360 v0_hipp_csc_ctrl.bits.hipp_csc_ck_gt_en = ck_gt_en;
1361 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_hipp_csc_ctrl.u32);
1362 } else if (layer >= HAL_DISP_LAYER_GFX0 && layer <= HAL_DISP_LAYER_GFX1) {
1363 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_CTRL.u32));
1364 v0_hipp_csc_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1365 v0_hipp_csc_ctrl.bits.hipp_csc_ck_gt_en = ck_gt_en;
1366 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_hipp_csc_ctrl.u32);
1367 }
1368 }
1369
hal_layer_csc_set_coef(hal_disp_layer layer,vdp_csc_coef * coef)1370 hi_void hal_layer_csc_set_coef(hal_disp_layer layer, vdp_csc_coef *coef)
1371 {
1372 U_V0_HIPP_CSC_COEF00 V0_HIPP_CSC_COEF00;
1373 U_V0_HIPP_CSC_COEF01 V0_HIPP_CSC_COEF01;
1374 U_V0_HIPP_CSC_COEF02 V0_HIPP_CSC_COEF02;
1375 U_V0_HIPP_CSC_COEF10 V0_HIPP_CSC_COEF10;
1376 U_V0_HIPP_CSC_COEF11 V0_HIPP_CSC_COEF11;
1377 U_V0_HIPP_CSC_COEF12 V0_HIPP_CSC_COEF12;
1378 U_V0_HIPP_CSC_COEF20 V0_HIPP_CSC_COEF20;
1379 U_V0_HIPP_CSC_COEF21 V0_HIPP_CSC_COEF21;
1380 U_V0_HIPP_CSC_COEF22 V0_HIPP_CSC_COEF22;
1381
1382 volatile hi_ulong addr_reg;
1383
1384 if (layer >= LAYER_VHD_START && layer <= LAYER_VHD_END) {
1385 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_COEF00.u32));
1386 V0_HIPP_CSC_COEF00.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1387 V0_HIPP_CSC_COEF00.bits.hipp_csc_coef00 = coef->csc_coef00;
1388 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF00.u32);
1389
1390 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_COEF01.u32));
1391 V0_HIPP_CSC_COEF01.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1392 V0_HIPP_CSC_COEF01.bits.hipp_csc_coef01 = coef->csc_coef01;
1393 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF01.u32);
1394
1395 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_COEF02.u32));
1396 V0_HIPP_CSC_COEF02.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1397 V0_HIPP_CSC_COEF02.bits.hipp_csc_coef02 = coef->csc_coef02;
1398 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF02.u32);
1399
1400 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_COEF10.u32));
1401 V0_HIPP_CSC_COEF10.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1402 V0_HIPP_CSC_COEF10.bits.hipp_csc_coef10 = coef->csc_coef10;
1403 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF10.u32);
1404
1405 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_COEF11.u32));
1406 V0_HIPP_CSC_COEF11.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1407 V0_HIPP_CSC_COEF11.bits.hipp_csc_coef11 = coef->csc_coef11;
1408 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF11.u32);
1409
1410 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_COEF12.u32));
1411 V0_HIPP_CSC_COEF12.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1412 V0_HIPP_CSC_COEF12.bits.hipp_csc_coef12 = coef->csc_coef12;
1413 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF12.u32);
1414
1415 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_COEF20.u32));
1416 V0_HIPP_CSC_COEF20.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1417 V0_HIPP_CSC_COEF20.bits.hipp_csc_coef20 = coef->csc_coef20;
1418 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF20.u32);
1419
1420 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_COEF21.u32));
1421 V0_HIPP_CSC_COEF21.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1422 V0_HIPP_CSC_COEF21.bits.hipp_csc_coef21 = coef->csc_coef21;
1423 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF21.u32);
1424
1425 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_COEF22.u32));
1426 V0_HIPP_CSC_COEF22.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1427 V0_HIPP_CSC_COEF22.bits.hipp_csc_coef22 = coef->csc_coef22;
1428 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF22.u32);
1429 } else if (layer >= HAL_DISP_LAYER_GFX0 && layer <= HAL_DISP_LAYER_GFX1) {
1430 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_COEF00.u32));
1431 V0_HIPP_CSC_COEF00.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1432 V0_HIPP_CSC_COEF00.bits.hipp_csc_coef00 = coef->csc_coef00;
1433 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF00.u32);
1434
1435 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_COEF01.u32));
1436 V0_HIPP_CSC_COEF01.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1437 V0_HIPP_CSC_COEF01.bits.hipp_csc_coef01 = coef->csc_coef01;
1438 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF01.u32);
1439
1440 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_COEF02.u32));
1441 V0_HIPP_CSC_COEF02.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1442 V0_HIPP_CSC_COEF02.bits.hipp_csc_coef02 = coef->csc_coef02;
1443 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF02.u32);
1444
1445 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_COEF10.u32));
1446 V0_HIPP_CSC_COEF10.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1447 V0_HIPP_CSC_COEF10.bits.hipp_csc_coef10 = coef->csc_coef10;
1448 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF10.u32);
1449
1450 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_COEF11.u32));
1451 V0_HIPP_CSC_COEF11.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1452 V0_HIPP_CSC_COEF11.bits.hipp_csc_coef11 = coef->csc_coef11;
1453 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF11.u32);
1454
1455 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_COEF12.u32));
1456 V0_HIPP_CSC_COEF12.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1457 V0_HIPP_CSC_COEF12.bits.hipp_csc_coef12 = coef->csc_coef12;
1458 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF12.u32);
1459
1460 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_COEF20.u32));
1461 V0_HIPP_CSC_COEF20.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1462 V0_HIPP_CSC_COEF20.bits.hipp_csc_coef20 = coef->csc_coef20;
1463 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF20.u32);
1464
1465 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_COEF21.u32));
1466 V0_HIPP_CSC_COEF21.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1467 V0_HIPP_CSC_COEF21.bits.hipp_csc_coef21 = coef->csc_coef21;
1468 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF21.u32);
1469
1470 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_COEF22.u32));
1471 V0_HIPP_CSC_COEF22.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1472 V0_HIPP_CSC_COEF22.bits.hipp_csc_coef22 = coef->csc_coef22;
1473 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_COEF22.u32);
1474 } else {
1475 }
1476
1477 return;
1478 }
1479
hal_layer_csc_set_dc_coef(hal_disp_layer layer,vdp_csc_dc_coef * csc_dc_coef)1480 hi_void hal_layer_csc_set_dc_coef(hal_disp_layer layer, vdp_csc_dc_coef *csc_dc_coef)
1481 {
1482 U_V0_HIPP_CSC_IDC0 V0_HIPP_CSC_IDC0;
1483 U_V0_HIPP_CSC_IDC1 V0_HIPP_CSC_IDC1;
1484 U_V0_HIPP_CSC_IDC2 V0_HIPP_CSC_IDC2;
1485 U_V0_HIPP_CSC_ODC0 V0_HIPP_CSC_ODC0;
1486 U_V0_HIPP_CSC_ODC1 V0_HIPP_CSC_ODC1;
1487 U_V0_HIPP_CSC_ODC2 V0_HIPP_CSC_ODC2;
1488
1489 volatile hi_ulong addr_reg;
1490
1491 if (layer >= LAYER_VHD_START && layer <= LAYER_VHD_END) {
1492 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_IDC0.u32));
1493 V0_HIPP_CSC_IDC0.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1494 V0_HIPP_CSC_IDC0.bits.hipp_csc_idc0 = csc_dc_coef->csc_in_dc0;
1495 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_IDC0.u32);
1496
1497 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_IDC1.u32));
1498 V0_HIPP_CSC_IDC1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1499 V0_HIPP_CSC_IDC1.bits.hipp_csc_idc1 = csc_dc_coef->csc_in_dc1;
1500 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_IDC1.u32);
1501
1502 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_IDC2.u32));
1503 V0_HIPP_CSC_IDC2.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1504 V0_HIPP_CSC_IDC2.bits.hipp_csc_idc2 = csc_dc_coef->csc_in_dc2;
1505 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_IDC2.u32);
1506
1507 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_ODC0.u32));
1508 V0_HIPP_CSC_ODC0.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1509 V0_HIPP_CSC_ODC0.bits.hipp_csc_odc0 = csc_dc_coef->csc_out_dc0;
1510 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_ODC0.u32);
1511
1512 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_ODC1.u32));
1513 V0_HIPP_CSC_ODC1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1514 V0_HIPP_CSC_ODC1.bits.hipp_csc_odc1 = csc_dc_coef->csc_out_dc1;
1515 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_ODC1.u32);
1516
1517 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_ODC2.u32));
1518 V0_HIPP_CSC_ODC2.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1519 V0_HIPP_CSC_ODC2.bits.hipp_csc_odc2 = csc_dc_coef->csc_out_dc2;
1520 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_ODC2.u32);
1521 } else if (layer >= HAL_DISP_LAYER_GFX0 && layer <= HAL_DISP_LAYER_GFX1) {
1522 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_IDC0.u32));
1523 V0_HIPP_CSC_IDC0.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1524 V0_HIPP_CSC_IDC0.bits.hipp_csc_idc0 = csc_dc_coef->csc_in_dc0;
1525 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_IDC0.u32);
1526
1527 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_IDC1.u32));
1528 V0_HIPP_CSC_IDC1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1529 V0_HIPP_CSC_IDC1.bits.hipp_csc_idc1 = csc_dc_coef->csc_in_dc1;
1530 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_IDC1.u32);
1531
1532 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_IDC2.u32));
1533 V0_HIPP_CSC_IDC2.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1534 V0_HIPP_CSC_IDC2.bits.hipp_csc_idc2 = csc_dc_coef->csc_in_dc2;
1535 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_IDC2.u32);
1536
1537 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_ODC0.u32));
1538 V0_HIPP_CSC_ODC0.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1539 V0_HIPP_CSC_ODC0.bits.hipp_csc_odc0 = csc_dc_coef->csc_out_dc0;
1540 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_ODC0.u32);
1541
1542 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_ODC1.u32));
1543 V0_HIPP_CSC_ODC1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1544 V0_HIPP_CSC_ODC1.bits.hipp_csc_odc1 = csc_dc_coef->csc_out_dc1;
1545 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_ODC1.u32);
1546
1547 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_ODC2.u32));
1548 V0_HIPP_CSC_ODC2.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1549 V0_HIPP_CSC_ODC2.bits.hipp_csc_odc2 = csc_dc_coef->csc_out_dc2;
1550 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_ODC2.u32);
1551 } else {
1552 }
1553
1554 return;
1555 }
1556
hal_layer_csc_set_param(hal_disp_layer layer,csc_coef_param * csc_param)1557 hi_void hal_layer_csc_set_param(hal_disp_layer layer, csc_coef_param *csc_param)
1558 {
1559 U_V0_HIPP_CSC_SCALE V0_HIPP_CSC_SCALE;
1560 U_V0_HIPP_CSC_MIN_Y V0_HIPP_CSC_MIN_Y;
1561 U_V0_HIPP_CSC_MIN_C V0_HIPP_CSC_MIN_C;
1562 U_V0_HIPP_CSC_MAX_Y V0_HIPP_CSC_MAX_Y;
1563 U_V0_HIPP_CSC_MAX_C V0_HIPP_CSC_MAX_C;
1564
1565 volatile hi_ulong addr_reg;
1566 if (layer >= LAYER_VHD_START && layer <= LAYER_VHD_END) {
1567 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_SCALE.u32));
1568 V0_HIPP_CSC_SCALE.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1569 V0_HIPP_CSC_SCALE.bits.hipp_csc_scale = csc_param->csc_scale2p;
1570 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_SCALE.u32);
1571
1572 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_MIN_Y.u32));
1573 V0_HIPP_CSC_MIN_Y.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1574 V0_HIPP_CSC_MIN_Y.bits.hipp_csc_min_y = csc_param->csc_clip_min;
1575 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_MIN_Y.u32);
1576
1577 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_MIN_C.u32));
1578 V0_HIPP_CSC_MIN_C.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1579 V0_HIPP_CSC_MIN_C.bits.hipp_csc_min_c = csc_param->csc_clip_min;
1580 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_MIN_C.u32);
1581
1582 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_MAX_Y.u32));
1583 V0_HIPP_CSC_MAX_Y.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1584 V0_HIPP_CSC_MAX_Y.bits.hipp_csc_max_y = csc_param->csc_clip_max;
1585 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_MAX_Y.u32);
1586
1587 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_HIPP_CSC_MAX_C.u32));
1588 V0_HIPP_CSC_MAX_C.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1589 V0_HIPP_CSC_MAX_C.bits.hipp_csc_max_c = csc_param->csc_clip_max;
1590 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_MAX_C.u32);
1591 } else if (layer >= HAL_DISP_LAYER_GFX0 && layer <= HAL_DISP_LAYER_GFX1) {
1592 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_SCALE.u32));
1593 V0_HIPP_CSC_SCALE.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1594 V0_HIPP_CSC_SCALE.bits.hipp_csc_scale = csc_param->csc_scale2p;
1595 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_SCALE.u32);
1596
1597 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_MIN_Y.u32));
1598 V0_HIPP_CSC_MIN_Y.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1599 V0_HIPP_CSC_MIN_Y.bits.hipp_csc_min_y = csc_param->csc_clip_min;
1600 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_MIN_Y.u32);
1601
1602 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_MIN_C.u32));
1603 V0_HIPP_CSC_MIN_C.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1604 V0_HIPP_CSC_MIN_C.bits.hipp_csc_min_c = csc_param->csc_clip_min;
1605 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_MIN_C.u32);
1606
1607 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_MAX_Y.u32));
1608 V0_HIPP_CSC_MAX_Y.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1609 V0_HIPP_CSC_MAX_Y.bits.hipp_csc_max_y = csc_param->csc_clip_max;
1610 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_MAX_Y.u32);
1611
1612 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->G0_HIPP_CSC_MAX_C.u32));
1613 V0_HIPP_CSC_MAX_C.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1614 V0_HIPP_CSC_MAX_C.bits.hipp_csc_max_c = csc_param->csc_clip_max;
1615 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, V0_HIPP_CSC_MAX_C.u32);
1616 }
1617 }
1618
hal_layer_set_csc_coef(hal_disp_layer layer,csc_coef * coef)1619 hi_bool hal_layer_set_csc_coef(hal_disp_layer layer, csc_coef *coef)
1620 {
1621 if ((layer < HAL_DISP_LAYER_VHD0) || (layer > HAL_DISP_LAYER_GFX1)) {
1622 return HI_FALSE;
1623 }
1624
1625 hal_layer_csc_set_dc_coef(layer, (vdp_csc_dc_coef *)(&coef->csc_in_dc0));
1626 hal_layer_csc_set_coef(layer, (vdp_csc_coef *)(&coef->csc_coef00));
1627 hal_layer_csc_set_param(layer, (csc_coef_param *)(&coef->new_csc_scale2p));
1628
1629 return HI_TRUE;
1630 }
1631
hal_layer_set_csc_en(hal_disp_layer layer,hi_bool csc_en)1632 hi_bool hal_layer_set_csc_en(hal_disp_layer layer, hi_bool csc_en)
1633 {
1634 if ((layer < HAL_DISP_LAYER_VHD0) || (layer > HAL_DISP_LAYER_GFX1)) {
1635 return HI_FALSE;
1636 }
1637
1638 hal_layer_csc_set_ck_gt_en(layer, csc_en);
1639 hal_layer_csc_set_enable(layer, csc_en);
1640
1641 return HI_TRUE;
1642 }
1643
hal_layer_set_layer_g_alpha(hal_disp_layer layer,hi_u8 alpha0)1644 hi_bool hal_layer_set_layer_g_alpha(hal_disp_layer layer,
1645 hi_u8 alpha0)
1646 {
1647 volatile U_V0_CTRL v0_ctrl;
1648 volatile hi_ulong addr_reg;
1649
1650 switch (layer) {
1651 case HAL_DISP_LAYER_VHD0: {
1652 addr_reg = vou_get_abs_addr(layer, (hi_uintptr_t) & (g_vo_reg->V0_CTRL.u32));
1653 v0_ctrl.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)addr_reg);
1654 v0_ctrl.bits.galpha = alpha0;
1655 hal_write_reg((hi_u32 *)(hi_uintptr_t)addr_reg, v0_ctrl.u32);
1656 break;
1657 }
1658
1659 default: {
1660 return HI_FALSE;
1661 }
1662 }
1663
1664 return HI_TRUE;
1665 }
1666
hal_cbm_set_cbm_bkg(hi_u32 mixer_id,hal_disp_bkcolor * bkg)1667 hi_bool hal_cbm_set_cbm_bkg(hi_u32 mixer_id, hal_disp_bkcolor *bkg)
1668 {
1669 U_CBM_BKG1 CBM_BKG1;
1670 U_CBM_BKG2 CBM_BKG2;
1671
1672 if (mixer_id == HAL_CBMMIX1) {
1673 CBM_BKG1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->CBM_BKG1.u32));
1674 CBM_BKG1.bits.cbm_bkgy1 = (bkg->bkg_y);
1675 CBM_BKG1.bits.cbm_bkgcb1 = (bkg->bkg_cb);
1676 CBM_BKG1.bits.cbm_bkgcr1 = (bkg->bkg_cr);
1677 hal_write_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->CBM_BKG1.u32), CBM_BKG1.u32);
1678 } else if (mixer_id == HAL_CBMMIX2) {
1679 CBM_BKG2.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->CBM_BKG2.u32));
1680 CBM_BKG2.bits.cbm_bkgy2 = (bkg->bkg_y);
1681 CBM_BKG2.bits.cbm_bkgcb2 = (bkg->bkg_cb);
1682 CBM_BKG2.bits.cbm_bkgcr2 = (bkg->bkg_cr);
1683 hal_write_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->CBM_BKG2.u32), CBM_BKG2.u32);
1684 } else {
1685 return HI_FALSE;
1686 }
1687
1688 return HI_TRUE;
1689 }
1690
hal_cbm_set_cbm_mixer_prio(hal_disp_layer layer,hi_u8 prio,hi_u8 mixer_id)1691 hi_bool hal_cbm_set_cbm_mixer_prio(hal_disp_layer layer, hi_u8 prio, hi_u8 mixer_id)
1692 {
1693 U_CBM_MIX1 CBM_MIX1;
1694 hi_u8 layer_id = 0;
1695
1696 /* settings for v0 and g0 */
1697 if (mixer_id == HAL_CBMMIX1) {
1698 /* check layer availability */
1699 switch (layer) {
1700 case HAL_DISP_LAYER_VHD0: {
1701 layer_id = 0x1;
1702 break;
1703 }
1704 case HAL_DISP_LAYER_GFX0: {
1705 layer_id = 0x2;
1706 break;
1707 }
1708 case HAL_DISP_INVALID_LAYER: {
1709 layer_id = 0x0;
1710 break;
1711 }
1712 default: {
1713 return HI_FALSE;
1714 }
1715 }
1716
1717 /* set mixer prio */
1718 CBM_MIX1.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->CBM_MIX1.u32));
1719
1720 switch (prio) {
1721 case VOU_MIX_PRIO0: {
1722 CBM_MIX1.bits.mixer_prio0 = layer_id;
1723 break;
1724 }
1725
1726 case VOU_MIX_PRIO1: {
1727 CBM_MIX1.bits.mixer_prio1 = layer_id;
1728 break;
1729 }
1730
1731 case VOU_MIX_PRIO2: {
1732 CBM_MIX1.bits.mixer_prio2 = layer_id;
1733 break;
1734 }
1735
1736 case VOU_MIX_PRIO3: {
1737 CBM_MIX1.bits.mixer_prio3 = layer_id;
1738 break;
1739 }
1740
1741 default: {
1742 return HI_FALSE;
1743 }
1744 }
1745
1746 hal_write_reg((hi_u32 *)(hi_uintptr_t) & (g_vo_reg->CBM_MIX1.u32), CBM_MIX1.u32);
1747 } else {
1748 return HI_FALSE;
1749 }
1750
1751 return HI_TRUE;
1752 }
1753
hal_fdr_vid_set_vid_out_uv_order(hi_u32 layer,hi_u32 uv_order_en)1754 hi_void hal_fdr_vid_set_vid_out_uv_order(hi_u32 layer, hi_u32 uv_order_en)
1755 {
1756 U_VID_OUT_CTRL VID_OUT_CTRL;
1757
1758 VID_OUT_CTRL.u32 = hal_read_reg((hi_u32 *)(hi_uintptr_t)(&(g_vo_reg->VID_OUT_CTRL.u32) + layer * FDR_VID_OFFSET));
1759 VID_OUT_CTRL.bits.uv_order_en = uv_order_en;
1760 hal_write_reg((hi_u32 *)(hi_uintptr_t)(&(g_vo_reg->VID_OUT_CTRL.u32) + layer * FDR_VID_OFFSET), VID_OUT_CTRL.u32);
1761
1762 return;
1763 }
1764
1765 #ifdef __cplusplus
1766 #if __cplusplus
1767 }
1768 #endif
1769 #endif /* end of #ifdef __cplusplus */
1770