1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18 #include "hdmi_hal_ctrl.h"
19 #include "hdmi_reg_tx.h"
20 #include "hdmi_reg_audio_path.h"
21 #include "hdmi_reg_video_path.h"
22 #include "hdmi_reg_aon.h"
23 #include "hdmi_reg_ctrl.h"
24 #include "hdmi_hal_ncts.h"
25 #include "hdmi_hal_ddc.h"
26 #include "hdmi_hal_intf.h"
27 #include "hdmi_reg_crg.h"
28 #include "hdmi_product_define.h"
29 #include "hdmi_hal_machine.h"
30 #include "drv_hdmi_common.h"
31
32 #define CTRL_CHANNEL0_Y 0x0
33 #define CTRL_CHANNEL0_Y422 0x3
34 #define CTRL_CHANNEL1_CB 0x1
35 #define CTRL_CHANNEL1_Y422 0x4
36 #define CTRL_CHANNEL2_CR 0x2
37 #define CTRL_CHANNEL2_Y422 0x3
38 #define CTRL_COLORMETRY_OUT_MASK 0xfc
39 #define CTRL_COLORMETRY_OUT_BIT 0 /* out colormetry offset in reg_csc_mode */
40 #define CTRL_COLORMETRY_IN_MASK 0xcf
41 #define CTRL_COLORMETRY_IN_BIT 0x4 /* in colormetry offset in reg_csc_mode */
42 #define CTRL_COLORMETRY_MASK 0x3
43 #define CTRL_RGB_OUT_BIT 0x3 /* out color space offset in reg_csc_mode */
44 #define CTRL_RGB_IN_BIT 0x7 /* in color space offset in reg_csc_mode */
45 #define CTRL_QUANTIZAION_OUT_BIT 0x2 /* out quantization offset in reg_csc_mode */
46 #define CTRL_QUANTIZAION_IN_BIT 0x6 /* in quantization offset in reg_csc_mode */
47 #define CTRL_SYCN_POL_V_BIT 0 /* vsync offset in reg_inver_sync */
48 #define CTRL_SYCN_POL_H_BIT 1 /* hsync offset in reg_inver_sync */
49 #define CTRL_SYCN_POL_DE_BIT 0x3 /* DE offset in reg_inver_sync */
50 #define CTRL_BLACK_Y_CB_CR 0x000000
51 #define CTRL_BLACK_DATA_YUV_CR 0x200 /* cr val for yuv black */
52 #define CTRL_BLACK_DATA_YUV_Y 0x40 /* y val for yuv black */
53 #define CTRL_BLACK_DATA_YUV_CB 0x200 /* cb val for yuv black */
54 #define CTRL_BLACK_DATA_RGB_R 0x40 /* r val for rgb black */
55 #define CTRL_BLACK_DATA_RGB_G 0x40 /* g val for rgb black */
56 #define CTRL_BLACK_DATA_RGB_B 0x40 /* b val for rgb black */
57 #define CTRL_AUDIO_INVALID_CFG 0xff
58 #define CTRL_AUDIO_INVALID_RATE 0xffffffff
59 #define CTRL_REAET_WAIT_TIME 5
60 #define HDMI_INFOFRAME_DATA_SIZE 31
61
62 typedef struct {
63 hi_bool ver_down_samp_bypass;
64 hi_bool ver_down_samp_enable;
65 hi_bool hor_down_samp_enable;
66 hi_bool demux_y420_enable;
67 hi_bool pxl_div_enable;
68 hi_bool hor_filter_enable;
69 } hdmi_video_down_samp;
70
71 typedef enum {
72 HDMI_AUDIO_FIFO_MAP_SD0,
73 HDMI_AUDIO_FIFO_MAP_SD1,
74 HDMI_AUDIO_FIFO_MAP_SD2,
75 HDMI_AUDIO_FIFO_MAP_SD3,
76 HDMI_AUDIO_FIFO_MAP_BUTT
77 } hdmi_audio_fifo_map;
78
79 typedef enum {
80 HDMI_AUDIO_I2S_SD_NONE,
81 HDMI_AUDIO_I2S_SD_0,
82 HDMI_AUDIO_I2S_SD_2,
83 HDMI_AUDIO_I2S_SD_3 = 0x4,
84 HDMI_AUDIO_I2S_SD_4 = 0x8,
85 HDMI_AUDIO_I2S_SD_ALL = 0xf
86 } hdmi_audio_i2s_sd;
87
88 typedef enum {
89 HDMI_AUDIO_HBRA_MASK_ALL,
90 HDMI_AUDIO_HBRA_MASK_NONE = 0xf
91 } hdmi_i2s_hbra_mask;
92
93 typedef enum {
94 HDMI_AUDIO_CLK_ACCURACY_LEVEL2,
95 HDMI_AUDIO_CLK_ACCURACY_LEVEL1,
96 HDMI_AUDIO_CLK_ACCURACY_LEVEL3,
97 HDMI_AUDIO_CLK_ACCURACY_NOTMATCH
98 } hdmi_audio_clk_accuracy;
99
100 typedef struct {
101 hi_bool test;
102 hdmi_i2s_hbra_mask hbra_mask;
103 } ctrl_fifo;
104
105 typedef struct {
106 hi_bool professional_app;
107 hi_bool compress;
108 hi_u32 samp_rate;
109 hi_u32 org_rate;
110 hi_u32 out_bit_length;
111 hdmi_audio_clk_accuracy clk_accuracy;
112 hdmi_audio_fifo_map fifo_map;
113 } ctrl_i2s_status;
114
115 typedef struct {
116 hi_bool channel_lr_swap;
117 hi_u32 in_bit_length;
118 hi_bool vbit_compress;
119 hi_bool data_dir_msb_first;
120 hi_bool justify_ws_right;
121 hi_bool polarity_ws_msb_left;
122 hi_bool sck_shift_one;
123 hi_bool hbra_enable;
124 } ctrl_i2s;
125
126 typedef struct {
127 hi_u32 bit_value;
128 hi_u32 bit_reg;
129 } hdmi_audio_samp_bit;
130
131 typedef struct {
132 hi_u32 rate_value;
133 hi_u32 rate_reg;
134 hi_u32 rate_org_reg;
135 } hdmi_i2s_samp_rate;
136
137 typedef struct {
138 hi_u32 rate_value;
139 hi_u32 rate_reg;
140 } hdmi_spdif_samp_rate;
141
142 typedef struct {
143 hi_bool in_rgb;
144 hi_bool out_rgb;
145 hi_bool csc_enable;
146 hi_bool y422_enable;
147 hi_bool y420_enable;
148 hi_bool dwsm_hori_enable;
149 hi_bool dwsm_vert_enable;
150 } ctrl_colorspace_en;
151
152 static hdmi_audio_samp_bit g_samp_bit[] = {
153 /* bit reg */
154 { 16, 0x2 },
155 { 17, 0xc },
156 { 18, 0x4 },
157 { 19, 0x8 },
158 { 20, 0xa },
159 { 21, 0xd },
160 { 22, 0x5 },
161 { 23, 0x9 },
162 { 24, 0xb }
163 };
164
165 static hdmi_i2s_samp_rate g_i2s_samp_rate[] = {
166 /* sample rate value reg org_reg */
167 { HDMI_SAMPLE_RATE_32K, 0x03, 0xc },
168 { HDMI_SAMPLE_RATE_44K, 0x00, 0xf },
169 { HDMI_SAMPLE_RATE_48K, 0x02, 0xd }
170 };
171
172 static hdmi_ctrl_info g_ctrl_info[HDMI_DEVICE_ID_BUTT];
173
ctrl_info_ptr_get(hdmi_device_id hdmi)174 static hdmi_ctrl_info *ctrl_info_ptr_get(hdmi_device_id hdmi)
175 {
176 if (hdmi < HDMI_DEVICE_ID_BUTT) {
177 return &g_ctrl_info[hdmi];
178 }
179 return HI_NULL;
180 }
181
ctrl_i2s_rate_reg_get(hi_u32 rate_value)182 static hi_u32 ctrl_i2s_rate_reg_get(hi_u32 rate_value)
183 {
184 hi_u32 i = 0;
185 hi_u32 ret = 0x2; /* 48Khz */
186 hdmi_i2s_samp_rate *i2s_rate = HI_NULL;
187
188 for (i2s_rate = &g_i2s_samp_rate[0]; i2s_rate && (i < hdmi_array_size(g_i2s_samp_rate)); i2s_rate++, i++) {
189 if (i2s_rate->rate_value == rate_value) {
190 ret = i2s_rate->rate_reg;
191 break;
192 }
193 }
194
195 if (i >= hdmi_array_size(g_i2s_samp_rate)) {
196 hdmi_err("can't find aduio rate = %u, force 48k\n", rate_value);
197 }
198
199 return ret;
200 }
201
ctrl_i2s_rate_org_reg_get(hi_u32 rate_value)202 static hi_u32 ctrl_i2s_rate_org_reg_get(hi_u32 rate_value)
203 {
204 hi_u32 i = 0;
205 hi_u32 ret = 0xd; /* 48Khz */
206 hdmi_i2s_samp_rate *i2s_rate = HI_NULL;
207
208 for (i2s_rate = &g_i2s_samp_rate[0]; i2s_rate && (i < hdmi_array_size(g_i2s_samp_rate)); i2s_rate++, i++) {
209 if (i2s_rate->rate_value == rate_value) {
210 ret = i2s_rate->rate_org_reg;
211 break;
212 }
213 }
214
215 if (i >= hdmi_array_size(g_i2s_samp_rate)) {
216 hdmi_err("can't find aduio rate = %u, force 48k\n", rate_value);
217 }
218
219 return ret;
220 }
221
ctrl_i2s_rate_value_get(hi_void)222 static hi_u32 ctrl_i2s_rate_value_get(hi_void)
223 {
224 hi_u32 i = 0;
225 hi_u32 rate_reg, rate_org_reg;
226 hdmi_i2s_samp_rate *i2s_rate = HI_NULL;
227
228 rate_reg = hdmi_reg_chst_byte3_fs_get();
229 rate_org_reg = hdmi_reg_chst_byte4_org_fs_get();
230
231 for (i2s_rate = &g_i2s_samp_rate[0]; i2s_rate && (i < hdmi_array_size(g_i2s_samp_rate)); i2s_rate++, i++) {
232 if ((i2s_rate->rate_reg == rate_reg) && (i2s_rate->rate_org_reg == rate_org_reg)) {
233 return i2s_rate->rate_value;
234 }
235 }
236
237 return HDMI_SAMPLE_RATE_UNKNOWN;
238 }
239
ctrl_audio_bit_reg_get(hi_u32 bit_value)240 static hi_u32 ctrl_audio_bit_reg_get(hi_u32 bit_value)
241 {
242 hi_u32 i = 0;
243 hi_u32 ret = 0x2; /* 16bit */
244 hdmi_audio_samp_bit *audio_bit = HI_NULL;
245
246 for (audio_bit = &g_samp_bit[0]; audio_bit && (i < hdmi_array_size(g_samp_bit)); audio_bit++, i++) {
247 if (audio_bit->bit_value == bit_value) {
248 ret = audio_bit->bit_reg;
249 break;
250 }
251 }
252
253 if (i >= hdmi_array_size(g_samp_bit)) {
254 hdmi_err("can't find audio bit= %u, force 16\n", bit_value);
255 }
256
257 return ret;
258 }
259
ctrl_audio_bit_value_get(hi_bool spdif)260 static hi_u32 ctrl_audio_bit_value_get(hi_bool spdif)
261 {
262 hi_u32 i = 0;
263 hi_u32 bit_reg;
264 hdmi_audio_samp_bit *audio_bit = HI_NULL;
265
266 if (spdif) {
267 bit_reg = hdmi_reg_aud_length_get();
268 } else {
269 bit_reg = hdmi_reg_chst_byte4_length_get();
270 }
271
272 for (audio_bit = &g_samp_bit[0]; audio_bit && (i < hdmi_array_size(g_samp_bit)); audio_bit++, i++) {
273 if (audio_bit->bit_reg == bit_reg) {
274 return audio_bit->bit_value;
275 }
276 }
277
278 return HDMI_AUDIO_BIT_DEPTH_UNKNOWN;
279 }
280
ctrl_audio_mute_set(hi_bool enable)281 static hi_void ctrl_audio_mute_set(hi_bool enable)
282 {
283 hdmi_reg_aud_mute_en_set(enable);
284 return;
285 }
286
ctrl_audio_mute_get(hi_void)287 static hi_bool ctrl_audio_mute_get(hi_void)
288 {
289 if (hdmi_reg_aud_mute_en_get()) {
290 return HI_TRUE;
291 }
292 return HI_FALSE;
293 }
294
ctrl_audio_i2s_enable_set(hi_bool enable)295 static hi_void ctrl_audio_i2s_enable_set(hi_bool enable)
296 {
297 hdmi_audio_i2s_sd audio_i2s_enable;
298 audio_i2s_enable = enable ? HDMI_AUDIO_I2S_SD_ALL : HDMI_AUDIO_I2S_SD_NONE;
299 hdmi_reg_aud_i2s_en_set(audio_i2s_enable);
300 return;
301 }
302
ctrl_audio_i2s_enable_get(hi_void)303 static hi_bool ctrl_audio_i2s_enable_get(hi_void)
304 {
305 if (hdmi_reg_aud_i2s_en_get()) {
306 return HI_TRUE;
307 }
308 return HI_FALSE;
309 }
310
ctrl_audio_spdif_enable_set(hi_bool spdif_enable)311 static hi_void ctrl_audio_spdif_enable_set(hi_bool spdif_enable)
312 {
313 hdmi_reg_aud_spdif_en_set(spdif_enable);
314 return;
315 }
316
ctrl_audio_spdif_enable_get(hi_void)317 static hi_bool ctrl_audio_spdif_enable_get(hi_void)
318 {
319 if (hdmi_reg_aud_spdif_en_get()) {
320 return HI_TRUE;
321 }
322 return HI_FALSE;
323 }
324
ctrl_audio_path_enable_set(hi_bool audio_enable)325 static hi_void ctrl_audio_path_enable_set(hi_bool audio_enable)
326 {
327 hdmi_reg_aud_in_en_set(audio_enable);
328 return;
329 }
330
ctrl_audio_path_enable_get(hi_void)331 static hi_bool ctrl_audio_path_enable_get(hi_void)
332 {
333 if (hdmi_reg_aud_in_en_get()) {
334 return HI_TRUE;
335 }
336 return HI_FALSE;
337 }
338
ctrl_audio_path_n_value_set(hi_u32 audio_n)339 static hi_void ctrl_audio_path_n_value_set(hi_u32 audio_n)
340 {
341 hdmi_reg_acr_n_val_sw_set(audio_n);
342 return;
343 }
344
ctrl_audio_path_n_value_get(hi_void)345 static hi_u32 ctrl_audio_path_n_value_get(hi_void)
346 {
347 return hdmi_reg_acr_n_val_sw_get();
348 }
349
ctrl_audio_path_cts_value_set(hi_bool sw_cts)350 static hi_void ctrl_audio_path_cts_value_set(hi_bool sw_cts)
351 {
352 hdmi_reg_acr_cts_hw_sw_sel_set(sw_cts);
353 return;
354 }
355
ctrl_audio_path_cts_value_get(hi_void)356 static hi_u32 ctrl_audio_path_cts_value_get(hi_void)
357 {
358 hi_u32 cts_value;
359
360 /* wait reg valid */
361 osal_msleep(1);
362 /* sw */
363 if (hdmi_reg_acr_cts_hw_sw_sel_get()) {
364 cts_value = hdmi_reg_acr_cts_val_sw_get();
365 } else { /* hw */
366 cts_value = hdmi_reg_acr_cts_val_hw_get();
367 }
368
369 return cts_value;
370 }
371
ctrl_audio_path_layout_set(hi_bool muti_layout)372 static hi_void ctrl_audio_path_layout_set(hi_bool muti_layout)
373 {
374 hdmi_reg_aud_layout_set(muti_layout);
375 return;
376 }
377
ctrl_audio_path_layout_get(hi_void)378 static hi_u32 ctrl_audio_path_layout_get(hi_void)
379 {
380 return hdmi_reg_aud_layout_get();
381 }
382
ctrl_audio_hbra_enable_set(hi_bool hbra_enable)383 static hi_void ctrl_audio_hbra_enable_set(hi_bool hbra_enable)
384 {
385 hdmi_reg_i2s_hbra_on_set(hbra_enable);
386 return;
387 }
388
ctrl_audio_hbra_enable_get(hi_void)389 static hi_bool ctrl_audio_hbra_enable_get(hi_void)
390 {
391 if (hdmi_reg_i2s_hbra_on_get()) {
392 return HI_TRUE;
393 }
394 return HI_FALSE;
395 }
396
ctrl_audio_i2s_ctrl_set(const ctrl_i2s * i2s_ctrl)397 static hi_void ctrl_audio_i2s_ctrl_set(const ctrl_i2s *i2s_ctrl)
398 {
399 hdmi_reg_i2s_1st_shift_set(i2s_ctrl->sck_shift_one);
400 hdmi_reg_i2s_ws_polarity_set(i2s_ctrl->polarity_ws_msb_left);
401 hdmi_reg_i2s_justify_set(i2s_ctrl->justify_ws_right);
402 hdmi_reg_i2s_data_dir_set(i2s_ctrl->data_dir_msb_first);
403 hdmi_reg_i2s_vbit_set(i2s_ctrl->vbit_compress);
404 hdmi_reg_i2s_length_set(i2s_ctrl->in_bit_length);
405 hdmi_reg_i2s_ch_swap_set(i2s_ctrl->channel_lr_swap);
406
407 return;
408 }
409
ctrl_audio_i2s_status_set(const ctrl_i2s_status * i2s_status)410 static hi_void ctrl_audio_i2s_status_set(const ctrl_i2s_status *i2s_status)
411 {
412 /* byte0_a config (0: consumer applications, 1: professional applications) */
413 hdmi_reg_chst_byte0_aset(i2s_status->professional_app);
414 /* byte0_b config (0: PCM, 1:compress) */
415 hdmi_reg_chst_byte0_bset(i2s_status->compress);
416 hdmi_reg_chst_byte3_fs_set(i2s_status->samp_rate);
417 hdmi_reg_chst_byte3_clock_accuracy_set(i2s_status->clk_accuracy);
418 hdmi_reg_chst_byte4_org_fs_set(i2s_status->org_rate);
419 hdmi_reg_chst_byte4_length_set(i2s_status->out_bit_length);
420
421 return;
422 }
423
ctrl_audio_fifo_ctrl_set(const ctrl_fifo * fifo_ctrl)424 static hi_void ctrl_audio_fifo_ctrl_set(const ctrl_fifo *fifo_ctrl)
425 {
426 hdmi_reg_aud_fifo_test_set(fifo_ctrl->test);
427 hdmi_reg_aud_fifo_hbr_mask_set(fifo_ctrl->hbra_mask);
428 return;
429 }
430
ctrl_audio_reset(hi_void)431 static hi_void ctrl_audio_reset(hi_void)
432 {
433 hdmi_reg_tx_afifo_srst_req_set(HI_TRUE);
434 hdmi_reg_tx_acr_srst_req_set(HI_TRUE);
435 hdmi_reg_tx_aud_srst_req_set(HI_TRUE);
436 hdmi_reg_tx_afifo_srst_req_set(HI_FALSE);
437 hdmi_reg_tx_acr_srst_req_set(HI_FALSE);
438 hdmi_reg_tx_aud_srst_req_set(HI_FALSE);
439
440 return;
441 }
442
ctrl_avmute_set(const hdmi_avmute_cfg * avmute_cfg)443 static hi_void ctrl_avmute_set(const hdmi_avmute_cfg *avmute_cfg)
444 {
445 hdmi_reg_cea_cp_en_set(HI_FALSE);
446 /* set GCP set mute & clr mute */
447 hdmi_reg_cp_set_avmute_set(avmute_cfg->mute_set);
448 hdmi_reg_cp_clr_avmute_set(avmute_cfg->mute_clr);
449 /* set GCP avmute function enable, sent loop */
450 hdmi_reg_cea_cp_rpt_cnt_set(avmute_cfg->rpt_cnt);
451 hdmi_reg_cea_cp_rpt_en_set(avmute_cfg->mute_pkg_en);
452 hdmi_reg_cea_cp_en_set(avmute_cfg->mute_pkg_en);
453
454 return;
455 }
456
ctrl_avmute_get(hi_bool * enable)457 static hi_s32 ctrl_avmute_get(hi_bool *enable)
458 {
459 *enable = HI_FALSE;
460
461 if (hdmi_reg_cp_set_avmute_get() || hdmi_reg_cea_cp_rpt_en_get()) {
462 if (hdmi_reg_cp_set_avmute_get()) {
463 *enable = HI_TRUE;
464 }
465 }
466
467 return HI_SUCCESS;
468 }
469
ctrl_video_path_deep_clr_set(hi_bool enable_gcp,hdmi_deep_color deep_color_bit)470 static hi_void ctrl_video_path_deep_clr_set(hi_bool enable_gcp, hdmi_deep_color deep_color_bit)
471 {
472 hdmi_reg_tmds_pack_mode_set(deep_color_bit);
473 hdmi_reg_dc_pkt_en_set(enable_gcp);
474 return;
475 }
476
ctrl_video_path_polarity_set(const hdmi_sync_pol_type * out_sync_pol)477 static hi_s32 ctrl_video_path_polarity_set(const hdmi_sync_pol_type *out_sync_pol)
478 {
479 hi_u32 sync_pol_cfg = 0;
480
481 if (out_sync_pol->h_pol_inver) {
482 hdmi_set_bit(sync_pol_cfg, CTRL_SYCN_POL_H_BIT);
483 } else {
484 hdmi_clr_bit(sync_pol_cfg, CTRL_SYCN_POL_H_BIT);
485 }
486
487 if (out_sync_pol->v_pol_inver) {
488 hdmi_set_bit(sync_pol_cfg, CTRL_SYCN_POL_V_BIT);
489 } else {
490 hdmi_clr_bit(sync_pol_cfg, CTRL_SYCN_POL_V_BIT);
491 }
492
493 if (out_sync_pol->de_inver) {
494 hdmi_set_bit(sync_pol_cfg, CTRL_SYCN_POL_DE_BIT);
495 } else {
496 hdmi_clr_bit(sync_pol_cfg, CTRL_SYCN_POL_DE_BIT);
497 }
498
499 hdmi_reg_inver_sync_set(sync_pol_cfg);
500 hdmi_reg_syncmask_en_set(HI_FALSE);
501
502 return HI_SUCCESS;
503 }
504
ctrl_video_path_dither_set(hi_bool enable,hdmi_video_dither dither_mode)505 static hi_void ctrl_video_path_dither_set(hi_bool enable, hdmi_video_dither dither_mode)
506 {
507 hdmi_reg_dither_rnd_bypass_set((!enable));
508 hdmi_reg_dither_mode_set(dither_mode);
509 return;
510 }
511
ctrl_video_color_rgb_set(hi_bool rgb_in,hi_bool rgb_out)512 static hi_void ctrl_video_color_rgb_set(hi_bool rgb_in, hi_bool rgb_out)
513 {
514 hi_u32 reg_value;
515
516 reg_value = hdmi_reg_csc_mode_get();
517
518 if (rgb_in) {
519 hdmi_set_bit(reg_value, CTRL_RGB_IN_BIT);
520 } else {
521 hdmi_clr_bit(reg_value, CTRL_RGB_IN_BIT);
522 }
523
524 if (rgb_out) {
525 hdmi_set_bit(reg_value, CTRL_RGB_OUT_BIT);
526 } else {
527 hdmi_clr_bit(reg_value, CTRL_RGB_OUT_BIT);
528 }
529 hdmi_reg_csc_mode_set(reg_value);
530
531 return;
532 }
533
ctrl_video_color_csc_set(hi_bool csc_enable)534 static hi_void ctrl_video_color_csc_set(hi_bool csc_enable)
535 {
536 hdmi_reg_csc_en_set(csc_enable);
537 return;
538 }
539
ctrl_video_color_ycbcr422_set(hi_bool enable)540 static hi_void ctrl_video_color_ycbcr422_set(hi_bool enable)
541 {
542 if (enable) {
543 hdmi_reg_vmux_y_sel_set(CTRL_CHANNEL0_Y422);
544 hdmi_reg_vmux_cb_sel_set(CTRL_CHANNEL1_Y422);
545 hdmi_reg_vmux_cr_sel_set(CTRL_CHANNEL2_Y422);
546 } else {
547 hdmi_reg_vmux_y_sel_set(CTRL_CHANNEL0_Y);
548 hdmi_reg_vmux_cb_sel_set(CTRL_CHANNEL1_CB);
549 hdmi_reg_vmux_cr_sel_set(CTRL_CHANNEL2_CR);
550 }
551 return;
552 }
553
ctrl_video_color_ycbcr420_set(hi_bool enable)554 static hi_void ctrl_video_color_ycbcr420_set(hi_bool enable)
555 {
556 hdmi_reg_demux_420_en_set(enable);
557 hdmi_reg_pxl_div_en_set(enable);
558 return;
559 }
560
ctrl_video_color_dwsm_vert_set(hi_bool dwsm_vert)561 static hi_void ctrl_video_color_dwsm_vert_set(hi_bool dwsm_vert)
562 {
563 hdmi_reg_dwsm_vert_bypass_set(!dwsm_vert);
564 hdmi_reg_dwsm_vert_en_set(dwsm_vert);
565 return;
566 }
567
ctrl_video_color_dwsm_hori_set(hi_bool dwsm_hori)568 static hi_void ctrl_video_color_dwsm_hori_set(hi_bool dwsm_hori)
569 {
570 hdmi_reg_hori_filter_en_set(dwsm_hori);
571 hdmi_reg_dwsm_hori_en_set(dwsm_hori);
572 return;
573 }
574
ctrl_video_path_colorimetry_set(hdmi_hal_colorimetry in_colormetry,hdmi_hal_colorimetry out_colormetry)575 static hi_void ctrl_video_path_colorimetry_set(hdmi_hal_colorimetry in_colormetry, hdmi_hal_colorimetry out_colormetry)
576 {
577 hi_u32 csc_mode;
578
579 csc_mode = hdmi_reg_csc_mode_get();
580
581 out_colormetry = (hi_u32)out_colormetry & CTRL_COLORMETRY_MASK;
582 csc_mode &= CTRL_COLORMETRY_OUT_MASK;
583 csc_mode |= (hi_u32)out_colormetry << CTRL_COLORMETRY_OUT_BIT;
584
585 in_colormetry = (hi_u32)in_colormetry & CTRL_COLORMETRY_MASK;
586 csc_mode &= CTRL_COLORMETRY_IN_MASK;
587 csc_mode |= (hi_u32)in_colormetry << CTRL_COLORMETRY_IN_BIT;
588
589 hdmi_reg_csc_mode_set(csc_mode);
590
591 return;
592 }
593
videopath_colorspace_param_get(hdmi_colorspace in,hdmi_colorspace out,ctrl_colorspace_en * en)594 static hi_void videopath_colorspace_param_get(hdmi_colorspace in, hdmi_colorspace out, ctrl_colorspace_en *en)
595 {
596 if (in == HDMI_COLORSPACE_YCBCR444) {
597 switch (out) {
598 case HDMI_COLORSPACE_YCBCR422:
599 en->y422_enable = HI_TRUE;
600 en->dwsm_hori_enable = HI_TRUE;
601 break;
602 case HDMI_COLORSPACE_YCBCR420:
603 en->dwsm_hori_enable = HI_TRUE;
604 en->y420_enable = HI_TRUE;
605 en->dwsm_vert_enable = HI_TRUE;
606 break;
607 case HDMI_COLORSPACE_RGB:
608 en->out_rgb = HI_TRUE;
609 en->csc_enable = HI_TRUE;
610 break;
611 default:
612 break;
613 }
614 } else if (in == HDMI_COLORSPACE_RGB) {
615 switch (out) {
616 case HDMI_COLORSPACE_YCBCR444:
617 en->in_rgb = HI_TRUE;
618 en->csc_enable = HI_TRUE;
619 break;
620 case HDMI_COLORSPACE_YCBCR422:
621 en->in_rgb = HI_TRUE;
622 en->csc_enable = HI_TRUE;
623 en->y422_enable = HI_TRUE;
624 en->dwsm_hori_enable = HI_TRUE;
625 break;
626 case HDMI_COLORSPACE_YCBCR420:
627 en->in_rgb = HI_TRUE;
628 en->csc_enable = HI_TRUE;
629 en->dwsm_hori_enable = HI_TRUE;
630 en->y420_enable = HI_TRUE;
631 en->dwsm_vert_enable = HI_TRUE;
632 break;
633 default:
634 en->in_rgb = HI_TRUE;
635 en->out_rgb = HI_TRUE;
636 break;
637 }
638 } else {
639 hdmi_warn("un-expected in_color_space=%u\n", in);
640 }
641
642 return;
643 }
644
ctrl_video_path_color_space_set(hdmi_colorspace in_color_space,hdmi_colorspace out_color_space)645 static hi_bool ctrl_video_path_color_space_set(hdmi_colorspace in_color_space, hdmi_colorspace out_color_space)
646 {
647 ctrl_colorspace_en colorspace_en = {0};
648
649 videopath_colorspace_param_get(in_color_space, out_color_space, &colorspace_en);
650
651 hdmi_info("ctrl csc set:\n"
652 "\tin_rgb=%u, out_rgb=%u, csc_enable=%u \n"
653 "\ty422_enable=%u, dwsm_hori_enable=%u \n"
654 "\ty420_enable=%u, dwsm_vert_enable=%u \n",
655 colorspace_en.in_rgb, colorspace_en.out_rgb, colorspace_en.csc_enable,
656 colorspace_en.y422_enable, colorspace_en.dwsm_hori_enable,
657 colorspace_en.y420_enable, colorspace_en.dwsm_vert_enable);
658
659 ctrl_video_color_rgb_set(colorspace_en.in_rgb, colorspace_en.out_rgb);
660 ctrl_video_color_ycbcr422_set(colorspace_en.y422_enable);
661 ctrl_video_color_dwsm_hori_set(colorspace_en.dwsm_hori_enable);
662 ctrl_video_color_ycbcr420_set(colorspace_en.y420_enable);
663 ctrl_video_color_dwsm_vert_set(colorspace_en.dwsm_vert_enable);
664 ctrl_video_color_csc_set(colorspace_en.csc_enable);
665
666 return colorspace_en.csc_enable;
667 }
668
ctrl_video_path_quantization_set(hdmi_quantization_range in_quantization,hdmi_quantization_range out_quantization)669 static hi_void ctrl_video_path_quantization_set(hdmi_quantization_range in_quantization,
670 hdmi_quantization_range out_quantization)
671 {
672 hi_u32 csc_mode;
673
674 csc_mode = hdmi_reg_csc_mode_get();
675
676 if (in_quantization != HDMI_QUANTIZATION_RANGE_LIMITED) {
677 hdmi_set_bit(csc_mode, CTRL_QUANTIZAION_IN_BIT);
678 } else {
679 hdmi_clr_bit(csc_mode, CTRL_QUANTIZAION_IN_BIT);
680 }
681
682 if (out_quantization != HDMI_QUANTIZATION_RANGE_LIMITED) {
683 hdmi_set_bit(csc_mode, CTRL_QUANTIZAION_OUT_BIT);
684 } else {
685 hdmi_clr_bit(csc_mode, CTRL_QUANTIZAION_OUT_BIT);
686 }
687
688 hdmi_reg_csc_mode_set(csc_mode);
689 hdmi_reg_csc_saturate_en_set(HI_TRUE);
690
691 return;
692 }
693
ctrl_vendor_infoframe_en_set(hi_bool enable)694 static hi_s32 ctrl_vendor_infoframe_en_set(hi_bool enable)
695 {
696 hdmi_reg_cea_vsif_rpt_en_set(enable);
697 hdmi_reg_cea_vsif_en_set(enable);
698 return HI_SUCCESS;
699 }
700
ctrl_vendor_infoframe_data_set(const hi_u8 * if_data)701 static hi_s32 ctrl_vendor_infoframe_data_set(const hi_u8 *if_data)
702 {
703 /* HB config */
704 hdmi_reg_vsif_header_set(if_data[0], if_data[1], if_data[2]);
705 /* pkt0 config */
706 hdmi_reg_vsif_pkt0_low_set(if_data[3], if_data[4], if_data[5], if_data[6]);
707 hdmi_reg_vsif_pkt0_high_set(if_data[7], if_data[8], if_data[9]);
708 /* pkt1 config */
709 hdmi_reg_vsif_pkt1_low_set(if_data[10], if_data[11], if_data[12], if_data[13]);
710 hdmi_reg_vsif_pkt1_high_set(if_data[14], if_data[15], if_data[16]);
711 /* pkt2 config */
712 hdmi_reg_vsif_pkt2_low_set(if_data[17], if_data[18], if_data[19], if_data[20]);
713 hdmi_reg_vsif_pkt2_high_set(if_data[21], if_data[22], if_data[23]);
714 /* pkt3 config */
715 hdmi_reg_vsif_pkt3_low_set(if_data[24], if_data[25], if_data[26], if_data[27]);
716 hdmi_reg_vsif_pkt3_high_set(if_data[28], if_data[29], if_data[30]);
717
718 return HI_SUCCESS;
719 }
720
ctrl_avi_infoframe_en_set(hi_bool enable)721 static hi_s32 ctrl_avi_infoframe_en_set(hi_bool enable)
722 {
723 /* repeat enable */
724 hdmi_reg_cea_avi_rpt_en_set(enable);
725 /* info_frame enable */
726 hdmi_reg_cea_avi_en_set(enable);
727
728 return HI_SUCCESS;
729 }
730
ctrl_avi_infoframe_data_set(const hi_u8 * if_data)731 static hi_s32 ctrl_avi_infoframe_data_set(const hi_u8 *if_data)
732 {
733 /* HB config */
734 hdmi_reg_avi_pkt_header_hb_set(if_data[0], if_data[1], if_data[2]);
735 hdmi_reg_avi_pkt0_low_set(if_data[3], if_data[4], if_data[5], if_data[6]);
736 hdmi_reg_avi_pkt0_high_set(if_data[7], if_data[8], if_data[9]);
737 hdmi_reg_avi_pkt1_low_set(if_data[10], if_data[11], if_data[12], if_data[13]);
738 hdmi_reg_avi_pkt1_high_set(if_data[14], if_data[15], if_data[16]);
739 hdmi_reg_avi_pkt2_low_set(if_data[17], if_data[18], if_data[19], if_data[20]);
740 hdmi_reg_avi_pkt2_high_set(if_data[21], if_data[22], if_data[23]);
741 hdmi_reg_avi_pkt3_low_set(if_data[24], if_data[25], if_data[26], if_data[27]);
742 hdmi_reg_avi_pkt3_high_set(if_data[28], if_data[29], if_data[30]);
743
744 return HI_SUCCESS;
745 }
746
ctrl_tmds_mode_set(hdmi_tmds_mode tmds_mode)747 static hi_s32 ctrl_tmds_mode_set(hdmi_tmds_mode tmds_mode)
748 {
749 switch (tmds_mode) {
750 case HDMI_TMDS_MODE_DVI:
751 hdmi_reg_hdmi_mode_set(HI_FALSE);
752 #if defined(HDMI_PRODUCT_HI3519A)
753 /*
754 * in case of HDMI_TMDS_MODE_DVI,hdmi_dvi_sel should be set 0,
755 * eess_mode_en should be set the default value
756 */
757 hdmi_reg_hdmi_dvi_sel_set(HI_FALSE);
758 hdmi_reg_eess_mode_en_set(HI_TRUE);
759 #endif
760 break;
761 case HDMI_TMDS_MODE_HDMI_1_4:
762 hdmi_reg_hdmi_mode_set(HI_TRUE);
763 hdmi_reg_enc_hdmi2_on_set(HI_FALSE);
764 #if defined(HDMI_PRODUCT_HI3519A)
765 /*
766 * in case of HDMI_TMDS_HDMI_1_4,hdmi_dvi_sel should be set 1,
767 * eess_mode_en should be set 1
768 */
769 hdmi_reg_hdmi_dvi_sel_set(HI_TRUE);
770 hdmi_reg_eess_mode_en_set(HI_TRUE);
771 #endif
772 break;
773 case HDMI_TMDS_MODE_HDMI_2_0:
774 hdmi_reg_hdmi_mode_set(HI_TRUE);
775 hdmi_reg_enc_hdmi2_on_set(HI_TRUE);
776 hdmi_reg_enc_bypass_set(HI_FALSE);
777 #if defined(HDMI_PRODUCT_HI3519A)
778 /*
779 * in case of HDMI_TMDS_MODE_HDMI_2_0,hdmi_dvi_sel should be set 1,
780 * eess_mode_en should be set 1
781 */
782 hdmi_reg_hdmi_dvi_sel_set(HI_TRUE);
783 hdmi_reg_eess_mode_en_set(HI_TRUE);
784 #endif
785 break;
786 default:
787 hdmi_warn("un-known tmds mode:%u\n", tmds_mode);
788 return HI_FAILURE;
789 }
790
791 return HI_SUCCESS;
792 }
793
ctrl_video_path_deep_clr_get(hi_bool * enable_gcp,hdmi_deep_color * deep_color_bit)794 static hi_s32 ctrl_video_path_deep_clr_get(hi_bool *enable_gcp, hdmi_deep_color *deep_color_bit)
795 {
796 *enable_gcp = hdmi_reg_dc_pkt_en_get() ? HI_TRUE : HI_FALSE;
797 *deep_color_bit = hdmi_reg_tmds_pack_mode_get();
798 return HI_SUCCESS;
799 }
800
ctrl_video_path_polarity_get(hdmi_sync_pol_type * out_sync_pol)801 static hi_s32 ctrl_video_path_polarity_get(hdmi_sync_pol_type *out_sync_pol)
802 {
803 hi_u32 sync_pol_cfg;
804
805 sync_pol_cfg = hdmi_reg_inver_sync_get();
806 out_sync_pol->h_pol_inver = is_bit_set(sync_pol_cfg, CTRL_SYCN_POL_H_BIT) ? HI_TRUE : HI_FALSE;
807 out_sync_pol->v_pol_inver = is_bit_set(sync_pol_cfg, CTRL_SYCN_POL_V_BIT) ? HI_TRUE : HI_FALSE;
808 out_sync_pol->de_inver = is_bit_set(sync_pol_cfg, CTRL_SYCN_POL_DE_BIT) ? HI_TRUE : HI_FALSE;
809
810 return HI_SUCCESS;
811 }
812
ctrl_video_path_dither_get(hi_bool * enable,hdmi_video_dither * dither_mode)813 static hi_s32 ctrl_video_path_dither_get(hi_bool *enable, hdmi_video_dither *dither_mode)
814 {
815 *enable = hdmi_reg_dither_rnd_bypass_get() ? HI_FALSE : HI_TRUE;
816 *dither_mode = hdmi_reg_dither_mode_get();
817 return HI_SUCCESS;
818 }
819
ctrl_video_color_rgb_get(hi_bool * rgb_in,hi_bool * rgb_out)820 static hi_void ctrl_video_color_rgb_get(hi_bool *rgb_in, hi_bool *rgb_out)
821 {
822 hi_u32 reg_value;
823
824 reg_value = hdmi_reg_csc_mode_get();
825 *rgb_in = is_bit_set(reg_value, CTRL_RGB_IN_BIT);
826 *rgb_out = is_bit_set(reg_value, CTRL_RGB_OUT_BIT);
827
828 return;
829 }
830
ctrl_video_color_csc_get(hi_void)831 static hi_bool ctrl_video_color_csc_get(hi_void)
832 {
833 if (hdmi_reg_csc_en_get()) {
834 return HI_TRUE;
835 }
836 return HI_FALSE;
837 }
838
ctrl_video_color_ycbcr422_get(hi_void)839 static hi_bool ctrl_video_color_ycbcr422_get(hi_void)
840 {
841 if ((hdmi_reg_vmux_y_sel_get() == CTRL_CHANNEL0_Y422) &&
842 (hdmi_reg_vmux_cb_sel_get() == CTRL_CHANNEL1_Y422) &&
843 (hdmi_reg_vmux_cr_sel_get() == CTRL_CHANNEL2_Y422)) {
844 return HI_TRUE;
845 }
846 return HI_FALSE;
847 }
848
ctrl_video_color_ycbcr420_get(hi_void)849 static hi_bool ctrl_video_color_ycbcr420_get(hi_void)
850 {
851 if ((hdmi_reg_demux_420_en_get()) && (hdmi_reg_pxl_div_en_get())) {
852 return HI_TRUE;
853 }
854 return HI_FALSE;
855 }
856
ctrl_video_color_dwsm_vert_get(hi_void)857 static hi_bool ctrl_video_color_dwsm_vert_get(hi_void)
858 {
859 if (hdmi_reg_dwsm_vert_en_get() && (!hdmi_reg_dwsm_vert_bypass_get())) {
860 return HI_TRUE;
861 }
862 return HI_FALSE;
863 }
864
ctrl_video_color_dwsm_hori_get(hi_void)865 static hi_bool ctrl_video_color_dwsm_hori_get(hi_void)
866 {
867 if (hdmi_reg_hori_filter_en_get() && hdmi_reg_dwsm_hori_en_get()) {
868 return HI_TRUE;
869 }
870 return HI_FALSE;
871 }
872
ctrl_video_path_color_space_get(hdmi_colorspace * in_color_space,hdmi_colorspace * out_color_space)873 static hi_void ctrl_video_path_color_space_get(hdmi_colorspace *in_color_space, hdmi_colorspace *out_color_space)
874 {
875 hi_bool in_rgb = HI_FALSE;
876 hi_bool out_rgb = HI_FALSE;
877
878 ctrl_video_color_rgb_get(&in_rgb, &out_rgb);
879 *in_color_space = in_rgb ? HDMI_COLORSPACE_RGB : HDMI_COLORSPACE_YCBCR444;
880 *out_color_space = out_rgb ? HDMI_COLORSPACE_RGB : HDMI_COLORSPACE_YCBCR444;
881
882 if (ctrl_video_color_ycbcr422_get() && ctrl_video_color_dwsm_hori_get()) {
883 *out_color_space = HDMI_COLORSPACE_YCBCR422;
884 }
885
886 if (ctrl_video_color_ycbcr420_get() && ctrl_video_color_dwsm_vert_get()) {
887 *out_color_space = HDMI_COLORSPACE_YCBCR420;
888 }
889
890 return;
891 }
892
ctrl_video_path_colormetry_get(hdmi_hal_colorimetry * in_colormetry,hdmi_hal_colorimetry * out_colormetry)893 static hi_s32 ctrl_video_path_colormetry_get(hdmi_hal_colorimetry *in_colormetry, hdmi_hal_colorimetry *out_colormetry)
894 {
895 hi_u32 csc_mode;
896
897 csc_mode = hdmi_reg_csc_mode_get();
898 *out_colormetry = (csc_mode & CTRL_COLORMETRY_OUT_MASK) >> CTRL_COLORMETRY_OUT_BIT;
899 *in_colormetry = (csc_mode & CTRL_COLORMETRY_OUT_MASK) >> CTRL_COLORMETRY_IN_BIT;
900
901 return HI_SUCCESS;
902 }
903
ctrl_video_path_quantization_get(hdmi_quantization_range * in_quantization,hdmi_quantization_range * out_quantization)904 static hi_s32 ctrl_video_path_quantization_get(hdmi_quantization_range *in_quantization,
905 hdmi_quantization_range *out_quantization)
906 {
907 hi_u32 csc_mode;
908
909 csc_mode = hdmi_reg_csc_mode_get();
910 *in_quantization =
911 is_bit_set(csc_mode, CTRL_QUANTIZAION_IN_BIT) ? HDMI_QUANTIZATION_RANGE_FULL : HDMI_QUANTIZATION_RANGE_LIMITED;
912 *out_quantization =
913 is_bit_set(csc_mode, CTRL_QUANTIZAION_OUT_BIT) ? HDMI_QUANTIZATION_RANGE_FULL : HDMI_QUANTIZATION_RANGE_LIMITED;
914
915 return HI_SUCCESS;
916 }
917
ctrl_tmds_mode_get(hdmi_tmds_mode * tmds_mode)918 static hi_s32 ctrl_tmds_mode_get(hdmi_tmds_mode *tmds_mode)
919 {
920 hi_bool hdmi_mode = HI_FALSE;
921 hi_bool hdmi2x_enable = HI_FALSE;
922
923 hdmi_mode = hdmi_reg_hdmi_mode_get();
924 hdmi2x_enable = hdmi_reg_enc_hdmi2_on_get();
925
926 if (!hdmi_mode) {
927 *tmds_mode = HDMI_TMDS_MODE_DVI;
928 } else if (hdmi_mode && (!hdmi2x_enable)) {
929 *tmds_mode = HDMI_TMDS_MODE_HDMI_1_4;
930 } else if (hdmi_mode && hdmi2x_enable) {
931 *tmds_mode = HDMI_TMDS_MODE_HDMI_2_0;
932 } else {
933 hdmi_warn("un-config tmds mode!\n");
934 return HI_FAILURE;
935 }
936
937 return HI_SUCCESS;
938 }
939
ctrl_vendor_infoframe_en_get(hi_bool * enable)940 static hi_s32 ctrl_vendor_infoframe_en_get(hi_bool *enable)
941 {
942 *enable = hdmi_reg_cea_vsif_rpt_en_get() ? HI_TRUE : HI_FALSE;
943 return HI_SUCCESS;
944 }
945
ctrl_vendor_infoframe_data_get(hi_u8 * if_data)946 static hi_s32 ctrl_vendor_infoframe_data_get(hi_u8 *if_data)
947 {
948 vsif_pkt_header vsif_pkt_head;
949 vsif_sub_pkt0_low vsif_sub_pkt0_l;
950 vsif_sub_pkt0_high vsif_sub_pkt0_h;
951 vsif_sub_pkt1_low vsif_sub_pkt1_l;
952 vsif_sub_pkt1_high vsif_sub_pkt1_h;
953 vsif_sub_pkt2_low vsif_sub_pkt2_l;
954 vsif_sub_pkt2_high vsif_sub_pkt2_h;
955 vsif_sub_pkt3_low vsif_sub_pkt3_l;
956 vsif_sub_pkt3_high vsif_sub_pkt3_h;
957
958 hdmi_reg_vsif_pkt_header_get(&vsif_pkt_head);
959 hdmi_reg_vsif_pkt0_low_get(&vsif_sub_pkt0_l);
960 hdmi_reg_vsif_pkt0_high_get(&vsif_sub_pkt0_h);
961 hdmi_reg_vsif_pkt1_low_get(&vsif_sub_pkt1_l);
962 hdmi_reg_vsif_pkt1_high_get(&vsif_sub_pkt1_h);
963 hdmi_reg_vsif_pkt2_low_get(&vsif_sub_pkt2_l);
964 hdmi_reg_vsif_pkt2_high_get(&vsif_sub_pkt2_h);
965 hdmi_reg_vsif_pkt3_low_get(&vsif_sub_pkt3_l);
966 hdmi_reg_vsif_pkt3_high_get(&vsif_sub_pkt3_h);
967
968 if_data[0] = vsif_pkt_head.bits.vsif_pkt_hb0;
969 if_data[1] = vsif_pkt_head.bits.vsif_pkt_hb1;
970 if_data[2] = vsif_pkt_head.bits.vsif_pkt_hb2;
971 if_data[3] = vsif_sub_pkt0_l.bits.vsif_sub_pkt0_pb0;
972 if_data[4] = vsif_sub_pkt0_l.bits.vsif_sub_pkt0_pb1;
973 if_data[5] = vsif_sub_pkt0_l.bits.vsif_sub_pkt0_pb2;
974 if_data[6] = vsif_sub_pkt0_l.bits.vsif_sub_pkt0_pb3;
975 if_data[7] = vsif_sub_pkt0_h.bits.vsif_sub_pkt0_pb4;
976 if_data[8] = vsif_sub_pkt0_h.bits.vsif_sub_pkt0_pb5;
977 if_data[9] = vsif_sub_pkt0_h.bits.vsif_sub_pkt0_pb6;
978 if_data[10] = vsif_sub_pkt1_l.bits.vsif_sub_pkt1_pb0;
979 if_data[11] = vsif_sub_pkt1_l.bits.vsif_sub_pkt1_pb1;
980 if_data[12] = vsif_sub_pkt1_l.bits.vsif_sub_pkt1_pb2;
981 if_data[13] = vsif_sub_pkt1_l.bits.vsif_sub_pkt1_pb3;
982 if_data[14] = vsif_sub_pkt1_h.bits.vsif_sub_pkt1_pb4;
983 if_data[15] = vsif_sub_pkt1_h.bits.vsif_sub_pkt1_pb5;
984 if_data[16] = vsif_sub_pkt1_h.bits.vsif_sub_pkt1_pb6;
985 if_data[17] = vsif_sub_pkt2_l.bits.vsif_sub_pkt2_pb0;
986 if_data[18] = vsif_sub_pkt2_l.bits.vsif_sub_pkt2_pb1;
987 if_data[19] = vsif_sub_pkt2_l.bits.vsif_sub_pkt2_pb2;
988 if_data[20] = vsif_sub_pkt2_l.bits.vsif_sub_pkt2_pb3;
989 if_data[21] = vsif_sub_pkt2_h.bits.vsif_sub_pkt2_pb4;
990 if_data[22] = vsif_sub_pkt2_h.bits.vsif_sub_pkt2_pb5;
991 if_data[23] = vsif_sub_pkt2_h.bits.vsif_sub_pkt2_pb6;
992 if_data[24] = vsif_sub_pkt3_l.bits.vsif_sub_pkt3_pb0;
993 if_data[25] = vsif_sub_pkt3_l.bits.vsif_sub_pkt3_pb1;
994 if_data[26] = vsif_sub_pkt3_l.bits.vsif_sub_pkt3_pb2;
995 if_data[27] = vsif_sub_pkt3_l.bits.vsif_sub_pkt3_pb3;
996 if_data[28] = vsif_sub_pkt3_h.bits.vsif_sub_pkt3_pb4;
997 if_data[29] = vsif_sub_pkt3_h.bits.vsif_sub_pkt3_pb5;
998 if_data[30] = vsif_sub_pkt3_h.bits.vsif_sub_pkt3_pb6;
999
1000 return HI_SUCCESS;
1001 }
1002
ctrl_avi_infoframe_en_get(hi_bool * enable)1003 static hi_s32 ctrl_avi_infoframe_en_get(hi_bool *enable)
1004 {
1005 *enable = hdmi_reg_cea_avi_en_get() ? HI_TRUE : HI_FALSE;
1006 return HI_SUCCESS;
1007 }
1008
ctrl_avi_infoframe_data_get(hi_u8 * if_data)1009 static hi_s32 ctrl_avi_infoframe_data_get(hi_u8 *if_data)
1010 {
1011 avi_pkt_header avi_pkt_head;
1012 avi_sub_pkt0_low avi_sub_pkt0_l;
1013 avi_sub_pkt0_high avi_sub_pkt0_h;
1014 avi_sub_pkt1_low avi_sub_pkt1_l;
1015 avi_sub_pkt1_high avi_sub_pkt1_h;
1016 avi_sub_pkt2_low avi_sub_pkt2_l;
1017 avi_sub_pkt2_high avi_sub_pkt2_h;
1018 avi_sub_pkt3_low avi_sub_pkt3_l;
1019 avi_sub_pkt3_high avi_sub_pkt3_h;
1020
1021 hdmi_reg_avi_pkt_header_hb_get(&avi_pkt_head);
1022 hdmi_reg_avi_pkt0_low_get(&avi_sub_pkt0_l);
1023 hdmi_reg_avi_pkt0_high_get(&avi_sub_pkt0_h);
1024 hdmi_reg_avi_pkt1_low_get(&avi_sub_pkt1_l);
1025 hdmi_reg_avi_pkt1_high_get(&avi_sub_pkt1_h);
1026 hdmi_reg_avi_pkt2_low_get(&avi_sub_pkt2_l);
1027 hdmi_reg_avi_pkt2_high_get(&avi_sub_pkt2_h);
1028 hdmi_reg_avi_pkt3_low_get(&avi_sub_pkt3_l);
1029 hdmi_reg_avi_pkt3_high_get(&avi_sub_pkt3_h);
1030
1031 if_data[0] = avi_pkt_head.bits.avi_pkt_hb0;
1032 if_data[1] = avi_pkt_head.bits.avi_pkt_hb1;
1033 if_data[2] = avi_pkt_head.bits.avi_pkt_hb2;
1034 if_data[3] = avi_sub_pkt0_l.bits.avi_sub_pkt0_pb0;
1035 if_data[4] = avi_sub_pkt0_l.bits.avi_sub_pkt0_pb1;
1036 if_data[5] = avi_sub_pkt0_l.bits.avi_sub_pkt0_pb2;
1037 if_data[6] = avi_sub_pkt0_l.bits.avi_sub_pkt0_pb3;
1038 if_data[7] = avi_sub_pkt0_h.bits.avi_sub_pkt0_pb4;
1039 if_data[8] = avi_sub_pkt0_h.bits.avi_sub_pkt0_pb5;
1040 if_data[9] = avi_sub_pkt0_h.bits.avi_sub_pkt0_pb6;
1041 if_data[10] = avi_sub_pkt1_l.bits.avi_sub_pkt1_pb0;
1042 if_data[11] = avi_sub_pkt1_l.bits.avi_sub_pkt1_pb1;
1043 if_data[12] = avi_sub_pkt1_l.bits.avi_sub_pkt1_pb2;
1044 if_data[13] = avi_sub_pkt1_l.bits.avi_sub_pkt1_pb3;
1045 if_data[14] = avi_sub_pkt1_h.bits.avi_sub_pkt1_pb4;
1046 if_data[15] = avi_sub_pkt1_h.bits.avi_sub_pkt1_pb5;
1047 if_data[16] = avi_sub_pkt1_h.bits.avi_sub_pkt1_pb6;
1048 if_data[17] = avi_sub_pkt2_l.bits.avi_sub_pkt2_pb0;
1049 if_data[18] = avi_sub_pkt2_l.bits.avi_sub_pkt2_pb1;
1050 if_data[19] = avi_sub_pkt2_l.bits.avi_sub_pkt2_pb2;
1051 if_data[20] = avi_sub_pkt2_l.bits.avi_sub_pkt2_pb3;
1052 if_data[21] = avi_sub_pkt2_h.bits.avi_sub_pkt2_pb4;
1053 if_data[22] = avi_sub_pkt2_h.bits.avi_sub_pkt2_pb5;
1054 if_data[23] = avi_sub_pkt2_h.bits.avi_sub_pkt2_pb6;
1055 if_data[24] = avi_sub_pkt3_l.bits.avi_sub_pkt3_pb0;
1056 if_data[25] = avi_sub_pkt3_l.bits.avi_sub_pkt3_pb1;
1057 if_data[26] = avi_sub_pkt3_l.bits.avi_sub_pkt3_pb2;
1058 if_data[27] = avi_sub_pkt3_l.bits.avi_sub_pkt3_pb3;
1059 if_data[28] = avi_sub_pkt3_h.bits.avi_sub_pkt3_pb4;
1060 if_data[29] = avi_sub_pkt3_h.bits.avi_sub_pkt3_pb5;
1061 if_data[30] = avi_sub_pkt3_h.bits.avi_sub_pkt3_pb6;
1062
1063 return HI_SUCCESS;
1064 }
1065
ctrl_timming_decect_get(ctrl_timming_detect * timing)1066 static hi_s32 ctrl_timming_decect_get(ctrl_timming_detect *timing)
1067 {
1068 timing->sync_sw_enable = HI_FALSE;
1069 hdmi_reg_sync_polarity_force_set(timing->sync_sw_enable);
1070
1071 timing->vsync_polarity = hdmi_reg_vsync_polarity_get() ? HI_TRUE : HI_FALSE;
1072 timing->hsync_polarity = hdmi_reg_hsync_polarity_get() ? HI_TRUE : HI_FALSE;
1073 timing->progressive = hdmi_reg_interlaced_get() ? HI_FALSE : HI_TRUE;
1074 timing->hsync_total = hdmi_reg_hsync_total_cnt_get();
1075 timing->hactive_cnt = hdmi_reg_hsync_active_cnt_get();
1076 timing->vsync_total = hdmi_reg_vsync_total_cnt_get();
1077 timing->vactive_cnt = hdmi_reg_vsync_active_cnt_get();
1078
1079 /* clear format detect status */
1080 hdmi_reg_fdt_status_clear_set(HI_FALSE);
1081 hdmi_reg_fdt_status_clear_set(HI_TRUE);
1082
1083 return HI_SUCCESS;
1084 }
1085
ctrl_video_mute_set(hi_bool enable)1086 static hi_void ctrl_video_mute_set(hi_bool enable)
1087 {
1088 hi_u32 data_value;
1089 hdmi_colorspace in_color_space = HDMI_COLORSPACE_RGB;
1090 hdmi_colorspace out_color_space = HDMI_COLORSPACE_RGB;
1091
1092 ctrl_video_path_color_space_get(&in_color_space, &out_color_space);
1093
1094 data_value = (in_color_space == HDMI_COLORSPACE_RGB) ? CTRL_BLACK_DATA_RGB_R : CTRL_BLACK_DATA_YUV_CR;
1095 hdmi_reg_solid_pattern_cr_set(data_value);
1096
1097 data_value = (in_color_space == HDMI_COLORSPACE_RGB) ? CTRL_BLACK_DATA_RGB_G : CTRL_BLACK_DATA_YUV_Y;
1098 hdmi_reg_solid_pattern_y_set(data_value);
1099
1100 data_value = (in_color_space == HDMI_COLORSPACE_RGB) ? CTRL_BLACK_DATA_RGB_B : CTRL_BLACK_DATA_YUV_CB;
1101 hdmi_reg_solid_pattern_cb_set(data_value);
1102
1103 hdmi_reg_video_blank_en_set(enable);
1104 hdmi_reg_solid_pattern_en_set(enable);
1105
1106 return;
1107 }
1108
ctrl_video_mute_get(hi_bool * enable)1109 static hi_s32 ctrl_video_mute_get(hi_bool *enable)
1110 {
1111 if (hdmi_reg_video_blank_en_get() && hdmi_reg_solid_pattern_en_get()) {
1112 *enable = HI_TRUE;
1113 } else {
1114 *enable = HI_FALSE;
1115 }
1116
1117 return HI_SUCCESS;
1118 }
1119
ctrl_audio_infoframe_en_set(hi_bool enable)1120 static hi_s32 ctrl_audio_infoframe_en_set(hi_bool enable)
1121 {
1122 /* repeat enable */
1123 hdmi_reg_cea_aud_rpt_en_set(enable);
1124 /* info_frame enable */
1125 hdmi_reg_cea_aud_en_set(enable);
1126 return HI_SUCCESS;
1127 }
1128
ctrl_audio_infoframe_en_get(hi_bool * enable)1129 static hi_s32 ctrl_audio_infoframe_en_get(hi_bool *enable)
1130 {
1131 *enable = hdmi_reg_cea_aud_en_get() ? HI_TRUE : HI_FALSE;
1132 return HI_SUCCESS;
1133 }
1134
ctrl_audio_infoframe_data_set(const hi_u8 * if_data)1135 static hi_s32 ctrl_audio_infoframe_data_set(const hi_u8 *if_data)
1136 {
1137 hdmi_reg_audio_pkt_header_set(if_data[0], if_data[1], if_data[2]);
1138 hdmi_reg_audio_pkt0_low_set(if_data[3], if_data[4], if_data[5], if_data[6]);
1139 hdmi_reg_audio_pkt0_high_set(if_data[7], if_data[8], if_data[9]);
1140 hdmi_reg_audio_pkt1_low_set(if_data[10], if_data[11], if_data[12], if_data[13]);
1141 hdmi_reg_audio_pkt1_high_set(if_data[14], if_data[15], if_data[16]);
1142 hdmi_reg_audio_pkt2_low_set(if_data[17], if_data[18], if_data[19], if_data[20]);
1143 hdmi_reg_audio_pkt2_high_set(if_data[21], if_data[22], if_data[23]);
1144 hdmi_reg_audio_pkt3_low_set(if_data[24], if_data[25], if_data[26], if_data[27]);
1145 hdmi_reg_audio_pkt3_high_set(if_data[28], if_data[29], if_data[30]);
1146
1147 return HI_SUCCESS;
1148 }
1149
ctrl_audio_infoframe_data_get(hi_u8 * if_data)1150 static hi_s32 ctrl_audio_infoframe_data_get(hi_u8 *if_data)
1151 {
1152 aif_pkt_header aif_pkt_head;
1153 aif_sub_pkt0_low aif_sub_pkt0_l;
1154 aif_sub_pkt0_high aif_sub_pkt0_h;
1155 aif_sub_pkt1_low aif_sub_pkt1_l;
1156 aif_sub_pkt1_high aif_sub_pkt1_h;
1157 aif_sub_pkt2_low aif_sub_pkt2_l;
1158 aif_sub_pkt2_high aif_sub_pkt2_h;
1159 aif_sub_pkt3_low aif_sub_pkt3_l;
1160 aif_sub_pkt3_high aif_sub_pkt3_h;
1161
1162 hdmi_reg_aif_pkt_header_get(&aif_pkt_head);
1163 hdmi_reg_aif_pkt0_low_get(&aif_sub_pkt0_l);
1164 hdmi_reg_aif_pkt0_high_get(&aif_sub_pkt0_h);
1165 hdmi_reg_aif_pkt1_low_get(&aif_sub_pkt1_l);
1166 hdmi_reg_aif_pkt1_high_get(&aif_sub_pkt1_h);
1167 hdmi_reg_aif_pkt2_low_get(&aif_sub_pkt2_l);
1168 hdmi_reg_aif_pkt2_high_get(&aif_sub_pkt2_h);
1169 hdmi_reg_aif_pkt3_low_get(&aif_sub_pkt3_l);
1170 hdmi_reg_aif_pkt3_high_get(&aif_sub_pkt3_h);
1171
1172 if_data[0] = aif_pkt_head.bits.aif_pkt_hb0;
1173 if_data[1] = aif_pkt_head.bits.aif_pkt_hb1;
1174 if_data[2] = aif_pkt_head.bits.aif_pkt_hb2;
1175 if_data[3] = aif_sub_pkt0_l.bits.aif_sub_pkt0_pb0;
1176 if_data[4] = aif_sub_pkt0_l.bits.aif_sub_pkt0_pb1;
1177 if_data[5] = aif_sub_pkt0_l.bits.aif_sub_pkt0_pb2;
1178 if_data[6] = aif_sub_pkt0_l.bits.aif_sub_pkt0_pb3;
1179 if_data[7] = aif_sub_pkt0_h.bits.aif_sub_pkt0_pb4;
1180 if_data[8] = aif_sub_pkt0_h.bits.aif_sub_pkt0_pb5;
1181 if_data[9] = aif_sub_pkt0_h.bits.aif_sub_pkt0_pb6;
1182 if_data[10] = aif_sub_pkt1_l.bits.aif_sub_pkt1_pb0;
1183 if_data[11] = aif_sub_pkt1_l.bits.aif_sub_pkt1_pb1;
1184 if_data[12] = aif_sub_pkt1_l.bits.aif_sub_pkt1_pb2;
1185 if_data[13] = aif_sub_pkt1_l.bits.aif_sub_pkt1_pb3;
1186 if_data[14] = aif_sub_pkt1_h.bits.aif_sub_pkt1_pb4;
1187 if_data[15] = aif_sub_pkt1_h.bits.aif_sub_pkt1_pb5;
1188 if_data[16] = aif_sub_pkt1_h.bits.aif_sub_pkt1_pb6;
1189 if_data[17] = aif_sub_pkt2_l.bits.aif_sub_pkt2_pb0;
1190 if_data[18] = aif_sub_pkt2_l.bits.aif_sub_pkt2_pb1;
1191 if_data[19] = aif_sub_pkt2_l.bits.aif_sub_pkt2_pb2;
1192 if_data[20] = aif_sub_pkt2_l.bits.aif_sub_pkt2_pb3;
1193 if_data[21] = aif_sub_pkt2_h.bits.aif_sub_pkt2_pb4;
1194 if_data[22] = aif_sub_pkt2_h.bits.aif_sub_pkt2_pb5;
1195 if_data[23] = aif_sub_pkt2_h.bits.aif_sub_pkt2_pb6;
1196 if_data[24] = aif_sub_pkt3_l.bits.aif_sub_pkt3_pb0;
1197 if_data[25] = aif_sub_pkt3_l.bits.aif_sub_pkt3_pb1;
1198 if_data[26] = aif_sub_pkt3_l.bits.aif_sub_pkt3_pb2;
1199 if_data[27] = aif_sub_pkt3_l.bits.aif_sub_pkt3_pb3;
1200 if_data[28] = aif_sub_pkt3_h.bits.aif_sub_pkt3_pb4;
1201 if_data[29] = aif_sub_pkt3_h.bits.aif_sub_pkt3_pb5;
1202 if_data[30] = aif_sub_pkt3_h.bits.aif_sub_pkt3_pb6;
1203
1204 return HI_SUCCESS;
1205 }
1206
ctrl_gbd_infoframe_en_set(hi_bool enable)1207 static hi_s32 ctrl_gbd_infoframe_en_set(hi_bool enable)
1208 {
1209 hdmi_reg_cea_gamut_rpt_en_set(enable);
1210 hdmi_reg_cea_gamut_en_set(enable);
1211 return HI_SUCCESS;
1212 }
1213
ctrl_gbd_infoframe_en_get(hi_bool * enable)1214 static hi_s32 ctrl_gbd_infoframe_en_get(hi_bool *enable)
1215 {
1216 *enable = hdmi_reg_cea_gamut_en_get() ? HI_TRUE : HI_FALSE;
1217 return HI_SUCCESS;
1218 }
1219
ctrl_gbd_infoframe_data_get(hi_u8 * if_data)1220 static hi_s32 ctrl_gbd_infoframe_data_get(hi_u8 *if_data)
1221 {
1222 gamut_pkt_header gamut_pkt_head;
1223 gamut_sub_pkt0_low gamut_sub_pkt0_l;
1224 gamut_sub_pkt0_high gamut_sub_pkt0_h;
1225 gamut_sub_pkt1_low gamut_sub_pkt1_l;
1226 gamut_sub_pkt1_high gamut_sub_pkt1_h;
1227 gamut_sub_pkt2_low gamut_sub_pkt2_l;
1228 gamut_sub_pkt2_high gamut_sub_pkt2_h;
1229 gamut_sub_pkt3_low gamut_sub_pkt3_l;
1230 gamut_sub_pkt3_high gamut_sub_pkt3_h;
1231
1232 hdmi_reg_gamut_pkt_header_get(&gamut_pkt_head);
1233 hdmi_reg_gamut_pkt0_low_get(&gamut_sub_pkt0_l);
1234 hdmi_reg_gamut_pkt0_high_get(&gamut_sub_pkt0_h);
1235 hdmi_reg_gamut_pkt1_low_get(&gamut_sub_pkt1_l);
1236 hdmi_reg_gamut_pkt1_high_get(&gamut_sub_pkt1_h);
1237 hdmi_reg_gamut_pkt2_low_get(&gamut_sub_pkt2_l);
1238 hdmi_reg_gamut_pkt2_high_get(&gamut_sub_pkt2_h);
1239 hdmi_reg_gamut_pkt3_low_get(&gamut_sub_pkt3_l);
1240 hdmi_reg_gamut_pkt3_high_get(&gamut_sub_pkt3_h);
1241
1242 if_data[0] = gamut_pkt_head.bits.gamut_pkt_hb0;
1243 if_data[1] = gamut_pkt_head.bits.gamut_pkt_hb1;
1244 if_data[2] = gamut_pkt_head.bits.gamut_pkt_hb2;
1245 if_data[3] = gamut_sub_pkt0_l.bits.gamut_sub_pkt0_pb0;
1246 if_data[4] = gamut_sub_pkt0_l.bits.gamut_sub_pkt0_pb1;
1247 if_data[5] = gamut_sub_pkt0_l.bits.gamut_sub_pkt0_pb2;
1248 if_data[6] = gamut_sub_pkt0_l.bits.gamut_sub_pkt0_pb3;
1249 if_data[7] = gamut_sub_pkt0_h.bits.gamut_sub_pkt0_pb4;
1250 if_data[8] = gamut_sub_pkt0_h.bits.gamut_sub_pkt0_pb5;
1251 if_data[9] = gamut_sub_pkt0_h.bits.gamut_sub_pkt0_pb6;
1252 if_data[10] = gamut_sub_pkt1_l.bits.gamut_sub_pkt1_pb0;
1253 if_data[11] = gamut_sub_pkt1_l.bits.gamut_sub_pkt1_pb1;
1254 if_data[12] = gamut_sub_pkt1_l.bits.gamut_sub_pkt1_pb2;
1255 if_data[13] = gamut_sub_pkt1_l.bits.gamut_sub_pkt1_pb3;
1256 if_data[14] = gamut_sub_pkt1_h.bits.gamut_sub_pkt1_pb4;
1257 if_data[15] = gamut_sub_pkt1_h.bits.gamut_sub_pkt1_pb5;
1258 if_data[16] = gamut_sub_pkt1_h.bits.gamut_sub_pkt1_pb6;
1259 if_data[17] = gamut_sub_pkt2_l.bits.gamut_sub_pkt2_pb0;
1260 if_data[18] = gamut_sub_pkt2_l.bits.gamut_sub_pkt2_pb1;
1261 if_data[19] = gamut_sub_pkt2_l.bits.gamut_sub_pkt2_pb2;
1262 if_data[20] = gamut_sub_pkt2_l.bits.gamut_sub_pkt2_pb3;
1263 if_data[21] = gamut_sub_pkt2_h.bits.gamut_sub_pkt2_pb4;
1264 if_data[22] = gamut_sub_pkt2_h.bits.gamut_sub_pkt2_pb5;
1265 if_data[23] = gamut_sub_pkt2_h.bits.gamut_sub_pkt2_pb6;
1266 if_data[24] = gamut_sub_pkt3_l.bits.gamut_sub_pkt3_pb0;
1267 if_data[25] = gamut_sub_pkt3_l.bits.gamut_sub_pkt3_pb1;
1268 if_data[26] = gamut_sub_pkt3_l.bits.gamut_sub_pkt3_pb2;
1269 if_data[27] = gamut_sub_pkt3_l.bits.gamut_sub_pkt3_pb3;
1270 if_data[28] = gamut_sub_pkt3_h.bits.gamut_sub_pkt3_pb4;
1271 if_data[29] = gamut_sub_pkt3_h.bits.gamut_sub_pkt3_pb5;
1272 if_data[30] = gamut_sub_pkt3_h.bits.gamut_sub_pkt3_pb6;
1273
1274 return HI_SUCCESS;
1275 }
1276
ctrl_drm_infoframe_en_set(hi_bool enable)1277 static hi_s32 ctrl_drm_infoframe_en_set(hi_bool enable)
1278 {
1279 hdmi_reg_cea_gen_rpt_en_set(enable);
1280 hdmi_reg_cea_gen_en_set(enable);
1281 return HI_SUCCESS;
1282 }
1283
ctrl_drm_infoframe_en_get(hi_bool * enable)1284 static hi_s32 ctrl_drm_infoframe_en_get(hi_bool *enable)
1285 {
1286 *enable = hdmi_reg_cea_gen_en_get() ? HI_TRUE : HI_FALSE;
1287 return HI_SUCCESS;
1288 }
1289
ctrl_drm_infoframe_data_set(const hi_u8 * if_data)1290 static hi_s32 ctrl_drm_infoframe_data_set(const hi_u8 *if_data)
1291 {
1292 hdmi_reg_gen_pkt_header_set(if_data[0], if_data[1], if_data[2]);
1293 hdmi_reg_gen_pkt0_low_set(if_data[3], if_data[4], if_data[5], if_data[6]);
1294 hdmi_reg_gen_pkt0_high_set(if_data[7], if_data[8], if_data[9]);
1295 hdmi_reg_gen_pkt1_low_set(if_data[10], if_data[11], if_data[12], if_data[13]);
1296 hdmi_reg_gen_pkt1_high_set(if_data[14], if_data[15], if_data[16]);
1297 hdmi_reg_gen_pkt2_low_set(if_data[17], if_data[18], if_data[19], if_data[20]);
1298 hdmi_reg_gen_pkt2_high_set(if_data[21], if_data[22], if_data[23]);
1299 hdmi_reg_gen_pkt3_low_set(if_data[24], if_data[25], if_data[26], if_data[27]);
1300 hdmi_reg_gen_pkt3_high_set(if_data[28], if_data[29], if_data[30]);
1301
1302 return HI_SUCCESS;
1303 }
1304
ctrl_drm_infoframe_data_get(hi_u8 * if_data)1305 static hi_s32 ctrl_drm_infoframe_data_get(hi_u8 *if_data)
1306 {
1307 gen_pkt_header gen_pkt_head;
1308 gen_sub_pkt0_low gen_sub_pkt0_l;
1309 gen_sub_pkt0_high gen_sub_pkt0_h;
1310 gen_sub_pkt1_low gen_sub_pkt1_l;
1311 gen_sub_pkt1_high gen_sub_pkt1_h;
1312 gen_sub_pkt2_low gen_sub_pkt2_l;
1313 gen_sub_pkt2_high gen_sub_pkt2_h;
1314 gen_sub_pkt3_low gen_sub_pkt3_l;
1315 gen_sub_pkt3_high gen_sub_pkt3_h;
1316
1317 hdmi_reg_gen_pkt_header_get(&gen_pkt_head);
1318 hdmi_reg_gen_pkt0_low_get(&gen_sub_pkt0_l);
1319 hdmi_reg_gen_pkt0_high_get(&gen_sub_pkt0_h);
1320 hdmi_reg_gen_pkt1_low_get(&gen_sub_pkt1_l);
1321 hdmi_reg_gen_pkt1_high_get(&gen_sub_pkt1_h);
1322 hdmi_reg_gen_pkt2_low_get(&gen_sub_pkt2_l);
1323 hdmi_reg_gen_pkt2_high_get(&gen_sub_pkt2_h);
1324 hdmi_reg_gen_pkt3_low_get(&gen_sub_pkt3_l);
1325 hdmi_reg_gen_pkt3_high_get(&gen_sub_pkt3_h);
1326
1327 if_data[0] = gen_pkt_head.bits.gen_pkt_hb0;
1328 if_data[1] = gen_pkt_head.bits.gen_pkt_hb1;
1329 if_data[2] = gen_pkt_head.bits.gen_pkt_hb2;
1330 if_data[3] = gen_sub_pkt0_l.bits.gen_sub_pkt0_pb0;
1331 if_data[4] = gen_sub_pkt0_l.bits.gen_sub_pkt0_pb1;
1332 if_data[5] = gen_sub_pkt0_l.bits.gen_sub_pkt0_pb2;
1333 if_data[6] = gen_sub_pkt0_l.bits.gen_sub_pkt0_pb3;
1334 if_data[7] = gen_sub_pkt0_h.bits.gen_sub_pkt0_pb4;
1335 if_data[8] = gen_sub_pkt0_h.bits.gen_sub_pkt0_pb5;
1336 if_data[9] = gen_sub_pkt0_h.bits.gen_sub_pkt0_pb6;
1337 if_data[10] = gen_sub_pkt1_l.bits.gen_sub_pkt1_pb0;
1338 if_data[11] = gen_sub_pkt1_l.bits.gen_sub_pkt1_pb1;
1339 if_data[12] = gen_sub_pkt1_l.bits.gen_sub_pkt1_pb2;
1340 if_data[13] = gen_sub_pkt1_l.bits.gen_sub_pkt1_pb3;
1341 if_data[14] = gen_sub_pkt1_h.bits.gen_sub_pkt1_pb4;
1342 if_data[15] = gen_sub_pkt1_h.bits.gen_sub_pkt1_pb5;
1343 if_data[16] = gen_sub_pkt1_h.bits.gen_sub_pkt1_pb6;
1344 if_data[17] = gen_sub_pkt2_l.bits.gen_sub_pkt2_pb0;
1345 if_data[18] = gen_sub_pkt2_l.bits.gen_sub_pkt2_pb1;
1346 if_data[19] = gen_sub_pkt2_l.bits.gen_sub_pkt2_pb2;
1347 if_data[20] = gen_sub_pkt2_l.bits.gen_sub_pkt2_pb3;
1348 if_data[21] = gen_sub_pkt2_h.bits.gen_sub_pkt2_pb4;
1349 if_data[22] = gen_sub_pkt2_h.bits.gen_sub_pkt2_pb5;
1350 if_data[23] = gen_sub_pkt2_h.bits.gen_sub_pkt2_pb6;
1351 if_data[24] = gen_sub_pkt3_l.bits.gen_sub_pkt3_pb0;
1352 if_data[25] = gen_sub_pkt3_l.bits.gen_sub_pkt3_pb1;
1353 if_data[26] = gen_sub_pkt3_l.bits.gen_sub_pkt3_pb2;
1354 if_data[27] = gen_sub_pkt3_l.bits.gen_sub_pkt3_pb3;
1355 if_data[28] = gen_sub_pkt3_h.bits.gen_sub_pkt3_pb4;
1356 if_data[29] = gen_sub_pkt3_h.bits.gen_sub_pkt3_pb5;
1357 if_data[30] = gen_sub_pkt3_h.bits.gen_sub_pkt3_pb6;
1358
1359 return HI_SUCCESS;
1360 }
1361
ctrl_hpd_get(hi_void)1362 static hi_bool ctrl_hpd_get(hi_void)
1363 {
1364 hi_s32 hot_plug;
1365 hi_bool hpd = HI_FALSE;
1366
1367 hot_plug = hdmi_reg_hotplug_state_get();
1368
1369 if (hdmi_reg_hpd_polarity_ctl_get() > 0) {
1370 hpd = (hot_plug > 0) ? HI_FALSE : HI_TRUE;
1371 } else {
1372 hpd = (hot_plug > 0) ? HI_TRUE : HI_FALSE;
1373 }
1374
1375 return hpd;
1376 }
1377
ctrl_rsen_get(hi_void)1378 static hi_bool ctrl_rsen_get(hi_void)
1379 {
1380 if (hdmi_reg_phy_rx_sense_get()) {
1381 return HI_TRUE;
1382 }
1383 return HI_FALSE;
1384 }
1385
ctrl_hpd_intr_enable(hi_bool enable)1386 static hi_void ctrl_hpd_intr_enable(hi_bool enable)
1387 {
1388 hdmi_reg_aon_intr_stat0_set(HI_TRUE);
1389 hdmi_reg_aon_intr_mask0_set(enable);
1390 return;
1391 }
1392
1393 #ifdef HDMI_HDR_SUPPORT
ctrl_hpd_timer_invoke(const hdmi_ctrl_info * ctrl_info)1394 static hi_void ctrl_hpd_timer_invoke(const hdmi_ctrl_info *ctrl_info)
1395 {
1396 hi_u32 i;
1397 hi_u64 timeout;
1398 ctrl_hdr_timer *hdr_timer = HI_NULL;
1399
1400 for (i = 0; i < HDMI_TIMER_TYPE_BUTT; i++) {
1401 hdr_timer = &ctrl_info->hdr_timer[i];
1402 if (hdr_timer->enable != HI_TRUE) {
1403 continue;
1404 }
1405 timeout = hal_hdmi_mach_ms_get() - hdr_timer->start_time;
1406 if (timeout >= hdr_timer->time_length) {
1407 hdr_timer->enable = HI_FALSE;
1408 hdmi_info("ctrl timer %u disable!\n", hdr_timer->timer_type);
1409 switch (hdr_timer->timer_type) {
1410 case HDMI_TIMER_ZERO_DRMIF:
1411 ctrl_info->event_callback(ctrl_info->event_data, HDMI_EVENT_ZERO_DRMIF_TIMEOUT);
1412 break;
1413 case HDMI_TIMER_SDR_TO_HDR10:
1414 ctrl_info->event_callback(ctrl_info->event_data, HDMI_EVENT_SWITCH_TO_HDRMODE_TIMEOUT);
1415 break;
1416 default:
1417 break;
1418 }
1419 }
1420 }
1421
1422 return;
1423 }
1424 #endif
1425
ctrl_mach_ppd_callback(hi_void * data)1426 hi_void ctrl_mach_ppd_callback(hi_void *data)
1427 {
1428 hi_bool event = HI_FALSE;
1429 hdmi_ctrl_info *ctrl_info = (hdmi_ctrl_info *)data;
1430
1431 hdmi_if_null_return_void(data);
1432 hdmi_if_null_return_void(ctrl_info->event_data);
1433 hdmi_if_null_return_void(ctrl_info->event_callback);
1434
1435 if (hdmi_reg_aon_intr_stat0_get()) {
1436 /* clr intr */
1437 hdmi_reg_aon_intr_stat0_set(HI_TRUE);
1438 /* event */
1439 event = ctrl_hpd_get();
1440 if (event != ctrl_info->hpd) {
1441 ctrl_info->event_callback(ctrl_info->event_data,
1442 (event == HI_TRUE) ? HDMI_EVENT_HOTPLUG : HDMI_EVENT_HOTUNPLUG);
1443 ctrl_info->hpd = event;
1444 } else {
1445 hdmi_warn("HPD event not change: %u!\n", event);
1446 }
1447 }
1448
1449 if (hdmi_reg_aon_intr_stat1_get()) {
1450 /* clr intr */
1451 hdmi_reg_aon_intr_stat1_set(HI_TRUE);
1452 /* event */
1453 event = ctrl_rsen_get();
1454 if (event != ctrl_info->rsen) {
1455 ctrl_info->event_callback(ctrl_info->event_data,
1456 (event == HI_TRUE) ? HDMI_EVENT_RSEN_CONNECT : HDMI_EVENT_RSEN_DISCONNECT);
1457 ctrl_info->rsen = event;
1458 } else {
1459 hdmi_warn("RSEN event not change: %u!\n", event);
1460 }
1461 }
1462
1463 #ifdef HDMI_HDR_SUPPORT
1464 ctrl_hpd_timer_invoke(ctrl_info);
1465 #endif
1466
1467 return;
1468 }
1469
ctrl_null_packet_set(hi_bool enable)1470 static hi_s32 ctrl_null_packet_set(hi_bool enable)
1471 {
1472 hdmi_reg_null_pkt_en_set(enable);
1473 return HI_SUCCESS;
1474 }
1475
ctrl_video_dither_set(hdmi_video_path * videopath)1476 static hi_void ctrl_video_dither_set(hdmi_video_path *videopath)
1477 {
1478 hi_bool enable_gcp = HI_FALSE;
1479 hi_bool enable_dither = HI_FALSE;
1480 hdmi_video_dither dither_mode = HDMI_VIDEO_DITHER_DISABLE;
1481
1482 if (videopath->out_deep_color != HDMI_DEEP_COLOR_30BIT && videopath->out_deep_color != HDMI_DEEP_COLOR_36BIT) {
1483 videopath->out_deep_color = HDMI_DEEP_COLOR_24BIT;
1484 }
1485
1486 /* dither */
1487 switch (videopath->out_deep_color) {
1488 case HDMI_DEEP_COLOR_24BIT:
1489 switch (videopath->in_deep_color) {
1490 case HDMI_DEEP_COLOR_30BIT:
1491 enable_dither = HI_TRUE;
1492 dither_mode = HDMI_VIDEO_DITHER_10_8;
1493 break;
1494 case HDMI_DEEP_COLOR_36BIT:
1495 enable_dither = HI_TRUE;
1496 dither_mode = HDMI_VIDEO_DITHER_12_8;
1497 break;
1498 default:
1499 break;
1500 }
1501 break;
1502 case HDMI_DEEP_COLOR_30BIT:
1503 enable_gcp = HI_TRUE;
1504 if (videopath->in_deep_color == HDMI_DEEP_COLOR_36BIT) {
1505 enable_dither = HI_TRUE;
1506 dither_mode = HDMI_VIDEO_DITHER_12_10;
1507 }
1508 break;
1509 case HDMI_DEEP_COLOR_36BIT:
1510 enable_gcp = HI_TRUE;
1511 break;
1512 default:
1513 break;
1514 }
1515
1516 if (videopath->timing == HDMI_VIDEO_TIMING_1440X480I_60000 ||
1517 videopath->timing == HDMI_VIDEO_TIMING_1440X576I_50000 ||
1518 videopath->out_color_space == HDMI_COLORSPACE_YCBCR422) {
1519 enable_dither = HI_FALSE;
1520 dither_mode = HDMI_VIDEO_DITHER_DISABLE;
1521 }
1522
1523 ctrl_video_path_dither_set(enable_dither, dither_mode);
1524 ctrl_video_path_deep_clr_set(enable_gcp, videopath->out_deep_color);
1525
1526 return;
1527 }
1528
hal_hdmi_ctrl_init(hdmi_device_id hdmi,const hdmi_hal_init * hal_init)1529 hi_s32 hal_hdmi_ctrl_init(hdmi_device_id hdmi, const hdmi_hal_init *hal_init)
1530 {
1531 hi_s32 ret = HI_SUCCESS;
1532 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1533 hdmi_mach_ctrl mach_ctrl = {0};
1534
1535 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1536 hdmi_if_null_return(hal_init, HI_FAILURE);
1537
1538 if (!ctrl_info->init) {
1539 ret += hdmi_reg_crg_init();
1540 hdmi_if_null_return(hal_init->base_addr, HI_FAILURE);
1541 ret += hdmi_reg_aon_regs_init(hal_init->base_addr);
1542 ret += hdmi_reg_audio_path_regs_init(hal_init->base_addr);
1543 /* this functions will not be used at BVT */
1544 ret += hdmi_reg_tx_ctrl_regs_init(hal_init->base_addr);
1545 ret += hdmi_reg_tx_hdmi_regs_init(hal_init->base_addr);
1546 ret += hdmi_reg_video_path_regs_init(hal_init->base_addr);
1547
1548 drv_hdmi_prod_crg_gate_set(HI_TRUE);
1549 ctrl_info->event_callback = hal_init->event_callback;
1550 ctrl_info->event_data = hal_init->event_data;
1551 ctrl_info->init = HI_TRUE;
1552 mach_ctrl.data = ctrl_info;
1553 mach_ctrl.callback = ctrl_mach_ppd_callback;
1554 mach_ctrl.interval = HDMI_MACH_DEFUALT_INTERVAL;
1555 mach_ctrl.name = "HPD";
1556 ret += hal_hdmi_mach_register(&mach_ctrl, &ctrl_info->mach_id);
1557 ret += hal_hdmi_mach_start(ctrl_info->mach_id);
1558
1559 ctrl_hpd_intr_enable(HI_TRUE);
1560 }
1561
1562 return (ret != HI_SUCCESS) ? HI_FAILURE : HI_SUCCESS;
1563 }
1564
hal_hdmi_ctrl_deinit(hdmi_device_id hdmi)1565 hi_s32 hal_hdmi_ctrl_deinit(hdmi_device_id hdmi)
1566 {
1567 hi_s32 ret;
1568 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1569
1570 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1571 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1572
1573 ctrl_hpd_intr_enable(HI_FALSE);
1574 ret = hal_hdmi_mach_stop(ctrl_info->mach_id);
1575 ret += hal_hdmi_mach_unregister(ctrl_info->mach_id);
1576 ret += hdmi_reg_audio_path_regs_deinit();
1577 ret += hdmi_reg_aon_regs_deinit();
1578 ret += hdmi_reg_tx_ctrl_regs_deinit();
1579 ret += hdmi_reg_tx_hdmi_regs_deinit();
1580 ret += hdmi_reg_video_path_regs_deinit();
1581
1582 (hi_void)memset_s(ctrl_info, sizeof(hdmi_ctrl_info), 0, sizeof(hdmi_ctrl_info));
1583 ctrl_info->init = HI_FALSE;
1584
1585 return (ret != HI_SUCCESS) ? HI_FAILURE : HI_SUCCESS;
1586 }
1587
hal_hdmi_ctrl_avmute_set(hdmi_device_id hdmi,const hdmi_avmute_cfg * avmute_cfg)1588 hi_s32 hal_hdmi_ctrl_avmute_set(hdmi_device_id hdmi, const hdmi_avmute_cfg *avmute_cfg)
1589 {
1590 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1591
1592 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1593 hdmi_if_null_return(avmute_cfg, HI_FAILURE);
1594 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1595
1596 ctrl_avmute_set(avmute_cfg);
1597
1598 return HI_SUCCESS;
1599 }
1600
hal_hdmi_ctrl_avmute_get(hdmi_device_id hdmi,hi_bool * enable)1601 hi_s32 hal_hdmi_ctrl_avmute_get(hdmi_device_id hdmi, hi_bool *enable)
1602 {
1603 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1604
1605 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1606 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1607 hdmi_if_null_return(enable, HI_FAILURE);
1608
1609 return ctrl_avmute_get(enable);
1610 }
1611
hal_hdmi_ctrl_csc_set(hdmi_device_id hdmi,const hdmi_video_config * video_cfg)1612 hi_s32 hal_hdmi_ctrl_csc_set(hdmi_device_id hdmi, const hdmi_video_config *video_cfg)
1613 {
1614 hi_unused(hdmi);
1615 hdmi_if_null_return(video_cfg, HI_FAILURE);
1616
1617 ctrl_video_path_colorimetry_set(video_cfg->conv_std, video_cfg->conv_std);
1618 ctrl_video_path_quantization_set(video_cfg->out_csc_quantization, video_cfg->out_csc_quantization);
1619 ctrl_video_path_color_space_set(video_cfg->in_color_space, video_cfg->out_color_space);
1620
1621 return HI_SUCCESS;
1622 }
1623
hal_hdmi_ctrl_video_path_set(hdmi_device_id hdmi,hdmi_video_path * video_path)1624 hi_s32 hal_hdmi_ctrl_video_path_set(hdmi_device_id hdmi, hdmi_video_path *video_path)
1625 {
1626 errno_t errnumber;
1627 hi_s32 ret;
1628 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1629
1630 hdmi_if_null_return(video_path, HI_FAILURE);
1631 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1632 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1633
1634 errnumber = memcpy_s(&ctrl_info->video_path, sizeof(ctrl_info->video_path), video_path, sizeof(hdmi_video_path));
1635 hdmi_unequal_eok_return(errnumber, HI_ERR_HDMI_INVALID_PARA);
1636
1637 /* dither */
1638 ctrl_video_dither_set(video_path);
1639 ret = ctrl_video_path_polarity_set(&video_path->out_hv_sync_pol);
1640 ctrl_video_path_colorimetry_set(video_path->in_colormetry, video_path->out_colormetry);
1641 ctrl_video_path_quantization_set(video_path->in_quantization, video_path->out_quantization);
1642 ctrl_video_path_color_space_set(video_path->in_color_space, video_path->out_color_space);
1643
1644 return ret;
1645 }
1646
hal_hdmi_ctrl_tmds_mode_set(hdmi_device_id hdmi,hdmi_tmds_mode tmds_mode)1647 hi_s32 hal_hdmi_ctrl_tmds_mode_set(hdmi_device_id hdmi, hdmi_tmds_mode tmds_mode)
1648 {
1649 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1650
1651 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1652 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1653
1654 return ctrl_tmds_mode_set(tmds_mode);
1655 }
1656
hal_hdmi_ctrl_infoframe_en_set(hdmi_device_id hdmi,hdmi_infoframe_id infoframe_id,hi_bool enable)1657 hi_s32 hal_hdmi_ctrl_infoframe_en_set(hdmi_device_id hdmi, hdmi_infoframe_id infoframe_id, hi_bool enable)
1658 {
1659 hi_s32 ret;
1660 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1661
1662 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1663 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1664
1665 switch (infoframe_id) {
1666 case HDMI_INFOFRAME_TYPE_NULL:
1667 ret = ctrl_null_packet_set(enable);
1668 break;
1669 case HDMI_INFOFRAME_TYPE_VENDOR:
1670 ret = ctrl_vendor_infoframe_en_set(enable);
1671 break;
1672 case HDMI_INFOFRAME_TYPE_AVI:
1673 ret = ctrl_avi_infoframe_en_set(enable);
1674 break;
1675 case HDMI_INFOFRAME_TYPE_AUDIO:
1676 ret = ctrl_audio_infoframe_en_set(enable);
1677 break;
1678 case HDMI_INFOFRAME_TYPE_GBD:
1679 ret = ctrl_gbd_infoframe_en_set(enable);
1680 break;
1681 case HDMI_INFOFRAME_TYPE_DRM:
1682 ret = ctrl_drm_infoframe_en_set(enable);
1683 break;
1684 default:
1685 hdmi_warn("un-support infoframe type:%u!\n", infoframe_id);
1686 ret = HI_FAILURE;
1687 break;
1688 }
1689
1690 return ret;
1691 }
1692
hal_hdmi_ctrl_infoframe_data_set(hdmi_device_id hdmi,hdmi_infoframe_id infoframe_id,const hi_u8 * if_data,hi_u32 data_len)1693 hi_s32 hal_hdmi_ctrl_infoframe_data_set(hdmi_device_id hdmi, hdmi_infoframe_id infoframe_id,
1694 const hi_u8 *if_data, hi_u32 data_len)
1695 {
1696 hi_s32 ret;
1697 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1698
1699 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1700 hdmi_if_null_return(if_data, HI_FAILURE);
1701 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1702
1703 if (data_len < HDMI_INFOFRAME_DATA_SIZE) {
1704 hdmi_warn("infoframe data size err, is %u!\n", data_len);
1705 }
1706
1707 switch (infoframe_id) {
1708 case HDMI_INFOFRAME_TYPE_VENDOR:
1709 ret = ctrl_vendor_infoframe_data_set(if_data);
1710 break;
1711 case HDMI_INFOFRAME_TYPE_AVI:
1712 ret = ctrl_avi_infoframe_data_set(if_data);
1713 break;
1714 case HDMI_INFOFRAME_TYPE_AUDIO:
1715 ret = ctrl_audio_infoframe_data_set(if_data);
1716 break;
1717 case HDMI_INFOFRAME_TYPE_DRM:
1718 ret = ctrl_drm_infoframe_data_set(if_data);
1719 break;
1720 default:
1721 hdmi_warn("un-support infoframe type:%u!\n", infoframe_id);
1722 ret = HI_FAILURE;
1723 break;
1724 }
1725
1726 return ret;
1727 }
1728
hal_hdmi_ctrl_data_reset(hdmi_device_id hdmi,hi_bool debug_mode,hi_u32 delay_ms)1729 hi_s32 hal_hdmi_ctrl_data_reset(hdmi_device_id hdmi, hi_bool debug_mode, hi_u32 delay_ms)
1730 {
1731 static hi_u32 delay;
1732 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1733
1734 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1735 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1736
1737 hdmi_reg_tx_acr_srst_req_set(HI_TRUE);
1738 hdmi_reg_tx_afifo_srst_req_set(HI_TRUE);
1739 hdmi_reg_tx_aud_srst_req_set(HI_TRUE);
1740 hdmi_reg_tx_hdmi_srst_req_set(HI_TRUE);
1741 osal_udelay(CTRL_REAET_WAIT_TIME);
1742 hdmi_reg_tx_acr_srst_req_set(HI_FALSE);
1743 hdmi_reg_tx_afifo_srst_req_set(HI_FALSE);
1744 hdmi_reg_tx_aud_srst_req_set(HI_FALSE);
1745 /* TOP rst: will also pack_fifo_ctrl reg_fifo_manu_rst */
1746 hdmi_reg_tx_hdmi_srst_req_set(HI_FALSE);
1747
1748 if (debug_mode) {
1749 delay = delay_ms;
1750 }
1751
1752 if (delay) {
1753 osal_msleep(delay);
1754 hdmi_info("data_rst %u ms\n", delay);
1755 }
1756
1757 return HI_SUCCESS;
1758 }
1759
hal_hdmi_ctrl_video_mute_set(hdmi_device_id hdmi,hi_bool enable)1760 hi_s32 hal_hdmi_ctrl_video_mute_set(hdmi_device_id hdmi, hi_bool enable)
1761 {
1762 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1763
1764 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1765 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1766
1767 ctrl_video_mute_set(enable);
1768
1769 return HI_SUCCESS;
1770 }
1771
hal_hdmi_ctrl_video_mute_get(hdmi_device_id hdmi,hi_bool * enable)1772 hi_s32 hal_hdmi_ctrl_video_mute_get(hdmi_device_id hdmi, hi_bool *enable)
1773 {
1774 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1775
1776 hdmi_if_null_return(enable, HI_FAILURE);
1777 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1778 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1779
1780 return ctrl_video_mute_get(enable);
1781 }
1782
hal_hdmi_ctrl_audio_mute_set(hdmi_device_id hdmi,hi_bool enable)1783 hi_s32 hal_hdmi_ctrl_audio_mute_set(hdmi_device_id hdmi, hi_bool enable)
1784 {
1785 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1786
1787 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1788 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1789
1790 ctrl_audio_mute_set(enable);
1791
1792 return HI_SUCCESS;
1793 }
1794
hal_hdmi_ctrl_audio_path_enable_set(hdmi_device_id hdmi,hi_bool enable)1795 hi_s32 hal_hdmi_ctrl_audio_path_enable_set(hdmi_device_id hdmi, hi_bool enable)
1796 {
1797 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1798
1799 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1800 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1801
1802 ctrl_audio_path_enable_set(enable);
1803
1804 return HI_SUCCESS;
1805 }
1806
hal_hdmi_ctrl_audio_path_set(hdmi_device_id hdmi,const hdmi_audio_path * audio_path)1807 hi_s32 hal_hdmi_ctrl_audio_path_set(hdmi_device_id hdmi, const hdmi_audio_path *audio_path)
1808 {
1809 errno_t ret;
1810 hi_u32 cts_value, n_value, org_reg_rate_cfg;
1811 hi_bool muti_layout = HI_FALSE;
1812 hi_bool spdif_enable = HI_FALSE;
1813 hi_bool hbra_enable = HI_FALSE;
1814 ctrl_i2s_status i2s_status = {0};
1815 ctrl_i2s i2s_ctrl = {0};
1816 ctrl_fifo fifo_ctrl = {0};
1817 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1818
1819 hdmi_if_null_return(audio_path, HI_FAILURE);
1820 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1821 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1822
1823 ret = memcpy_s(&ctrl_info->audio_path, sizeof(ctrl_info->audio_path), audio_path, sizeof(hdmi_audio_path));
1824 hdmi_unequal_eok_return(ret, HI_ERR_HDMI_INVALID_PARA);
1825 ctrl_audio_path_enable_set(HI_FALSE);
1826 ctrl_audio_reset();
1827
1828 org_reg_rate_cfg = audio_path->sample_rate;
1829 /* I2S layout */
1830 if (audio_path->channel_num == HDMI_AUDIO_FORMAT_8CH) {
1831 muti_layout = HI_TRUE;
1832 } else if (audio_path->channel_num < HDMI_AUDIO_FORMAT_8CH) {
1833 muti_layout = HI_FALSE;
1834 } else {
1835 hdmi_warn("error audio channel number:%u\n", audio_path->channel_num);
1836 }
1837 ctrl_audio_path_layout_set(muti_layout);
1838
1839 /* i2s ctrl */
1840 i2s_ctrl.in_bit_length = ctrl_audio_bit_reg_get(audio_path->sample_bit);
1841 ctrl_audio_i2s_ctrl_set(&i2s_ctrl);
1842
1843 /* i2s status */
1844 i2s_status.clk_accuracy = HDMI_AUDIO_CLK_ACCURACY_LEVEL2;
1845 i2s_status.samp_rate = ctrl_i2s_rate_reg_get(org_reg_rate_cfg);
1846 i2s_status.org_rate = ctrl_i2s_rate_org_reg_get(audio_path->sample_rate);
1847 i2s_status.out_bit_length = ctrl_audio_bit_reg_get(audio_path->sample_bit);
1848 ctrl_audio_i2s_status_set(&i2s_status);
1849
1850 fifo_ctrl.hbra_mask = HDMI_AUDIO_HBRA_MASK_NONE;
1851 ctrl_audio_fifo_ctrl_set(&fifo_ctrl);
1852
1853 /* CTS & N value */
1854 ctrl_audio_path_cts_value_set(HI_FALSE);
1855 n_value = hal_hdmi_n_value_get(audio_path->sample_rate, audio_path->pixel_clk);
1856 ctrl_audio_path_n_value_set(n_value);
1857
1858 cts_value = hal_hdmi_cts_value_get(audio_path->sample_rate, audio_path->pixel_clk);
1859 hdmi_info("\n fs=%u,bit=%u,intf=%u,tmds=%u\n"
1860 "reference N=%u,real N=%u,reference cts=%u,real_cts=%u\n",
1861 audio_path->sample_rate, audio_path->sample_bit, audio_path->sound_intf, audio_path->pixel_clk,
1862 n_value, ctrl_audio_path_n_value_get(), cts_value, ctrl_audio_path_cts_value_get());
1863
1864 /* enable */
1865 ctrl_audio_i2s_enable_set(HI_TRUE);
1866 ctrl_audio_spdif_enable_set(spdif_enable);
1867 ctrl_audio_hbra_enable_set(hbra_enable); /* when spdif, it must false */
1868
1869 return HI_SUCCESS;
1870 }
1871
hal_hdmi_ctrl_audio_path_get(hdmi_device_id hdmi,ctrl_audio_status * audio_stat)1872 hi_s32 hal_hdmi_ctrl_audio_path_get(hdmi_device_id hdmi, ctrl_audio_status *audio_stat)
1873 {
1874 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1875 hdmi_audio_path *audio_path = HI_NULL;
1876
1877 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1878 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1879 hdmi_if_null_return(audio_stat, HI_FAILURE);
1880
1881 audio_path = &ctrl_info->audio_path;
1882 hdmi_if_null_return(audio_path, HI_FAILURE);
1883
1884 if (ctrl_audio_spdif_enable_get()) {
1885 audio_stat->sound_intf = HDMI_AUDIO_INTF_SPDIF;
1886 } else if (ctrl_audio_hbra_enable_get()) {
1887 audio_stat->sound_intf = HDMI_AUDIO_INTF_HBRA;
1888 } else if (ctrl_audio_i2s_enable_get()) {
1889 audio_stat->sound_intf = HDMI_AUDIO_INTF_I2S;
1890 } else {
1891 audio_stat->sound_intf = HDMI_AUDIO_INTF_BUTT;
1892 }
1893
1894 audio_stat->enable_audio = ctrl_audio_path_enable_get();
1895 audio_stat->audio_mute = ctrl_audio_mute_get();
1896 audio_stat->sample_bit = ctrl_audio_bit_value_get(HI_FALSE);
1897 audio_stat->sample_rate = ctrl_i2s_rate_value_get();
1898 audio_stat->channel_num = ctrl_audio_path_layout_get() ? HDMI_AUDIO_FORMAT_8CH : HDMI_AUDIO_FORMAT_2CH;
1899 audio_stat->ref_cts = hal_hdmi_cts_value_get(audio_path->sample_rate, audio_path->pixel_clk);
1900 audio_stat->reg_cts = ctrl_audio_path_cts_value_get();
1901 audio_stat->ref_n = hal_hdmi_n_value_get(audio_path->sample_rate, audio_path->pixel_clk);
1902 audio_stat->reg_n = ctrl_audio_path_n_value_get();
1903
1904 return HI_SUCCESS;
1905 }
1906
hal_hdmi_ctrl_video_path_get(hdmi_device_id hdmi,ctrl_video_status * video_stat)1907 hi_void hal_hdmi_ctrl_video_path_get(hdmi_device_id hdmi, ctrl_video_status *video_stat)
1908 {
1909 hi_s32 ret;
1910 hi_bool enable_gcp = HI_FALSE;
1911 hi_bool enable_dither = HI_FALSE;
1912 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1913
1914 hdmi_if_null_return_void(video_stat);
1915 hdmi_if_null_return_void(ctrl_info);
1916 hdmi_if_false_return_void(ctrl_info->init);
1917
1918 ret = ctrl_timming_decect_get(&video_stat->timing);
1919 ret += ctrl_video_path_polarity_get(&video_stat->out_hv_sync_pol);
1920 ctrl_video_path_color_space_get(&video_stat->in_color_space, &video_stat->out_color_space);
1921 ret += ctrl_video_path_dither_get(&enable_dither, &video_stat->dither_mode);
1922 ret += ctrl_video_path_colormetry_get(&video_stat->in_colormetry, &video_stat->out_colormetry);
1923 ret += ctrl_video_path_quantization_get(&video_stat->in_quantization, &video_stat->out_quantization);
1924 ret += ctrl_video_path_deep_clr_get(&enable_gcp, &video_stat->out_deep_color);
1925 video_stat->csc_enable = ctrl_video_color_csc_get();
1926
1927 if (!enable_gcp) {
1928 video_stat->out_deep_color = HDMI_DEEP_COLOR_OFF;
1929 }
1930
1931 switch (video_stat->dither_mode) {
1932 case HDMI_VIDEO_DITHER_12_10:
1933 case HDMI_VIDEO_DITHER_12_8:
1934 video_stat->in_deep_color = HDMI_DEEP_COLOR_36BIT;
1935 break;
1936 case HDMI_VIDEO_DITHER_10_8:
1937 video_stat->in_deep_color = HDMI_DEEP_COLOR_30BIT;
1938 break;
1939 default:
1940 video_stat->in_deep_color = video_stat->out_deep_color;
1941 break;
1942 }
1943
1944 video_stat->y422_enable = ctrl_video_color_dwsm_hori_get();
1945 video_stat->y420_enable = ctrl_video_color_ycbcr420_get();
1946
1947 return;
1948 }
1949
hal_hdmi_ctrl_tmds_mode_get(hdmi_device_id hdmi,hdmi_tmds_mode * tmds_mode)1950 hi_s32 hal_hdmi_ctrl_tmds_mode_get(hdmi_device_id hdmi, hdmi_tmds_mode *tmds_mode)
1951 {
1952 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1953
1954 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1955 hdmi_if_null_return(tmds_mode, HI_FAILURE);
1956 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1957
1958 return ctrl_tmds_mode_get(tmds_mode);
1959 }
1960
hal_hdmi_ctrl_infoframe_en_get(hdmi_device_id hdmi,hdmi_infoframe_id infoframe_id,hi_bool * enable)1961 hi_s32 hal_hdmi_ctrl_infoframe_en_get(hdmi_device_id hdmi, hdmi_infoframe_id infoframe_id, hi_bool *enable)
1962 {
1963 hi_s32 ret;
1964 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1965
1966 hdmi_if_null_return(ctrl_info, HI_FAILURE);
1967 hdmi_if_null_return(enable, HI_FAILURE);
1968 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
1969
1970 switch (infoframe_id) {
1971 case HDMI_INFOFRAME_TYPE_VENDOR:
1972 ret = ctrl_vendor_infoframe_en_get(enable);
1973 break;
1974 case HDMI_INFOFRAME_TYPE_AVI:
1975 ret = ctrl_avi_infoframe_en_get(enable);
1976 break;
1977 case HDMI_INFOFRAME_TYPE_AUDIO:
1978 ret = ctrl_audio_infoframe_en_get(enable);
1979 break;
1980 case HDMI_INFOFRAME_TYPE_GBD:
1981 ret = ctrl_gbd_infoframe_en_get(enable);
1982 break;
1983 case HDMI_INFOFRAME_TYPE_DRM:
1984 ret = ctrl_drm_infoframe_en_get(enable);
1985 break;
1986 default:
1987 hdmi_warn("un-support infoframe type:%u!\n", infoframe_id);
1988 ret = HI_FAILURE;
1989 break;
1990 }
1991
1992 return ret;
1993 }
1994
hal_hdmi_ctrl_infoframe_data_get(hdmi_device_id hdmi,hdmi_infoframe_id infoframe_id,hi_u8 * if_data)1995 hi_s32 hal_hdmi_ctrl_infoframe_data_get(hdmi_device_id hdmi, hdmi_infoframe_id infoframe_id, hi_u8 *if_data)
1996 {
1997 hi_s32 ret;
1998 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
1999
2000 hdmi_if_null_return(ctrl_info, HI_FAILURE);
2001 hdmi_if_null_return(if_data, HI_FAILURE);
2002 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
2003
2004 switch (infoframe_id) {
2005 case HDMI_INFOFRAME_TYPE_VENDOR:
2006 ret = ctrl_vendor_infoframe_data_get(if_data);
2007 break;
2008 case HDMI_INFOFRAME_TYPE_AVI:
2009 ret = ctrl_avi_infoframe_data_get(if_data);
2010 break;
2011 case HDMI_INFOFRAME_TYPE_AUDIO:
2012 ret = ctrl_audio_infoframe_data_get(if_data);
2013 break;
2014 case HDMI_INFOFRAME_TYPE_GBD:
2015 ret = ctrl_gbd_infoframe_data_get(if_data);
2016 break;
2017 case HDMI_INFOFRAME_TYPE_DRM:
2018 ret = ctrl_drm_infoframe_data_get(if_data);
2019 break;
2020 default:
2021 hdmi_warn("un-support infoframe type:%u!\n", infoframe_id);
2022 ret = HI_FAILURE;
2023 break;
2024 }
2025
2026 return ret;
2027 }
2028
2029 #ifdef HDMI_HDR_SUPPORT
hal_hdmi_ctrl_hdr_timer_set(hdmi_device_id hdmi,const hdmi_timer_config * hdr_timer_cfg)2030 hi_s32 hal_hdmi_ctrl_hdr_timer_set(hdmi_device_id hdmi, const hdmi_timer_config *hdr_timer_cfg)
2031 {
2032 hi_u32 i;
2033 ctrl_hdr_timer *hdr_timer = HI_NULL;
2034 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
2035
2036 hdmi_if_null_return(hdr_timer_cfg, HI_FAILURE);
2037 hdmi_if_null_return(ctrl_info, HI_FAILURE);
2038 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
2039
2040 if (hdr_timer_cfg->timer_type >= HDMI_TIMER_TYPE_BUTT) {
2041 hdmi_warn("invalid timer type=%u,fail\n", hdr_timer_cfg->timer_type);
2042 return HI_FAILURE;
2043 }
2044
2045 for (i = 0; i < HDMI_TIMER_TYPE_BUTT; i++) {
2046 hdr_timer = &ctrl_info->hdr_timer[i];
2047 if ((hdr_timer_cfg->timer_start) && (!hdr_timer->enable)) {
2048 hdr_timer->enable = HI_TRUE;
2049 hdr_timer->timer_type = hdr_timer_cfg->timer_type;
2050 hdr_timer->start_time = hal_hdmi_mach_ms_get();
2051 hdr_timer->time_length = hdr_timer_cfg->time;
2052 break;
2053 } else if (hdr_timer_cfg->timer_type == hdr_timer->timer_type) {
2054 (hi_void)memset_s(hdr_timer, sizeof(ctrl_hdr_timer), 0, sizeof(ctrl_hdr_timer));
2055 break;
2056 }
2057 }
2058
2059 if (i >= HDMI_TIMER_TYPE_BUTT) {
2060 hdmi_warn("can't find valid timer type=%u, fail\n", hdr_timer_cfg->timer_type);
2061 return HI_FAILURE;
2062 }
2063
2064 return HI_SUCCESS;
2065 }
2066 #endif
2067
hal_hdmi_ctrl_hpd_rsen_get(hdmi_device_id hdmi,hdmi_hpd_rsen * hpd_rsen)2068 hi_s32 hal_hdmi_ctrl_hpd_rsen_get(hdmi_device_id hdmi, hdmi_hpd_rsen *hpd_rsen)
2069 {
2070 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
2071
2072 hdmi_if_null_return(ctrl_info, HI_FAILURE);
2073 hdmi_if_null_return(hpd_rsen, HI_FAILURE);
2074 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
2075
2076 hpd_rsen->rsen_on = ctrl_rsen_get();
2077 hpd_rsen->hpd_on = ctrl_hpd_get();
2078
2079 return HI_SUCCESS;
2080 }
2081
hal_hdmi_ctrl_dither_dbg_set(hdmi_device_id hdmi,hdmi_video_dither dither_mode)2082 hi_void hal_hdmi_ctrl_dither_dbg_set(hdmi_device_id hdmi, hdmi_video_dither dither_mode)
2083 {
2084 hi_bool enable_dither = HI_FALSE;
2085
2086 hi_unused(hdmi);
2087 if (dither_mode >= HDMI_VIDEO_DITHER_DISABLE) {
2088 enable_dither = HI_FALSE;
2089 dither_mode = HDMI_VIDEO_DITHER_DISABLE;
2090 } else {
2091 enable_dither = HI_TRUE;
2092 }
2093 ctrl_video_path_dither_set(enable_dither, dither_mode);
2094
2095 return;
2096 }
2097
hal_hdmi_ctrl_tmds_stable_get(hdmi_device_id hdmi,hi_bool * stable)2098 hi_s32 hal_hdmi_ctrl_tmds_stable_get(hdmi_device_id hdmi, hi_bool *stable)
2099 {
2100 hdmi_ctrl_info *ctrl_info = ctrl_info_ptr_get(hdmi);
2101
2102 hdmi_if_null_return(stable, HI_FAILURE);
2103 hdmi_if_null_return(ctrl_info, HI_FAILURE);
2104 hdmi_if_false_return(ctrl_info->init, HI_FAILURE);
2105
2106 *stable = hdmi_reg_pclk2tclk_stable_get() ? HI_TRUE : HI_FALSE;
2107 return HI_SUCCESS;
2108 }
2109
2110