1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18 #include "hdmi_reg_audio_path.h"
19 #include "hdmi_product_define.h"
20
21 volatile hdmi_reg_audio_path *g_audio_path_regs = NULL;
22
hdmi_reg_audio_path_regs_init(hi_char * addr)23 int hdmi_reg_audio_path_regs_init(hi_char *addr)
24 {
25 g_audio_path_regs = (volatile hdmi_reg_audio_path *)(addr + (HDMI_TX_BASE_ADDR_AUDIO));
26 return HI_SUCCESS;
27 }
28
hdmi_reg_audio_path_regs_deinit(void)29 int hdmi_reg_audio_path_regs_deinit(void)
30 {
31 if (g_audio_path_regs != HI_NULL) {
32 g_audio_path_regs = HI_NULL;
33 }
34 return HI_SUCCESS;
35 }
36
hdmi_reg_aud_spdif_en_set(unsigned int aud_spdif_en)37 int hdmi_reg_aud_spdif_en_set(unsigned int aud_spdif_en)
38 {
39 hi_u32 *reg_addr = NULL;
40 tx_audio_ctrl ctrl;
41
42 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32);
43 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
44 ctrl.bits.aud_spdif_en = aud_spdif_en;
45 hdmi_tx_reg_write(reg_addr, ctrl.u32);
46
47 return HI_SUCCESS;
48 }
49
hdmi_reg_aud_i2s_en_set(unsigned int aud_i2s_en)50 int hdmi_reg_aud_i2s_en_set(unsigned int aud_i2s_en)
51 {
52 hi_u32 *reg_addr = NULL;
53 tx_audio_ctrl ctrl;
54
55 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32);
56 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
57 ctrl.bits.aud_i2s_en = aud_i2s_en;
58 hdmi_tx_reg_write(reg_addr, ctrl.u32);
59
60 return HI_SUCCESS;
61 }
62
hdmi_reg_aud_layout_set(unsigned int aud_layout)63 int hdmi_reg_aud_layout_set(unsigned int aud_layout)
64 {
65 hi_u32 *reg_addr = NULL;
66 tx_audio_ctrl ctrl;
67
68 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32);
69 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
70 ctrl.bits.aud_layout = aud_layout;
71 hdmi_tx_reg_write(reg_addr, ctrl.u32);
72
73 return HI_SUCCESS;
74 }
75
hdmi_reg_aud_mute_en_set(unsigned int aud_mute_en)76 int hdmi_reg_aud_mute_en_set(unsigned int aud_mute_en)
77 {
78 hi_u32 *reg_addr = NULL;
79 tx_audio_ctrl ctrl;
80
81 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32);
82 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
83 ctrl.bits.aud_mute_en = aud_mute_en;
84 hdmi_tx_reg_write(reg_addr, ctrl.u32);
85
86 return HI_SUCCESS;
87 }
88
hdmi_reg_aud_in_en_set(unsigned int aud_in_en)89 int hdmi_reg_aud_in_en_set(unsigned int aud_in_en)
90 {
91 hi_u32 *reg_addr = NULL;
92 tx_audio_ctrl ctrl;
93
94 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32);
95 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
96 ctrl.bits.aud_in_en = aud_in_en;
97 hdmi_tx_reg_write(reg_addr, ctrl.u32);
98
99 return HI_SUCCESS;
100 }
101
hdmi_reg_i2s_ch_swap_set(unsigned int i2s_ch_swap)102 int hdmi_reg_i2s_ch_swap_set(unsigned int i2s_ch_swap)
103 {
104 hi_u32 *reg_addr = NULL;
105 audio_i2s_ctrl aud_i2s_ctrl;
106
107 reg_addr = (hi_u32 *)&(g_audio_path_regs->i2s_ctl.u32);
108 aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
109 aud_i2s_ctrl.bits.i2s_ch_swap = i2s_ch_swap;
110 hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32);
111
112 return HI_SUCCESS;
113 }
114
hdmi_reg_i2s_length_set(unsigned int i2s_length)115 int hdmi_reg_i2s_length_set(unsigned int i2s_length)
116 {
117 hi_u32 *reg_addr = NULL;
118 audio_i2s_ctrl aud_i2s_ctrl;
119
120 reg_addr = (hi_u32 *)&(g_audio_path_regs->i2s_ctl.u32);
121 aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
122 aud_i2s_ctrl.bits.i2s_length = i2s_length;
123 hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32);
124
125 return HI_SUCCESS;
126 }
127
hdmi_reg_i2s_vbit_set(unsigned int i2s_vbit)128 int hdmi_reg_i2s_vbit_set(unsigned int i2s_vbit)
129 {
130 hi_u32 *reg_addr = NULL;
131 audio_i2s_ctrl aud_i2s_ctrl;
132
133 reg_addr = (hi_u32 *)&(g_audio_path_regs->i2s_ctl.u32);
134 aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
135 aud_i2s_ctrl.bits.i2s_vbit = i2s_vbit;
136 hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32);
137
138 return HI_SUCCESS;
139 }
140
hdmi_reg_i2s_data_dir_set(unsigned int i2s_data_dir)141 int hdmi_reg_i2s_data_dir_set(unsigned int i2s_data_dir)
142 {
143 hi_u32 *reg_addr = NULL;
144 audio_i2s_ctrl aud_i2s_ctrl;
145
146 reg_addr = (hi_u32 *)&(g_audio_path_regs->i2s_ctl.u32);
147 aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
148 aud_i2s_ctrl.bits.i2s_data_dir = i2s_data_dir;
149 hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32);
150
151 return HI_SUCCESS;
152 }
153
hdmi_reg_i2s_justify_set(unsigned int i2s_justify)154 int hdmi_reg_i2s_justify_set(unsigned int i2s_justify)
155 {
156 hi_u32 *reg_addr = NULL;
157 audio_i2s_ctrl aud_i2s_ctrl;
158
159 reg_addr = (hi_u32 *)&(g_audio_path_regs->i2s_ctl.u32);
160 aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
161 aud_i2s_ctrl.bits.i2s_justify = i2s_justify;
162 hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32);
163
164 return HI_SUCCESS;
165 }
166
hdmi_reg_i2s_ws_polarity_set(unsigned int i2s_ws_polarity)167 int hdmi_reg_i2s_ws_polarity_set(unsigned int i2s_ws_polarity)
168 {
169 hi_u32 *reg_addr = NULL;
170 audio_i2s_ctrl aud_i2s_ctrl;
171
172 reg_addr = (hi_u32 *)&(g_audio_path_regs->i2s_ctl.u32);
173 aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
174 aud_i2s_ctrl.bits.i2s_ws_polarity = i2s_ws_polarity;
175 hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32);
176
177 return HI_SUCCESS;
178 }
179
hdmi_reg_i2s_1st_shift_set(unsigned int i2s_1st_shift)180 int hdmi_reg_i2s_1st_shift_set(unsigned int i2s_1st_shift)
181 {
182 hi_u32 *reg_addr = NULL;
183 audio_i2s_ctrl aud_i2s_ctrl;
184
185 reg_addr = (hi_u32 *)&(g_audio_path_regs->i2s_ctl.u32);
186 aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
187 aud_i2s_ctrl.bits.i2s_1st_shift = i2s_1st_shift;
188 hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32);
189
190 return HI_SUCCESS;
191 }
192
hdmi_reg_i2s_hbra_on_set(unsigned int i2s_hbra_on)193 int hdmi_reg_i2s_hbra_on_set(unsigned int i2s_hbra_on)
194 {
195 hi_u32 *reg_addr = NULL;
196 audio_i2s_ctrl aud_i2s_ctrl;
197
198 reg_addr = (hi_u32 *)&(g_audio_path_regs->i2s_ctl.u32);
199 aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
200 aud_i2s_ctrl.bits.i2s_hbra_on = i2s_hbra_on;
201 hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32);
202
203 return HI_SUCCESS;
204 }
205
hdmi_reg_chst_byte3_clock_accuracy_set(unsigned int chst_byte3_clock_accuracy)206 int hdmi_reg_chst_byte3_clock_accuracy_set(unsigned int chst_byte3_clock_accuracy)
207 {
208 hi_u32 *reg_addr = NULL;
209 audio_chst_cfg0 aud_chst_cfg0;
210
211 reg_addr = (hi_u32 *)&(g_audio_path_regs->chst_cfg0.u32);
212 aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr);
213 aud_chst_cfg0.bits.chst_byte3_clock_accuracy = chst_byte3_clock_accuracy;
214 hdmi_tx_reg_write(reg_addr, aud_chst_cfg0.u32);
215
216 return HI_SUCCESS;
217 }
218
hdmi_reg_chst_byte3_fs_set(unsigned int chst_byte3_fs)219 int hdmi_reg_chst_byte3_fs_set(unsigned int chst_byte3_fs)
220 {
221 hi_u32 *reg_addr = NULL;
222 audio_chst_cfg0 aud_chst_cfg0;
223
224 reg_addr = (hi_u32 *)&(g_audio_path_regs->chst_cfg0.u32);
225 aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr);
226 aud_chst_cfg0.bits.chst_byte3_fs = chst_byte3_fs;
227 hdmi_tx_reg_write(reg_addr, aud_chst_cfg0.u32);
228
229 return HI_SUCCESS;
230 }
231
hdmi_reg_chst_byte0_bset(unsigned int chst_byte0_b)232 int hdmi_reg_chst_byte0_bset(unsigned int chst_byte0_b)
233 {
234 hi_u32 *reg_addr = NULL;
235 audio_chst_cfg0 aud_chst_cfg0;
236
237 reg_addr = (hi_u32 *)&(g_audio_path_regs->chst_cfg0.u32);
238 aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr);
239 aud_chst_cfg0.bits.chst_byte0_b = chst_byte0_b;
240 hdmi_tx_reg_write(reg_addr, aud_chst_cfg0.u32);
241
242 return HI_SUCCESS;
243 }
244
hdmi_reg_chst_byte0_aset(unsigned int chst_byte0_a)245 int hdmi_reg_chst_byte0_aset(unsigned int chst_byte0_a)
246 {
247 hi_u32 *reg_addr = NULL;
248 audio_chst_cfg0 aud_chst_cfg0;
249
250 reg_addr = (hi_u32 *)&(g_audio_path_regs->chst_cfg0.u32);
251 aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr);
252 aud_chst_cfg0.bits.chst_byte0_a = chst_byte0_a;
253 hdmi_tx_reg_write(reg_addr, aud_chst_cfg0.u32);
254
255 return HI_SUCCESS;
256 }
257
hdmi_reg_chst_byte4_org_fs_set(unsigned int chst_byte4_org_fs)258 int hdmi_reg_chst_byte4_org_fs_set(unsigned int chst_byte4_org_fs)
259 {
260 hi_u32 *reg_addr = NULL;
261 audio_chst_cfg1 aud_chst_cfg1;
262
263 reg_addr = (hi_u32 *)&(g_audio_path_regs->chst_cfg1.u32);
264 aud_chst_cfg1.u32 = hdmi_tx_reg_read(reg_addr);
265 aud_chst_cfg1.bits.chst_byte4_org_fs = chst_byte4_org_fs;
266 hdmi_tx_reg_write(reg_addr, aud_chst_cfg1.u32);
267
268 return HI_SUCCESS;
269 }
270
hdmi_reg_chst_byte4_length_set(unsigned int chst_byte4_length)271 int hdmi_reg_chst_byte4_length_set(unsigned int chst_byte4_length)
272 {
273 hi_u32 *reg_addr = NULL;
274 audio_chst_cfg1 aud_chst_cfg1;
275
276 reg_addr = (hi_u32 *)&(g_audio_path_regs->chst_cfg1.u32);
277 aud_chst_cfg1.u32 = hdmi_tx_reg_read(reg_addr);
278 aud_chst_cfg1.bits.chst_byte4_length = chst_byte4_length;
279 hdmi_tx_reg_write(reg_addr, aud_chst_cfg1.u32);
280
281 return HI_SUCCESS;
282 }
283
hdmi_reg_aud_fifo_hbr_mask_set(unsigned int aud_fifo_hbr_mask)284 int hdmi_reg_aud_fifo_hbr_mask_set(unsigned int aud_fifo_hbr_mask)
285 {
286 hi_u32 *reg_addr = NULL;
287 audio_fifo_ctrl aud_fifo_ctrl;
288
289 reg_addr = (hi_u32 *)&(g_audio_path_regs->fifo_ctl.u32);
290 aud_fifo_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
291 aud_fifo_ctrl.bits.aud_fifo_hbr_mask = aud_fifo_hbr_mask;
292 hdmi_tx_reg_write(reg_addr, aud_fifo_ctrl.u32);
293
294 return HI_SUCCESS;
295 }
296
hdmi_reg_aud_fifo_test_set(unsigned int aud_fifo_test)297 int hdmi_reg_aud_fifo_test_set(unsigned int aud_fifo_test)
298 {
299 hi_u32 *reg_addr = NULL;
300 audio_fifo_ctrl aud_fifo_ctrl;
301
302 reg_addr = (hi_u32 *)&(g_audio_path_regs->fifo_ctl.u32);
303 aud_fifo_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
304 aud_fifo_ctrl.bits.aud_fifo_test = aud_fifo_test;
305 hdmi_tx_reg_write(reg_addr, aud_fifo_ctrl.u32);
306
307 return HI_SUCCESS;
308 }
309
hdmi_reg_acr_cts_hw_sw_sel_set(unsigned int acr_cts_hw_sw_sel)310 int hdmi_reg_acr_cts_hw_sw_sel_set(unsigned int acr_cts_hw_sw_sel)
311 {
312 hi_u32 *reg_addr = NULL;
313 audio_acr_ctrl aud_acr_ctrl;
314
315 reg_addr = (hi_u32 *)&(g_audio_path_regs->acr_ctl.u32);
316 aud_acr_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
317 aud_acr_ctrl.bits.acr_cts_hw_sw_sel = acr_cts_hw_sw_sel;
318 hdmi_tx_reg_write(reg_addr, aud_acr_ctrl.u32);
319
320 return HI_SUCCESS;
321 }
322
hdmi_reg_acr_n_val_sw_set(unsigned int acr_n_value)323 int hdmi_reg_acr_n_val_sw_set(unsigned int acr_n_value)
324 {
325 hi_u32 *reg_addr = NULL;
326 acr_n_val_sw acr_n_val;
327
328 reg_addr = (hi_u32 *)&(g_audio_path_regs->acr_sw_n.u32);
329 acr_n_val.u32 = hdmi_tx_reg_read(reg_addr);
330 acr_n_val.bits.acr_n_val_sw = acr_n_value;
331 hdmi_tx_reg_write(reg_addr, acr_n_val.u32);
332
333 return HI_SUCCESS;
334 }
335
hdmi_reg_aud_spdif_en_get(hi_void)336 hi_u32 hdmi_reg_aud_spdif_en_get(hi_void)
337 {
338 hi_u32 *reg_addr = NULL;
339 tx_audio_ctrl ctrl;
340
341 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32);
342 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
343 return ctrl.bits.aud_spdif_en;
344 }
345
hdmi_reg_aud_i2s_en_get(hi_void)346 hi_u32 hdmi_reg_aud_i2s_en_get(hi_void)
347 {
348 hi_u32 *reg_addr = NULL;
349 tx_audio_ctrl ctrl;
350
351 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32);
352 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
353 return ctrl.bits.aud_i2s_en;
354 }
355
hdmi_reg_aud_layout_get(hi_void)356 hi_u32 hdmi_reg_aud_layout_get(hi_void)
357 {
358 hi_u32 *reg_addr = NULL;
359 tx_audio_ctrl ctrl;
360
361 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32);
362 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
363 return ctrl.bits.aud_layout;
364 }
365
hdmi_reg_aud_mute_en_get(hi_void)366 hi_u32 hdmi_reg_aud_mute_en_get(hi_void)
367 {
368 hi_u32 *reg_addr = NULL;
369 tx_audio_ctrl ctrl;
370
371 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32);
372 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
373 return ctrl.bits.aud_mute_en;
374 }
375
hdmi_reg_aud_in_en_get(hi_void)376 hi_u32 hdmi_reg_aud_in_en_get(hi_void)
377 {
378 hi_u32 *reg_addr = NULL;
379 tx_audio_ctrl ctrl;
380
381 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32);
382 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
383 return ctrl.bits.aud_in_en;
384 }
385
hdmi_reg_i2s_hbra_on_get(hi_void)386 hi_u32 hdmi_reg_i2s_hbra_on_get(hi_void)
387 {
388 hi_u32 *reg_addr = NULL;
389 audio_i2s_ctrl aud_i2s_ctrl;
390
391 reg_addr = (hi_u32 *)&(g_audio_path_regs->i2s_ctl.u32);
392 aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
393 return aud_i2s_ctrl.bits.i2s_hbra_on;
394 }
395
hdmi_reg_chst_byte3_fs_get(hi_void)396 hi_u32 hdmi_reg_chst_byte3_fs_get(hi_void)
397 {
398 hi_u32 *reg_addr = NULL;
399 audio_chst_cfg0 aud_chst_cfg0;
400
401 reg_addr = (hi_u32 *)&(g_audio_path_regs->chst_cfg0.u32);
402 aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr);
403 return aud_chst_cfg0.bits.chst_byte3_fs;
404 }
405
hdmi_reg_chst_byte4_org_fs_get(hi_void)406 hi_u32 hdmi_reg_chst_byte4_org_fs_get(hi_void)
407 {
408 hi_u32 *reg_addr = NULL;
409 audio_chst_cfg1 aud_chst_cfg1;
410
411 reg_addr = (hi_u32 *)&(g_audio_path_regs->chst_cfg1.u32);
412 aud_chst_cfg1.u32 = hdmi_tx_reg_read(reg_addr);
413 return aud_chst_cfg1.bits.chst_byte4_org_fs;
414 }
415
hdmi_reg_chst_byte4_length_get(hi_void)416 hi_u32 hdmi_reg_chst_byte4_length_get(hi_void)
417 {
418 hi_u32 *reg_addr = NULL;
419 audio_chst_cfg1 aud_chst_cfg1;
420
421 reg_addr = (hi_u32 *)&(g_audio_path_regs->chst_cfg1.u32);
422 aud_chst_cfg1.u32 = hdmi_tx_reg_read(reg_addr);
423 return aud_chst_cfg1.bits.chst_byte4_length;
424 }
425
hdmi_reg_aud_spdif_fs_get(hi_void)426 hi_u32 hdmi_reg_aud_spdif_fs_get(hi_void)
427 {
428 hi_u32 *reg_addr = NULL;
429 tx_audio_state state;
430
431 reg_addr = (hi_u32 *)&(g_audio_path_regs->aud_state.u32);
432 state.u32 = hdmi_tx_reg_read(reg_addr);
433 return state.bits.aud_spdif_fs;
434 }
435
hdmi_reg_aud_length_get(hi_void)436 hi_u32 hdmi_reg_aud_length_get(hi_void)
437 {
438 hi_u32 *reg_addr = NULL;
439 tx_audio_state state;
440
441 reg_addr = (hi_u32 *)&(g_audio_path_regs->aud_state.u32);
442 state.u32 = hdmi_tx_reg_read(reg_addr);
443 return state.bits.aud_length;
444 }
445
hdmi_reg_acr_cts_hw_sw_sel_get(hi_void)446 hi_u32 hdmi_reg_acr_cts_hw_sw_sel_get(hi_void)
447 {
448 hi_u32 *reg_addr = NULL;
449 audio_acr_ctrl aud_acr_ctrl;
450
451 reg_addr = (hi_u32 *)&(g_audio_path_regs->acr_ctl.u32);
452 aud_acr_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
453 return aud_acr_ctrl.bits.acr_cts_hw_sw_sel;
454 }
455
hdmi_reg_acr_n_val_sw_get(hi_void)456 hi_u32 hdmi_reg_acr_n_val_sw_get(hi_void)
457 {
458 hi_u32 *reg_addr = NULL;
459 acr_n_val_sw acr_n_val;
460
461 reg_addr = (hi_u32 *)&(g_audio_path_regs->acr_sw_n.u32);
462 acr_n_val.u32 = hdmi_tx_reg_read(reg_addr);
463 return acr_n_val.bits.acr_n_val_sw;
464 }
465
hdmi_reg_acr_cts_val_sw_get(hi_void)466 hi_u32 hdmi_reg_acr_cts_val_sw_get(hi_void)
467 {
468 hi_u32 *reg_addr = NULL;
469 acr_cts_val_sw acr_cts_val;
470
471 reg_addr = (hi_u32 *)&(g_audio_path_regs->acr_sw_cts.u32);
472 acr_cts_val.u32 = hdmi_tx_reg_read(reg_addr);
473 return acr_cts_val.bits.acr_cts_val_sw;
474 }
475
hdmi_reg_acr_cts_val_hw_get(hi_void)476 hi_u32 hdmi_reg_acr_cts_val_hw_get(hi_void)
477 {
478 hi_u32 *reg_addr = NULL;
479 acr_cts_val_hw acr_cts_val;
480
481 reg_addr = (hi_u32 *)&(g_audio_path_regs->acr_hw_cts.u32);
482 acr_cts_val.u32 = hdmi_tx_reg_read(reg_addr);
483 return acr_cts_val.bits.acr_cts_val_hw;
484 }
485
486