1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Broadcom PCIE 4 * Software-specific definitions shared between device and host side 5 * Explains the shared area between host and dongle 6 * 7 * Copyright (C) 1999-2019, Broadcom. 8 * 9 * Unless you and Broadcom execute a separate written software license 10 * agreement governing use of this software, this software is licensed to you 11 * under the terms of the GNU General Public License version 2 (the "GPL"), 12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 13 * following added to such license: 14 * 15 * As a special exception, the copyright holders of this software give you 16 * permission to link this software with independent modules, and to copy and 17 * distribute the resulting executable under terms of your choice, provided that 18 * you also meet, for each linked independent module, the terms and conditions of 19 * the license of that module. An independent module is a module which is not 20 * derived from this software. The special exception does not apply to any 21 * modifications of the software. 22 * 23 * Notwithstanding the above, under no circumstances may you combine this 24 * software in any way with any other Broadcom software provided under a license 25 * other than the GPL, without Broadcom's express prior written consent. 26 * 27 * 28 * <<Broadcom-WL-IPTag/Open:>> 29 * 30 * $Id: bcmpcie.h 821465 2019-05-23 19:50:00Z $ 31 */ 32 33 #ifndef _bcmpcie_h_ 34 #define _bcmpcie_h_ 35 36 #include <typedefs.h> 37 38 #define ADDR_64(x) (x.addr) 39 #define HIGH_ADDR_32(x) ((uint32) (((sh_addr_t) x).high_addr)) 40 #define LOW_ADDR_32(x) ((uint32) (((sh_addr_t) x).low_addr)) 41 42 typedef struct { 43 uint32 low_addr; 44 uint32 high_addr; 45 } sh_addr_t; 46 47 /* May be overridden by 43xxxxx-roml.mk */ 48 #if !defined(BCMPCIE_MAX_TX_FLOWS) 49 #define BCMPCIE_MAX_TX_FLOWS 40 50 #endif /* ! BCMPCIE_MAX_TX_FLOWS */ 51 52 #define PCIE_SHARED_VERSION_7 0x00007 53 #define PCIE_SHARED_VERSION_6 0x00006 /* rev6 is compatible with rev 5 */ 54 #define PCIE_SHARED_VERSION_5 0x00005 /* rev6 is compatible with rev 5 */ 55 /** 56 * Feature flags enabled in dongle. Advertised by dongle to DHD via the PCIe Shared structure that 57 * is located in device memory. 58 */ 59 #define PCIE_SHARED_VERSION_MASK 0x000FF 60 #define PCIE_SHARED_ASSERT_BUILT 0x00100 61 #define PCIE_SHARED_ASSERT 0x00200 62 #define PCIE_SHARED_TRAP 0x00400 63 #define PCIE_SHARED_IN_BRPT 0x00800 64 #define PCIE_SHARED_SET_BRPT 0x01000 65 #define PCIE_SHARED_PENDING_BRPT 0x02000 66 /* BCMPCIE_SUPPORT_TX_PUSH_RING 0x04000 obsolete */ 67 #define PCIE_SHARED_EVT_SEQNUM 0x08000 68 #define PCIE_SHARED_DMA_INDEX 0x10000 69 70 /** 71 * There are host types where a device interrupt can 'race ahead' of data written by the device into 72 * host memory. The dongle can avoid this condition using a variety of techniques (read barrier, 73 * using PCIe Message Signalled Interrupts, or by using the PCIE_DMA_INDEX feature). Unfortunately 74 * these techniques have drawbacks on router platforms. For these platforms, it was decided to not 75 * avoid the condition, but to detect the condition instead and act on it. 76 * D2H M2M DMA Complete Sync mechanism: Modulo-253-SeqNum or XORCSUM 77 */ 78 #define PCIE_SHARED_D2H_SYNC_SEQNUM 0x20000 79 #define PCIE_SHARED_D2H_SYNC_XORCSUM 0x40000 80 #define PCIE_SHARED_D2H_SYNC_MODE_MASK \ 81 (PCIE_SHARED_D2H_SYNC_SEQNUM | PCIE_SHARED_D2H_SYNC_XORCSUM) 82 #define PCIE_SHARED_IDLE_FLOW_RING 0x80000 83 #define PCIE_SHARED_2BYTE_INDICES 0x100000 84 85 #define PCIE_SHARED_FAST_DELETE_RING 0x00000020 /* Fast Delete Ring */ 86 #define PCIE_SHARED_EVENT_BUF_POOL_MAX 0x000000c0 /* event buffer pool max bits */ 87 #define PCIE_SHARED_EVENT_BUF_POOL_MAX_POS 6 /* event buffer pool max bit position */ 88 89 /* dongle supports fatal buf log collection */ 90 #define PCIE_SHARED_FATAL_LOGBUG_VALID 0x200000 91 92 /* Implicit DMA with corerev 19 and after */ 93 #define PCIE_SHARED_IDMA 0x400000 94 95 /* MSI support */ 96 #define PCIE_SHARED_D2H_MSI_MULTI_MSG 0x800000 97 98 /* IFRM with corerev 19 and after */ 99 #define PCIE_SHARED_IFRM 0x1000000 100 101 /** 102 * From Rev6 and above, suspend/resume can be done using two handshake methods. 103 * 1. Using ctrl post/ctrl cmpl messages (Default rev6) 104 * 2. Using Mailbox data (old method as used in rev5) 105 * This shared flag indicates whether to overide rev6 default method and use mailbox for 106 * suspend/resume. 107 */ 108 #define PCIE_SHARED_USE_MAILBOX 0x2000000 109 110 /* Firmware compiled for mfgbuild purposes */ 111 #define PCIE_SHARED_MFGBUILD_FW 0x4000000 112 113 /* Firmware could use DB0 value as host timestamp */ 114 #define PCIE_SHARED_TIMESTAMP_DB0 0x8000000 115 /* Firmware could use Hostready (IPC rev7) */ 116 #define PCIE_SHARED_HOSTRDY_SUPPORT 0x10000000 117 118 /* When set, Firmwar does not support OOB Device Wake based DS protocol */ 119 #define PCIE_SHARED_NO_OOB_DW 0x20000000 120 121 /* When set, Firmwar supports Inband DS protocol */ 122 #define PCIE_SHARED_INBAND_DS 0x40000000 123 124 /* use DAR registers */ 125 #define PCIE_SHARED_DAR 0x80000000 126 127 /** 128 * Following are the shared2 flags. All bits in flags have been used. A flags2 129 * field got added and the definition for these flags come here: 130 */ 131 /* WAR: D11 txstatus through unused status field of PCIe completion header */ 132 #define PCIE_SHARED2_EXTENDED_TRAP_DATA 0x00000001 /* using flags2 in shared area */ 133 #define PCIE_SHARED2_TXSTATUS_METADATA 0x00000002 134 #define PCIE_SHARED2_BT_LOGGING 0x00000004 /* BT logging support */ 135 #define PCIE_SHARED2_SNAPSHOT_UPLOAD 0x00000008 /* BT/WLAN snapshot upload support */ 136 #define PCIE_SHARED2_SUBMIT_COUNT_WAR 0x00000010 /* submission count WAR */ 137 #define PCIE_SHARED2_FAST_DELETE_RING 0x00000020 /* Fast Delete ring support */ 138 #define PCIE_SHARED2_EVTBUF_MAX_MASK 0x000000C0 /* 0:32, 1:64, 2:128, 3: 256 */ 139 140 /* using flags2 to indicate firmware support added to reuse timesync to update PKT txstatus */ 141 #define PCIE_SHARED2_PKT_TX_STATUS 0x00000100 142 #define PCIE_SHARED2_FW_SMALL_MEMDUMP 0x00000200 /* FW small memdump */ 143 #define PCIE_SHARED2_FW_HC_ON_TRAP 0x00000400 144 #define PCIE_SHARED2_HSCB 0x00000800 /* Host SCB support */ 145 146 #define PCIE_SHARED2_EDL_RING 0x00001000 /* Support Enhanced Debug Lane */ 147 #define PCIE_SHARED2_DEBUG_BUF_DEST 0x00002000 /* debug buf dest support */ 148 #define PCIE_SHARED2_PCIE_ENUM_RESET_FLR 0x00004000 /* BT producer index reset WAR */ 149 #define PCIE_SHARED2_PKT_TIMESTAMP 0x00008000 /* Timestamp in packet */ 150 151 #define PCIE_SHARED2_HP2P 0x00010000u /* HP2P feature */ 152 #define PCIE_SHARED2_HWA 0x00020000u /* HWA feature */ 153 #define PCIE_SHARED2_TRAP_ON_HOST_DB7 0x00040000u /* can take a trap on DB7 from host */ 154 155 #define PCIE_SHARED2_DURATION_SCALE 0x00100000u 156 157 #define PCIE_SHARED2_D2H_D11_TX_STATUS 0x40000000 158 #define PCIE_SHARED2_H2D_D11_TX_STATUS 0x80000000 159 160 #define PCIE_SHARED_D2H_MAGIC 0xFEDCBA09 161 #define PCIE_SHARED_H2D_MAGIC 0x12345678 162 163 typedef uint16 pcie_hwa_db_index_t; /* 16 bit HWA index (IPC Rev 7) */ 164 #define PCIE_HWA_DB_INDEX_SZ (2u) /* 2 bytes sizeof(pcie_hwa_db_index_t) */ 165 166 /** 167 * Message rings convey messages between host and device. They are unidirectional, and are located 168 * in host memory. 169 * 170 * This is the minimal set of message rings, known as 'common message rings': 171 */ 172 #define BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT 0 173 #define BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT 1 174 #define BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE 2 175 #define BCMPCIE_D2H_MSGRING_TX_COMPLETE 3 176 #define BCMPCIE_D2H_MSGRING_RX_COMPLETE 4 177 #define BCMPCIE_COMMON_MSGRING_MAX_ID 4 178 179 #define BCMPCIE_H2D_COMMON_MSGRINGS 2 180 #define BCMPCIE_D2H_COMMON_MSGRINGS 3 181 #define BCMPCIE_COMMON_MSGRINGS 5 182 183 #define BCMPCIE_H2D_MSGRINGS(max_tx_flows) \ 184 (BCMPCIE_H2D_COMMON_MSGRINGS + (max_tx_flows)) 185 186 /* different ring types */ 187 #define BCMPCIE_H2D_RING_TYPE_CTRL_SUBMIT 0x1 188 #define BCMPCIE_H2D_RING_TYPE_TXFLOW_RING 0x2 189 #define BCMPCIE_H2D_RING_TYPE_RXBUFPOST 0x3 190 #define BCMPCIE_H2D_RING_TYPE_TXSUBMIT 0x4 191 #define BCMPCIE_H2D_RING_TYPE_DBGBUF_SUBMIT 0x5 192 #define BCMPCIE_H2D_RING_TYPE_BTLOG_SUBMIT 0x6 193 194 #define BCMPCIE_D2H_RING_TYPE_CTRL_CPL 0x1 195 #define BCMPCIE_D2H_RING_TYPE_TX_CPL 0x2 196 #define BCMPCIE_D2H_RING_TYPE_RX_CPL 0x3 197 #define BCMPCIE_D2H_RING_TYPE_DBGBUF_CPL 0x4 198 #define BCMPCIE_D2H_RING_TYPE_AC_RX_COMPLETE 0x5 199 #define BCMPCIE_D2H_RING_TYPE_BTLOG_CPL 0x6 200 #define BCMPCIE_D2H_RING_TYPE_EDL 0x7 201 #define BCMPCIE_D2H_RING_TYPE_HPP_TX_CPL 0x8 202 #define BCMPCIE_D2H_RING_TYPE_HPP_RX_CPL 0x9 203 204 /** 205 * H2D and D2H, WR and RD index, are maintained in the following arrays: 206 * - Array of all H2D WR Indices 207 * - Array of all H2D RD Indices 208 * - Array of all D2H WR Indices 209 * - Array of all D2H RD Indices 210 * 211 * The offset of the WR or RD indexes (for common rings) in these arrays are 212 * listed below. Arrays ARE NOT indexed by a ring's id. 213 * 214 * D2H common rings WR and RD index start from 0, even though their ringids 215 * start from BCMPCIE_H2D_COMMON_MSGRINGS 216 */ 217 218 #define BCMPCIE_H2D_RING_IDX(h2d_ring_id) (h2d_ring_id) 219 220 enum h2dring_idx { 221 /* H2D common rings */ 222 BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT_IDX = 223 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT), 224 BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT_IDX = 225 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT), 226 227 /* First TxPost's WR or RD index starts after all H2D common rings */ 228 BCMPCIE_H2D_MSGRING_TXFLOW_IDX_START = 229 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_COMMON_MSGRINGS) 230 }; 231 232 #define BCMPCIE_D2H_RING_IDX(d2h_ring_id) \ 233 ((d2h_ring_id) - BCMPCIE_H2D_COMMON_MSGRINGS) 234 235 enum d2hring_idx { 236 /* D2H Common Rings */ 237 BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE_IDX = 238 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE), 239 BCMPCIE_D2H_MSGRING_TX_COMPLETE_IDX = 240 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_TX_COMPLETE), 241 BCMPCIE_D2H_MSGRING_RX_COMPLETE_IDX = 242 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_RX_COMPLETE) 243 }; 244 245 /** 246 * Macros for managing arrays of RD WR indices: 247 * rw_index_sz: 248 * - in dongle, rw_index_sz is known at compile time 249 * - in host/DHD, rw_index_sz is derived from advertized pci_shared flags 250 * 251 * ring_idx: See h2dring_idx and d2hring_idx 252 */ 253 254 /** Offset of a RD or WR index in H2D or D2H indices array */ 255 #define BCMPCIE_RW_INDEX_OFFSET(rw_index_sz, ring_idx) \ 256 ((rw_index_sz) * (ring_idx)) 257 258 /** Fetch the address of RD or WR index in H2D or D2H indices array */ 259 #define BCMPCIE_RW_INDEX_ADDR(indices_array_base, rw_index_sz, ring_idx) \ 260 (void *)((uint32)(indices_array_base) + \ 261 BCMPCIE_RW_INDEX_OFFSET((rw_index_sz), (ring_idx))) 262 263 /** H2D DMA Indices array size: given max flow rings */ 264 #define BCMPCIE_H2D_RW_INDEX_ARRAY_SZ(rw_index_sz, max_tx_flows) \ 265 ((rw_index_sz) * BCMPCIE_H2D_MSGRINGS(max_tx_flows)) 266 267 /** D2H DMA Indices array size */ 268 #define BCMPCIE_D2H_RW_INDEX_ARRAY_SZ(rw_index_sz) \ 269 ((rw_index_sz) * BCMPCIE_D2H_COMMON_MSGRINGS) 270 271 /** 272 * This type is used by a 'message buffer' (which is a FIFO for messages). Message buffers are used 273 * for host<->device communication and are instantiated on both sides. ring_mem_t is instantiated 274 * both in host as well as device memory. 275 */ 276 typedef struct ring_mem { 277 uint16 idx; /* ring id */ 278 uint8 type; 279 uint8 rsvd; 280 uint16 max_item; /* Max number of items in flow ring */ 281 uint16 len_items; /* Items are fixed size. Length in bytes of one item */ 282 sh_addr_t base_addr; /* 64 bits address, either in host or device memory */ 283 } ring_mem_t; 284 285 /** 286 * Per flow ring, information is maintained in device memory, eg at what address the ringmem and 287 * ringstate are located. The flow ring itself can be instantiated in either host or device memory. 288 * 289 * Perhaps this type should be renamed to make clear that it resides in device memory only. 290 */ 291 typedef struct ring_info { 292 uint32 ringmem_ptr; /* ring mem location in dongle memory */ 293 294 /* Following arrays are indexed using h2dring_idx and d2hring_idx, and not 295 * by a ringid. 296 */ 297 298 /* 32bit ptr to arrays of WR or RD indices for all rings in dongle memory */ 299 uint32 h2d_w_idx_ptr; /* Array of all H2D ring's WR indices */ 300 uint32 h2d_r_idx_ptr; /* Array of all H2D ring's RD indices */ 301 uint32 d2h_w_idx_ptr; /* Array of all D2H ring's WR indices */ 302 uint32 d2h_r_idx_ptr; /* Array of all D2H ring's RD indices */ 303 304 /* PCIE_DMA_INDEX feature: Dongle uses mem2mem DMA to sync arrays in host. 305 * Host may directly fetch WR and RD indices from these host-side arrays. 306 * 307 * 64bit ptr to arrays of WR or RD indices for all rings in host memory. 308 */ 309 sh_addr_t h2d_w_idx_hostaddr; /* Array of all H2D ring's WR indices */ 310 sh_addr_t h2d_r_idx_hostaddr; /* Array of all H2D ring's RD indices */ 311 sh_addr_t d2h_w_idx_hostaddr; /* Array of all D2H ring's WR indices */ 312 sh_addr_t d2h_r_idx_hostaddr; /* Array of all D2H ring's RD indices */ 313 314 uint16 max_tx_flowrings; /* maximum number of H2D rings: common + flow */ 315 uint16 max_submission_queues; /* maximum number of H2D rings: common + flow */ 316 uint16 max_completion_rings; /* maximum number of H2D rings: common + flow */ 317 uint16 max_vdevs; /* max number of virtual interfaces supported */ 318 319 sh_addr_t ifrm_w_idx_hostaddr; /* Array of all H2D ring's WR indices for IFRM */ 320 321 /* 32bit ptr to arrays of HWA DB indices for all rings in dongle memory */ 322 uint32 h2d_hwa_db_idx_ptr; /* Array of all H2D ring's HWA DB indices */ 323 uint32 d2h_hwa_db_idx_ptr; /* Array of all D2H ring's HWA DB indices */ 324 325 } ring_info_t; 326 327 /** 328 * A structure located in TCM that is shared between host and device, primarily used during 329 * initialization. 330 */ 331 typedef struct { 332 /** shared area version captured at flags 7:0 */ 333 uint32 flags; 334 335 uint32 trap_addr; 336 uint32 assert_exp_addr; 337 uint32 assert_file_addr; 338 uint32 assert_line; 339 uint32 console_addr; /**< Address of hnd_cons_t */ 340 341 uint32 msgtrace_addr; 342 343 uint32 fwid; 344 345 /* Used for debug/flow control */ 346 uint16 total_lfrag_pkt_cnt; 347 uint16 max_host_rxbufs; /* rsvd in spec */ 348 349 uint32 dma_rxoffset; /* rsvd in spec */ 350 351 /** these will be used for sleep request/ack, d3 req/ack */ 352 uint32 h2d_mb_data_ptr; 353 uint32 d2h_mb_data_ptr; 354 355 /* information pertinent to host IPC/msgbuf channels */ 356 /** location in the TCM memory which has the ring_info */ 357 uint32 rings_info_ptr; 358 359 /** block of host memory for the scratch buffer */ 360 uint32 host_dma_scratch_buffer_len; 361 sh_addr_t host_dma_scratch_buffer; 362 363 /* location in host memory for scb host offload structures */ 364 sh_addr_t host_scb_addr; 365 uint32 host_scb_size; 366 367 /* anonymous union for overloading fields in structure */ 368 union { 369 uint32 buzz_dbg_ptr; /* BUZZZ state format strings and trace buffer */ 370 struct { 371 /* Host provided trap buffer length in words */ 372 uint16 device_trap_debug_buffer_len; 373 uint16 rsvd2; 374 }; 375 }; 376 377 /* rev6 compatible changes */ 378 uint32 flags2; 379 uint32 host_cap; 380 381 /* location in the host address space to write trap indication. 382 * At this point for the current rev of the spec, firmware will 383 * support only indications to 32 bit host addresses. 384 * This essentially is device_trap_debug_buffer_addr 385 */ 386 sh_addr_t host_trap_addr; 387 388 /* location for host fatal error log buffer start address */ 389 uint32 device_fatal_logbuf_start; 390 391 /* location in host memory for offloaded modules */ 392 sh_addr_t hoffload_addr; 393 uint32 flags3; 394 uint32 host_cap2; 395 uint32 host_cap3; 396 } pciedev_shared_t; 397 398 /* Device F/W provides the following access function: 399 * pciedev_shared_t *hnd_get_pciedev_shared(void); 400 */ 401 402 /* host capabilities */ 403 #define HOSTCAP_PCIEAPI_VERSION_MASK 0x000000FF 404 #define HOSTCAP_H2D_VALID_PHASE 0x00000100 405 #define HOSTCAP_H2D_ENABLE_TRAP_ON_BADPHASE 0x00000200 406 #define HOSTCAP_H2D_ENABLE_HOSTRDY 0x00000400 407 #define HOSTCAP_DB0_TIMESTAMP 0x00000800 408 #define HOSTCAP_DS_NO_OOB_DW 0x00001000 409 #define HOSTCAP_DS_INBAND_DW 0x00002000 410 #define HOSTCAP_H2D_IDMA 0x00004000 411 #define HOSTCAP_H2D_IFRM 0x00008000 412 #define HOSTCAP_H2D_DAR 0x00010000 413 #define HOSTCAP_EXTENDED_TRAP_DATA 0x00020000 414 #define HOSTCAP_TXSTATUS_METADATA 0x00040000 415 #define HOSTCAP_BT_LOGGING 0x00080000 416 #define HOSTCAP_SNAPSHOT_UPLOAD 0x00100000 417 #define HOSTCAP_FAST_DELETE_RING 0x00200000 418 #define HOSTCAP_PKT_TXSTATUS 0x00400000 419 #define HOSTCAP_UR_FW_NO_TRAP 0x00800000 /* Don't trap on UR */ 420 #define HOSTCAP_HSCB 0x02000000 421 /* Host support for extended device trap debug buffer */ 422 #define HOSTCAP_EXT_TRAP_DBGBUF 0x04000000 423 /* Host support for enhanced debug lane */ 424 #define HOSTCAP_EDL_RING 0x10000000 425 #define HOSTCAP_PKT_TIMESTAMP 0x20000000 426 #define HOSTCAP_PKT_HP2P 0x40000000 427 #define HOSTCAP_HWA 0x80000000 428 #define HOSTCAP2_DURATION_SCALE_MASK 0x0000003Fu 429 430 /* extended trap debug buffer allocation sizes. Note that this buffer can be used for 431 * other trap related purposes also. 432 */ 433 #define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MIN (64u * 1024u) 434 #define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MAX (256u * 1024u) 435 436 /** 437 * Mailboxes notify a remote party that an event took place, using interrupts. They use hardware 438 * support. 439 */ 440 441 /* H2D mail box Data */ 442 #define H2D_HOST_D3_INFORM 0x00000001 443 #define H2D_HOST_DS_ACK 0x00000002 444 #define H2D_HOST_DS_NAK 0x00000004 445 #define H2D_HOST_D0_INFORM_IN_USE 0x00000008 446 #define H2D_HOST_D0_INFORM 0x00000010 447 #define H2DMB_DS_ACTIVE 0x00000020 448 #define H2DMB_DS_DEVICE_WAKE 0x00000040 449 #define H2D_HOST_IDMA_INITED 0x00000080 450 #define H2D_HOST_ACK_NOINT 0x00010000 /* d2h_ack interrupt ignore */ 451 #define H2D_HOST_CONS_INT 0x80000000 /**< h2d int for console cmds */ 452 #define H2D_FW_TRAP 0x20000000 /**< h2d force TRAP */ 453 #define H2DMB_DS_HOST_SLEEP_INFORM H2D_HOST_D3_INFORM 454 #define H2DMB_DS_DEVICE_SLEEP_ACK H2D_HOST_DS_ACK 455 #define H2DMB_DS_DEVICE_SLEEP_NAK H2D_HOST_DS_NAK 456 #define H2DMB_D0_INFORM_IN_USE H2D_HOST_D0_INFORM_IN_USE 457 #define H2DMB_D0_INFORM H2D_HOST_D0_INFORM 458 #define H2DMB_FW_TRAP H2D_FW_TRAP 459 #define H2DMB_HOST_CONS_INT H2D_HOST_CONS_INT 460 #define H2DMB_DS_DEVICE_WAKE_ASSERT H2DMB_DS_DEVICE_WAKE 461 #define H2DMB_DS_DEVICE_WAKE_DEASSERT H2DMB_DS_ACTIVE 462 463 /* D2H mail box Data */ 464 #define D2H_DEV_D3_ACK 0x00000001 465 #define D2H_DEV_DS_ENTER_REQ 0x00000002 466 #define D2H_DEV_DS_EXIT_NOTE 0x00000004 467 #define D2HMB_DS_HOST_SLEEP_EXIT_ACK 0x00000008 468 #define D2H_DEV_IDMA_INITED 0x00000010 469 #define D2HMB_DS_HOST_SLEEP_ACK D2H_DEV_D3_ACK 470 #define D2HMB_DS_DEVICE_SLEEP_ENTER_REQ D2H_DEV_DS_ENTER_REQ 471 #define D2HMB_DS_DEVICE_SLEEP_EXIT D2H_DEV_DS_EXIT_NOTE 472 473 #define D2H_DEV_MB_MASK (D2H_DEV_D3_ACK | D2H_DEV_DS_ENTER_REQ | \ 474 D2H_DEV_DS_EXIT_NOTE | D2H_DEV_IDMA_INITED) 475 #define D2H_DEV_MB_INVALIDATED(x) ((!x) || (x & ~D2H_DEV_MB_MASK)) 476 477 /* trap data codes */ 478 #define D2H_DEV_FWHALT 0x10000000 479 #define D2H_DEV_EXT_TRAP_DATA 0x20000000 480 #define D2H_DEV_TRAP_IN_TRAP 0x40000000 481 #define D2H_DEV_TRAP_HOSTDB 0x80000000 /* trap as set by host DB */ 482 #define D2H_DEV_TRAP_DUE_TO_BT 0x01000000 483 /* Indicates trap due to HMAP violation */ 484 #define D2H_DEV_TRAP_DUE_TO_HMAP 0x02000000 485 /* Indicates whether HMAP violation was Write */ 486 #define D2H_DEV_TRAP_HMAP_WRITE 0x04000000 487 #define D2H_DEV_TRAP_PING_HOST_FAILURE 0x08000000 488 #define D2H_FWTRAP_MASK 0x0000001F /* Adding maskbits for TRAP information */ 489 490 #define D2HMB_FWHALT D2H_DEV_FWHALT 491 #define D2HMB_TRAP_IN_TRAP D2H_DEV_TRAP_IN_TRAP 492 #define D2HMB_EXT_TRAP_DATA D2H_DEV_EXT_TRAP_DATA 493 494 /* Size of Extended Trap data Buffer */ 495 #define BCMPCIE_EXT_TRAP_DATA_MAXLEN 4096 496 497 /** These macro's operate on type 'inuse_lclbuf_pool_t' and are used by firmware only */ 498 #define PREVTXP(i, d) (((i) == 0) ? ((d) - 1) : ((i) - 1)) 499 #define NEXTTXP(i, d) ((((i)+1) >= (d)) ? 0 : ((i)+1)) 500 #define NEXTNTXP(i, n, d) ((((i)+(n)) >= (d)) ? 0 : ((i)+(n))) 501 #define NTXPACTIVE(r, w, d) (((r) <= (w)) ? ((w)-(r)) : ((d)-(r)+(w))) 502 #define NTXPAVAIL(r, w, d) (((d) - NTXPACTIVE((r), (w), (d))) > 1) 503 504 /* Function can be used to notify host of FW halt */ 505 #define READ_AVAIL_SPACE(w, r, d) ((w >= r) ? (uint32)(w - r) : (uint32)(d - r)) 506 #define WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d) ((w >= r) ? (d - w) : (r - w)) 507 #define WRITE_SPACE_AVAIL(r, w, d) (d - (NTXPACTIVE(r, w, d)) - 1) 508 #define CHECK_WRITE_SPACE(r, w, d) ((r) > (w)) ? \ 509 (uint32)((r) - (w) - 1) : ((r) == 0 || (w) == 0) ? \ 510 (uint32)((d) - (w) - 1) : (uint32)((d) - (w)) 511 512 #define CHECK_NOWRITE_SPACE(r, w, d) \ 513 (((uint32)(r) == (uint32)((w) + 1)) || (((r) == 0) && ((w) == ((d) - 1)))) 514 515 #define WRT_PEND(x) ((x)->wr_pending) 516 #define DNGL_RING_WPTR(msgbuf) (*((msgbuf)->tcm_rs_w_ptr)) /**< advanced by producer */ 517 #define BCMMSGBUF_RING_SET_W_PTR(msgbuf, a) (DNGL_RING_WPTR(msgbuf) = (a)) 518 519 #define DNGL_RING_RPTR(msgbuf) (*((msgbuf)->tcm_rs_r_ptr)) /**< advanced by consumer */ 520 #define BCMMSGBUF_RING_SET_R_PTR(msgbuf, a) (DNGL_RING_RPTR(msgbuf) = (a)) 521 522 #define MODULO_RING_IDX(x, y) ((x) % (y)->bitmap_size) 523 524 #define RING_READ_PTR(x) ((x)->ringstate->r_offset) 525 #define RING_WRITE_PTR(x) ((x)->ringstate->w_offset) 526 #define RING_START_PTR(x) ((x)->ringmem->base_addr.low_addr) 527 #define RING_MAX_ITEM(x) ((x)->ringmem->max_item) 528 #define RING_LEN_ITEMS(x) ((x)->ringmem->len_items) 529 #define HOST_RING_BASE(x) ((x)->dma_buf.va) 530 #define HOST_RING_END(x) ((uint8 *)HOST_RING_BASE((x)) + \ 531 ((RING_MAX_ITEM((x))-1)*RING_LEN_ITEMS((x)))) 532 533 /* Trap types copied in the pciedev_shared.trap_addr */ 534 #define FW_INITIATED_TRAP_TYPE (0x1 << 7) 535 #define HEALTHCHECK_NODS_TRAP_TYPE (0x1 << 6) 536 537 #endif /* _bcmpcie_h_ */ 538