1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Include file private to the SOC Interconnect support files. 4 * 5 * Copyright (C) 1999-2019, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * 26 * <<Broadcom-WL-IPTag/Open:>> 27 * 28 * $Id: siutils_priv.h 795345 2018-12-18 16:52:03Z $ 29 */ 30 31 #ifndef _siutils_priv_h_ 32 #define _siutils_priv_h_ 33 34 #if defined(SI_ERROR_ENFORCE) 35 #define SI_ERROR(args) printf args 36 #else 37 #define SI_ERROR(args) 38 #endif // endif 39 40 #if defined(ENABLE_CORECAPTURE) 41 42 #define SI_PRINT(args) osl_wificc_logDebug args 43 44 #else 45 46 #define SI_PRINT(args) printf args 47 48 #endif /* ENABLE_CORECAPTURE */ 49 50 #define SI_MSG(args) 51 52 #ifdef BCMDBG_SI 53 #define SI_VMSG(args) printf args 54 #else 55 #define SI_VMSG(args) 56 #endif // endif 57 58 #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) 59 60 typedef uint32 (*si_intrsoff_t)(void *intr_arg); 61 typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg); 62 typedef bool (*si_intrsenabled_t)(void *intr_arg); 63 64 #define SI_GPIO_MAX 16 65 66 typedef struct gci_gpio_item { 67 void *arg; 68 uint8 gci_gpio; 69 uint8 status; 70 gci_gpio_handler_t handler; 71 struct gci_gpio_item *next; 72 } gci_gpio_item_t; 73 74 #define AI_SLAVE_WRAPPER 0 75 #define AI_MASTER_WRAPPER 1 76 77 typedef struct axi_wrapper { 78 uint32 mfg; 79 uint32 cid; 80 uint32 rev; 81 uint32 wrapper_type; 82 uint32 wrapper_addr; 83 uint32 wrapper_size; 84 } axi_wrapper_t; 85 86 #define SI_MAX_AXI_WRAPPERS 32 87 #define AI_REG_READ_TIMEOUT 300 /* in msec */ 88 89 /* for some combo chips, BT side accesses chipcommon->0x190, as a 16 byte addr */ 90 /* register at 0x19C doesn't exist, so error is logged at the slave wrapper */ 91 #define BT_CC_SPROM_BADREG_LO 0x18000190 92 #define BT_CC_SPROM_BADREG_SIZE 4 93 #define BT_CC_SPROM_BADREG_HI 0 94 #define BCM4350_BT_AXI_ID 6 95 #define BCM4345_BT_AXI_ID 6 96 #define BCM4349_BT_AXI_ID 5 97 #define BCM4364_BT_AXI_ID 5 98 99 /* for BT logging and memory dump, ignore failed access to BT memory */ 100 #define BCM4347_BT_ADDR_HI 0 101 #define BCM4347_BT_ADDR_LO 0x19000000 /* BT address space */ 102 #define BCM4347_BT_SIZE 0x01000000 /* BT address space size */ 103 #define BCM4347_UNUSED_AXI_ID 0xffffffff 104 #define BCM4347_CC_AXI_ID 0 105 #define BCM4347_PCIE_AXI_ID 1 106 107 typedef struct si_cores_info { 108 volatile void *regs[SI_MAXCORES]; /* other regs va */ 109 110 uint coreid[SI_MAXCORES]; /**< id of each core */ 111 uint32 coresba[SI_MAXCORES]; /**< backplane address of each core */ 112 void *regs2[SI_MAXCORES]; /**< va of each core second register set (usbh20) */ 113 uint32 coresba2[SI_MAXCORES]; /**< address of each core second register set (usbh20) */ 114 uint32 coresba_size[SI_MAXCORES]; /**< backplane address space size */ 115 uint32 coresba2_size[SI_MAXCORES]; /**< second address space size */ 116 117 void *wrappers[SI_MAXCORES]; /**< other cores wrapper va */ 118 uint32 wrapba[SI_MAXCORES]; /**< address of controlling wrapper */ 119 120 void *wrappers2[SI_MAXCORES]; /**< other cores wrapper va */ 121 uint32 wrapba2[SI_MAXCORES]; /**< address of controlling wrapper */ 122 123 void *wrappers3[SI_MAXCORES]; /**< other cores wrapper va */ 124 uint32 wrapba3[SI_MAXCORES]; /**< address of controlling wrapper */ 125 126 uint32 cia[SI_MAXCORES]; /**< erom cia entry for each core */ 127 uint32 cib[SI_MAXCORES]; /**< erom cia entry for each core */ 128 129 uint32 csp2ba[SI_MAXCORES]; /**< Second slave port base addr 0 */ 130 uint32 csp2ba_size[SI_MAXCORES]; /**< Second slave port addr space size */ 131 } si_cores_info_t; 132 133 /** misc si info needed by some of the routines */ 134 typedef struct si_info { 135 struct si_pub pub; /**< back plane public state (must be first field) */ 136 137 void *osh; /**< osl os handle */ 138 void *sdh; /**< bcmsdh handle */ 139 140 uint dev_coreid; /**< the core provides driver functions */ 141 void *intr_arg; /**< interrupt callback function arg */ 142 si_intrsoff_t intrsoff_fn; /**< turns chip interrupts off */ 143 si_intrsrestore_t intrsrestore_fn; /**< restore chip interrupts */ 144 si_intrsenabled_t intrsenabled_fn; /**< check if interrupts are enabled */ 145 146 void *pch; /**< PCI/E core handle */ 147 148 bool memseg; /**< flag to toggle MEM_SEG register */ 149 150 char *vars; 151 uint varsz; 152 153 volatile void *curmap; /* current regs va */ 154 155 uint curidx; /**< current core index */ 156 uint numcores; /**< # discovered cores */ 157 158 void *curwrap; /**< current wrapper va */ 159 160 uint32 oob_router; /**< oob router registers for axi */ 161 uint32 oob_router1; /**< oob router registers for axi */ 162 163 si_cores_info_t *cores_info; 164 gci_gpio_item_t *gci_gpio_head; /**< gci gpio interrupts head */ 165 uint chipnew; /**< new chip number */ 166 uint second_bar0win; /**< Backplane region */ 167 uint num_br; /**< # discovered bridges */ 168 uint32 br_wrapba[SI_MAXBR]; /**< address of bridge controlling wrapper */ 169 uint32 xtalfreq; 170 uint32 openloop_dco_code; /**< OPEN loop calibration dco code */ 171 uint8 spurmode; 172 bool device_removed; 173 uint axi_num_wrappers; 174 axi_wrapper_t * axi_wrapper; 175 uint8 device_wake_opt; /* device_wake GPIO number */ 176 uint8 lhl_ps_mode; 177 } si_info_t; 178 179 #define SI_INFO(sih) ((si_info_t *)(uintptr)sih) 180 181 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \ 182 ISALIGNED((x), SI_CORE_SIZE)) 183 #define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE)) 184 #define BADCOREADDR 0 185 #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES) 186 #define NOREV -1 /**< Invalid rev */ 187 188 #define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 189 ((si)->pub.buscoretype == PCI_CORE_ID)) 190 191 #define PCIE_GEN1(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 192 ((si)->pub.buscoretype == PCIE_CORE_ID)) 193 194 #define PCIE_GEN2(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 195 ((si)->pub.buscoretype == PCIE2_CORE_ID)) 196 197 #define PCIE(si) (PCIE_GEN1(si) || PCIE_GEN2(si)) 198 199 #define PCMCIA(si) ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE)) 200 201 /** Newer chips can access PCI/PCIE and CC core without requiring to change PCI BAR0 WIN */ 202 #define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13))) 203 204 #define CCREGS_FAST(si) \ 205 (((si)->curmap == NULL) ? NULL : \ 206 ((volatile char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET)) 207 #define PCIEREGS(si) (((volatile char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET)) 208 209 /* 210 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/ 211 * after core switching to avoid invalid register accesss inside ISR. 212 */ 213 #define INTR_OFF(si, intr_val) \ 214 if ((si)->intrsoff_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \ 215 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); } 216 #define INTR_RESTORE(si, intr_val) \ 217 if ((si)->intrsrestore_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \ 218 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); } 219 220 /* dynamic clock control defines */ 221 #define LPOMINFREQ 25000 /**< low power oscillator min */ 222 #define LPOMAXFREQ 43000 /**< low power oscillator max */ 223 #define XTALMINFREQ 19800000 /**< 20 MHz - 1% */ 224 #define XTALMAXFREQ 20200000 /**< 20 MHz + 1% */ 225 #define PCIMINFREQ 25000000 /**< 25 MHz */ 226 #define PCIMAXFREQ 34000000 /**< 33 MHz + fudge */ 227 228 #define ILP_DIV_5MHZ 0 /**< ILP = 5 MHz */ 229 #define ILP_DIV_1MHZ 4 /**< ILP = 1 MHz */ 230 231 /* GPIO Based LED powersave defines */ 232 #define DEFAULT_GPIO_ONTIME 10 /**< Default: 10% on */ 233 #define DEFAULT_GPIO_OFFTIME 90 /**< Default: 10% on */ 234 235 #ifndef DEFAULT_GPIOTIMERVAL 236 #define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME) 237 #endif // endif 238 239 /* Silicon Backplane externs */ 240 extern void sb_scan(si_t *sih, volatile void *regs, uint devid); 241 extern uint sb_coreid(si_t *sih); 242 extern uint sb_intflag(si_t *sih); 243 extern uint sb_flag(si_t *sih); 244 extern void sb_setint(si_t *sih, int siflag); 245 extern uint sb_corevendor(si_t *sih); 246 extern uint sb_corerev(si_t *sih); 247 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 248 extern volatile uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff); 249 extern bool sb_iscoreup(si_t *sih); 250 extern volatile void *sb_setcoreidx(si_t *sih, uint coreidx); 251 extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val); 252 extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 253 extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val); 254 extern void sb_commit(si_t *sih); 255 extern uint32 sb_base(uint32 admatch); 256 extern uint32 sb_size(uint32 admatch); 257 extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 258 extern void sb_core_disable(si_t *sih, uint32 bits); 259 extern uint32 sb_addrspace(si_t *sih, uint asidx); 260 extern uint32 sb_addrspacesize(si_t *sih, uint asidx); 261 extern int sb_numaddrspaces(si_t *sih); 262 263 extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx); 264 265 extern bool sb_taclear(si_t *sih, bool details); 266 267 #if defined(BCMDBG_PHYDUMP) 268 extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b); 269 #endif // endif 270 271 /* Wake-on-wireless-LAN (WOWL) */ 272 extern bool sb_pci_pmecap(si_t *sih); 273 struct osl_info; 274 extern bool sb_pci_fastpmecap(struct osl_info *osh); 275 extern bool sb_pci_pmeclr(si_t *sih); 276 extern void sb_pci_pmeen(si_t *sih); 277 extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset); 278 279 /* AMBA Interconnect exported externs */ 280 extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, 281 void *sdh, char **vars, uint *varsz); 282 extern si_t *ai_kattach(osl_t *osh); 283 extern void ai_scan(si_t *sih, void *regs, uint devid); 284 285 extern uint ai_flag(si_t *sih); 286 extern uint ai_flag_alt(si_t *sih); 287 extern void ai_setint(si_t *sih, int siflag); 288 extern uint ai_coreidx(si_t *sih); 289 extern uint ai_corevendor(si_t *sih); 290 extern uint ai_corerev(si_t *sih); 291 extern uint ai_corerev_minor(si_t *sih); 292 extern volatile uint32 *ai_corereg_addr(si_t *sih, uint coreidx, uint regoff); 293 extern bool ai_iscoreup(si_t *sih); 294 extern volatile void *ai_setcoreidx(si_t *sih, uint coreidx); 295 extern volatile void *ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx); 296 extern volatile void *ai_setcoreidx_3rdwrap(si_t *sih, uint coreidx); 297 extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val); 298 extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 299 extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val); 300 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 301 extern uint ai_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 302 extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 303 extern void ai_d11rsdb_core_reset(si_t *sih, uint32 bits, 304 uint32 resetbits, void *p, volatile void *s); 305 extern void ai_core_disable(si_t *sih, uint32 bits); 306 extern void ai_d11rsdb_core_disable(const si_info_t *sii, uint32 bits, 307 aidmp_t *pmacai, aidmp_t *smacai); 308 extern int ai_numaddrspaces(si_t *sih); 309 extern uint32 ai_addrspace(si_t *sih, uint spidx, uint baidx); 310 extern uint32 ai_addrspacesize(si_t *sih, uint spidx, uint baidx); 311 extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size); 312 extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 313 extern void ai_update_backplane_timeouts(si_t *sih, bool enable, uint32 timeout, uint32 cid); 314 extern uint32 ai_clear_backplane_to(si_t *sih); 315 void ai_force_clocks(si_t *sih, uint clock_state); 316 extern uint ai_num_slaveports(si_t *sih, uint coreidx); 317 318 #ifdef BCM_BACKPLANE_TIMEOUT 319 uint32 ai_clear_backplane_to_fast(si_t *sih, void * addr); 320 #endif /* BCM_BACKPLANE_TIMEOUT */ 321 322 #if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT) 323 extern uint32 ai_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void * wrap); 324 #endif /* AXI_TIMEOUTS || BCM_BACKPLANE_TIMEOUT */ 325 326 #if defined(BCMDBG_PHYDUMP) 327 extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b); 328 #endif // endif 329 330 extern uint32 ai_wrapper_dump_buf_size(si_t *sih); 331 extern uint32 ai_wrapper_dump_binary(si_t *sih, uchar *p); 332 extern bool ai_check_enable_backplane_log(si_t *sih); 333 extern uint32 ai_wrapper_dump_last_timeout(si_t *sih, uint32 *error, uint32 *core, uint32 *ba, 334 uchar *p); 335 336 #define ub_scan(a, b, c) do {} while (0) 337 #define ub_flag(a) (0) 338 #define ub_setint(a, b) do {} while (0) 339 #define ub_coreidx(a) (0) 340 #define ub_corevendor(a) (0) 341 #define ub_corerev(a) (0) 342 #define ub_iscoreup(a) (0) 343 #define ub_setcoreidx(a, b) (0) 344 #define ub_core_cflags(a, b, c) (0) 345 #define ub_core_cflags_wo(a, b, c) do {} while (0) 346 #define ub_core_sflags(a, b, c) (0) 347 #define ub_corereg(a, b, c, d, e) (0) 348 #define ub_core_reset(a, b, c) do {} while (0) 349 #define ub_core_disable(a, b) do {} while (0) 350 #define ub_numaddrspaces(a) (0) 351 #define ub_addrspace(a, b) (0) 352 #define ub_addrspacesize(a, b) (0) 353 #define ub_view(a, b) do {} while (0) 354 #define ub_dumpregs(a, b) do {} while (0) 355 356 #endif /* _siutils_priv_h_ */ 357