1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: Provides V151 PWM register \n 16 * 17 * History: \n 18 * 2022-09-16， Create file. \n 19 */ 20 21 #ifndef HAL_PWM_V151_REGS_DEF_H 22 #define HAL_PWM_V151_REGS_DEF_H 23 24 #include <stdint.h> 25 #include "pwm_porting.h" 26 27 #ifdef __cplusplus 28 #if __cplusplus 29 extern "C" { 30 #endif /* __cplusplus */ 31 #endif /* __cplusplus */ 32 33 /** 34 * @defgroup drivers_hal_pwm_v151_regs_def PWM V151 Regs Definition 35 * @ingroup drivers_hal_pwm 36 * @{ 37 */ 38 39 #define BIT16 16 40 41 /** 42 * @brief This union represents the bit fields in the pwm_sel register. 43 * Read the register into the <i>d32</i> member then 44 * set/clear the bits using the <i>b</i> elements. 45 */ 46 typedef union pwm_sel_data { 47 uint32_t d32; /*!< Raw register data. */ 48 struct { 49 uint32_t pwm_sel_i : 16; /*!< Grouped pwm selection signals, up to ten groups, 50 each group corresponding to 10bit pwm_sel, each 51 bit corresponding to one way pwm. */ 52 uint32_t reserved16_31 : 16; 53 } b; 54 } pwm_sel_data_t; 55 56 57 /** 58 * @brief This union represents the bit fields in the pwm_startclrcnt_en register. 59 * Read the register into the <i>d32</i> member then 60 * set/clear the bits using the <i>b</i> elements. 61 */ 62 typedef union pwm_startclrcnt_en_data { 63 uint32_t d32; /*!< Raw register data. */ 64 struct { 65 uint32_t pwm_startclrcnt_en_i : 1; /*!< It will clear pwm clk cnt(internal data, invisible) & refresh 66 new cfg to pwm registers when pwm_start_i = 1. */ 67 uint32_t reserved1_31 : 31; 68 } b; 69 } pwm_startclrcnt_en_data_t; 70 71 /** 72 * @brief This union represents the bit fields in the pwm_start register. 73 * Read the register into the <i>d32</i> member then 74 * set/clear the bits using the <i>b</i> elements. 75 */ 76 typedef union pwm_start_data { 77 uint32_t d32; /*!< Raw register data. */ 78 struct { 79 uint32_t pwm_start_i : 1; /*!< pwm configuration effective register. When set to 1, 80 the previously assigned pwm-related registers take effect. 81 Each group corresponds to 1bit pwm_start. */ 82 uint32_t reserved1_31 : 31; 83 } b; 84 } pwm_start_data_t; 85 86 /** 87 * @brief This union represents the bit fields in the pwm_en register. 88 * Read the register into the <i>d32</i> member then 89 * set/clear the bits using the <i>b</i> elements. 90 */ 91 typedef union pwm_en_data { 92 uint32_t d32; /*!< Raw register data. */ 93 struct { 94 uint32_t pwm_en_j : 1; /*!< The pwm function is enabled, each pwm channel corresponds to 95 one pwm_en. 96 -0: pwm off, pwm_out output is continuously 0. 97 -1: pwm enable on. */ 98 uint32_t reserved1_31 : 31; 99 } b; 100 } pwm_en_data_t; 101 102 /** 103 * @brief This union represents the bit fields in the pwm_portity register. 104 * Read the register into the <i>d32</i> member then 105 * set/clear the bits using the <i>b</i> elements. 106 */ 107 typedef union pwm_portity_data { 108 uint32_t d32; /*!< Raw register data. */ 109 struct { 110 uint32_t pwm_portity_j : 1; /*!< Pwm output polarity configuration. 111 -0: forward polarity. 112 -1: Reverse polarity. */ 113 uint32_t reserved1_31 : 31; 114 } b; 115 } pwm_portity_data_t; 116 117 /** 118 * @brief This union represents the bit fields in the pwm_oen_cfg register. 119 * Read the register into the <i>d32</i> member then 120 * set/clear the bits using the <i>b</i> elements. 121 */ 122 typedef union pwm_oen_cfg_data { 123 uint32_t d32; /*!< Raw register data. */ 124 struct { 125 uint32_t pwm_oen_cfg_j : 1; /*!< Pwm invalid level high resistance enable configuration. 126 -0: Invalid level follows polarity and other configurations. 127 -1: Invalid level Pwm output high resistance. */ 128 uint32_t reserved1_31 : 31; 129 } b; 130 } pwm_oen_cfg_data_t; 131 132 /** 133 * @brief This union represents the bit fields in the pwm_offset_low register. 134 * Read the register into the <i>d32</i> member then 135 * set/clear the bits using the <i>b</i> elements. 136 */ 137 typedef union pwm_offset_l_data { 138 uint32_t d32; /*!< Raw register data. */ 139 struct { 140 uint32_t pwm_offset_l_j : 16; /*!< The low 16 bits of the pwm phase control counter controls 141 the position of the pwm at 1 in a cycle. For PWM, 142 the value range is 1 to 65535. Each channel of PWM 143 corresponds to an offset parameter. */ 144 uint32_t reserved1_31 : 16; 145 } b; 146 } pwm_offset_l_data_t; 147 148 /** 149 * @brief This union represents the bit fields in the pwm_offset_high register. 150 * Read the register into the <i>d32</i> member then 151 * set/clear the bits using the <i>b</i> elements. 152 */ 153 typedef union pwm_offset_h_data { 154 uint32_t d32; /*!< Raw register data. */ 155 struct { 156 uint32_t pwm_offset_h_j : 16; /*!< The high 16 bits of the pwm phase control counter, 157 +1 after the pwm_offset_l count is full, controls 158 the position of the pwm at 1 in a cycle. For PWM, 159 the value range is 1 to 65535. Each channel of PWM 160 corresponds to an offset parameter. */ 161 uint32_t reserved1_31 : 16; 162 } b; 163 } pwm_offset_h_data_t; 164 165 /** 166 * @brief This union represents the bit fields in the pwm_freq_low register. 167 * Read the register into the <i>d32</i> member then 168 * set/clear the bits using the <i>b</i> elements. 169 */ 170 typedef union pwm_freq_l_data { 171 uint32_t d32; /*!< Raw register data. */ 172 struct { 173 uint32_t pwm_freq_l_j : 16; /*!< The low 16 bits of the pwm frequency control count 174 means the number of times the PWM clock is divided, 175 ranging from 1 to 65535. Each channel of pwm 176 corresponds to a freq parameter. */ 177 uint32_t reserved1_31 : 16; 178 } b; 179 } pwm_freq_l_data_t; 180 181 /** 182 * @brief This union represents the bit fields in the pwm_freq_high register. 183 * Read the register into the <i>d32</i> member then 184 * set/clear the bits using the <i>b</i> elements. 185 */ 186 typedef union pwm_freq_h_data { 187 uint32_t d32; /*!< Raw register data. */ 188 struct { 189 uint32_t pwm_freq_h_j : 16; /*!< The high 16 bits of the pwm frequency control count, 190 +1 after the pwm_freq_l count is full, 191 means the frequency division of the PWM clock, 192 the range is 1 to 65535. Each channel of pwm 193 corresponds to one freq parameter. */ 194 uint32_t reserved1_31 : 16; 195 } b; 196 } pwm_freq_h_data_t; 197 198 /** 199 * @brief This union represents the bit fields in the pwm_duty_low register. 200 * Read the register into the <i>d32</i> member then 201 * set/clear the bits using the <i>b</i> elements. 202 */ 203 typedef union pwm_duty_l_data { 204 uint32_t d32; /*!< Raw register data. */ 205 struct { 206 uint32_t pwm_duty_l_j : 16; /*!< The pwm duty cycle controls the low 16 bits of the count value, 207 ranging from 1 to 65535. 208 The duty cycle is the ratio of pwm_duty to pwm_freq. 209 Each pwm corresponds to a duty parameter. */ 210 uint32_t reserved1_31 : 16; 211 } b; 212 } pwm_duty_l_data_t; 213 214 /** 215 * @brief This union represents the bit fields in the pwm_duty_high register. 216 * Read the register into the <i>d32</i> member then 217 * set/clear the bits using the <i>b</i> elements. 218 */ 219 typedef union pwm_duty_h_data { 220 uint32_t d32; /*!< Raw register data. */ 221 struct { 222 uint32_t pwm_duty_h_j : 16; /*!< The high 16 bits of the pwm duty control counter, 223 +1 after pwm_duty_l is full, in the range 1 to 65535. 224 The duty cycle is the ratio of pwm_duty to pwm_freq. 225 Each pwm corresponds to a duty parameter. */ 226 uint32_t reserved1_31 : 16; 227 } b; 228 } pwm_duty_h_data_t; 229 230 /** 231 * @brief This union represents the bit fields in the pwm_periodload_flag register. 232 * Read the register into the <i>d32</i> member then 233 * set/clear the bits using the <i>b</i> elements. 234 */ 235 typedef union pwm_periodload_flag_data { 236 uint32_t d32; /*!< Raw register data. */ 237 struct { 238 uint32_t pwm_periodload_flag_j : 1; /*!< The flag register in which new parameters can be configured 239 when pwm smoothly switches to the next cycle 240 at the end of the cycle. The flag is generated at the end 241 of the cycle count. */ 242 uint32_t reserved1_31 : 31; 243 } b; 244 } pwm_periodload_flag_data_t; 245 246 /** 247 * @brief This union represents the bit fields in the pwm_period_value register. 248 * Read the register into the <i>d32</i> member then 249 * set/clear the bits using the <i>b</i> elements. 250 */ 251 typedef union pwm_period_val_data { 252 uint32_t d32; /*!< Raw register data. */ 253 struct { 254 uint32_t pwm_period_val_j : 16; /*!< Pwm output pulse value, non-zero trigger pwm output 255 pulse counting function, the number of output pulses 256 than this value will load new parameters to continue counting. */ 257 uint32_t reserved1_31 : 16; 258 } b; 259 } pwm_period_val_data_t; 260 261 /** 262 * @brief This union represents the bit fields in the pwm_periodcnt register. 263 * Read the register into the <i>d32</i> member then 264 * set/clear the bits using the <i>b</i> elements. 265 */ 266 typedef union pwm_periodcnt_data { 267 uint32_t d32; /*!< Raw register data. */ 268 struct { 269 uint32_t pwm_periodcnt_j : 16; /*!< Pwm output pulse count value. */ 270 uint32_t reserved16_31 : 16; 271 } b; 272 } pwm_periodcnt_data_t; 273 274 /** 275 * @brief This union represents the bit fields in the pwm_abnor_state0 register. 276 * Read the register into the <i>d32</i> member then 277 * set/clear the bits using the <i>b</i> elements. 278 */ 279 typedef union pwm_abnor_state0_data { 280 uint32_t d32; /*!< Raw register data. */ 281 struct { 282 uint32_t pwm_abnor_state0 : 16; /*!< The bit[15:0] is a configuration exception for Pwm 283 multi-channel use, corresponding to 1 bit per pwm channel. */ 284 uint32_t reserved16_31 : 16; 285 } b; 286 } pwm_abnor_state0_data_t; 287 288 /** 289 * @brief This union represents the bit fields in the pwm_abnor_state1 register. 290 * Read the register into the <i>d32</i> member then 291 * set/clear the bits using the <i>b</i> elements. 292 */ 293 typedef union pwm_abnor_state1_data { 294 uint32_t d32; /*!< Raw register data. */ 295 struct { 296 uint32_t pwm_abnor_state1 : 16; /*!< The bit[15:0] for Pwm count value configuration exception, 297 1 bit per pwm channel. */ 298 uint32_t reserved16_31 : 16; /*!< Reserved. */ 299 } b; 300 } pwm_abnor_state1_data_t; 301 302 /** 303 * @brief This union represents the bit fields in the pwm_abnor_state_clr0 register. 304 * Read the register into the <i>d32</i> member then 305 * set/clear the bits using the <i>b</i> elements. 306 */ 307 typedef union pwm_abnor_state_clr0_data { 308 uint32_t d32; /*!< Raw register data. */ 309 struct { 310 uint32_t pwm_abnor_state_clr0 : 16; /*!< Pwm exception clear register, corresponding to 311 register pwm_abnor_state0. */ 312 uint32_t reserved16_31 : 16; /*!< Reserved. */ 313 } b; 314 } pwm_abnor_state_clr0_data_t; 315 316 /** 317 * @brief This union represents the bit fields in the pwm_abnor_state_clr1 register. 318 * Read the register into the <i>d32</i> member then 319 * set/clear the bits using the <i>b</i> elements. 320 */ 321 typedef union pwm_abnor_state_clr1_data { 322 uint32_t d32; /*!< Raw register data. */ 323 struct { 324 uint32_t pwm_abnor_state_clr1 : 16; /*!< Pwm exception clear register, corresponding to 325 register pwm_abnor_state1. */ 326 uint32_t reserved16_31 : 16; /*!< Reserved. */ 327 } b; 328 } pwm_abnor_state_clr1_data_t; 329 330 /** 331 * @brief This union represents the bit fields in the pwm_int_mask register. 332 * Read the register into the <i>d32</i> member then 333 * set/clear the bits using the <i>b</i> elements. 334 */ 335 typedef union pwm_int_mask_data { 336 uint32_t d32; /*!< Raw register data. */ 337 struct { 338 uint32_t pwm_int_mask : 2; /*!< pwm interrupt mask register. 339 -0: mask; 340 -1: no mask, default mask. 341 bit[1]:step mode end of cycle cycle interrupt mask. 342 bit[0]:abnormal interrupt mask. */ 343 uint32_t reserved2_31 : 30; 344 } b; 345 } pwm_int_mask_data_t; 346 347 /** 348 * @brief This union represents the bit fields in the pwm_dma_en register. 349 * Read the register into the <i>d32</i> member then 350 * set/clear the bits using the <i>b</i> elements. 351 */ 352 typedef union pwm_dma_en_data { 353 uint32_t d32; /*!< Raw register data. */ 354 struct { 355 uint32_t pwm_dma_en : 1; /*!< dma function enable 356 -1: Enabled. 357 -0: not enabled. */ 358 uint32_t reserved1_31 : 31; 359 } b; 360 } pwm_dma_en_data_t; 361 362 /** 363 * @brief This union represents the bit fields in the pwm_cfg_int_clr0 register. 364 * Read the register into the <i>d32</i> member then 365 * set/clear the bits using the <i>b</i> elements. 366 */ 367 typedef union pwm_cfg_int_clr0_data { 368 uint32_t d32; /*!< Raw register data. */ 369 struct { 370 uint32_t pwm_cfg_int_clr0 : 16; /*!< Pwm step mode end-of-cycle interrupt clear register. 371 Corresponds to the pwm_cfg_int interrupt 372 and pwm_periodload_flag_j registers. */ 373 uint32_t reserved16_31 : 16; /*!< Reserved. */ 374 } b; 375 } pwm_cfg_int_clr0_data_t; 376 377 /** 378 * @brief Registers associated with the group of PWM. 379 */ 380 typedef struct pwm_v151_sel { 381 volatile uint32_t pwm_sel; /*!< pwm_sel. <i>Offset: 000h+10h*i</i>. */ 382 volatile uint32_t pwm_startclrcnt_en; /*!< pwm_startclrcnt_en. <i>Offset: 004h+10h*i</i>. */ 383 volatile uint32_t pwm_start; /*!< pwm_start. <i>Offset: 008h+10h*i</i>. */ 384 volatile uint32_t reserved; /*!< reserved. <i>Offset: 00Ch+10h*i</i>. */ 385 } pwm_v151_sel_t; 386 387 /** 388 * @brief Registers associated with the channel of PWM. 389 */ 390 typedef struct pwm_ip { 391 volatile uint32_t pwm_en; /*!< pwm_en. <i>Offset: 100h+40h*j</i>. */ 392 volatile uint32_t pwm_portity; /*!< pwm_portity. <i>Offset: 104h+40h*j</i>. */ 393 volatile uint32_t pwm_oen_cfg; /*!< pwm_oen_cfg. <i>Offset: 108h+40h*j</i>. */ 394 volatile uint32_t pwm_offset_l; /*!< pwm_offset_l. <i>Offset: 10Ch+40h*j</i>. */ 395 volatile uint32_t pwm_offset_h; /*!< pwm_offset_h. <i>Offset: 110h+40h*j</i>. */ 396 volatile uint32_t pwm_freq_l; /*!< pwm_freq_l. <i>Offset: 114h+40h*j</i>. */ 397 volatile uint32_t pwm_freq_h; /*!< pwm_freq_h. <i>Offset: 118h+40h*j</i>. */ 398 volatile uint32_t pwm_duty_l; /*!< pwm_duty_l. <i>Offset: 11Ch+40h*j</i>. */ 399 volatile uint32_t pwm_duty_h; /*!< pwm_duty_h. <i>Offset: 120h+40h*j</i>. */ 400 volatile uint32_t pwm_periodload_flag; /*!< pwm_periodload_flag. <i>Offset: 124h+40h*j</i>. */ 401 volatile uint32_t pwm_period_val; /*!< pwm_period_val. <i>Offset: 128h+40h*j</i>. */ 402 volatile uint32_t pwm_periodcnt; /*!< pwm_periodcnt. <i>Offset: 12Ch+40h*j</i>. */ 403 volatile uint32_t reserved1; /*!< reserved1. <i>Offset: 130h+40h*j</i>. */ 404 volatile uint32_t reserved2; /*!< reserved2. <i>Offset: 134h+40h*j</i>. */ 405 volatile uint32_t reserved3; /*!< reserved3. <i>Offset: 138h+40h*j</i>. */ 406 volatile uint32_t reserved4; /*!< reserved4. <i>Offset: 13Ch+40h*j</i>. */ 407 } pwm_ip_t; 408 409 typedef struct pwm_v151_regs { 410 volatile pwm_v151_sel_t pwm_v151_sel[CONFIG_PWM_GROUP_NUM]; /*!< PWM GROUP. <i>Offset: 000h</i>. */ 411 volatile pwm_v151_sel_t pwm_v151_sel_reserv[BIT16 - CONFIG_PWM_GROUP_NUM]; 412 volatile pwm_ip_t pwm_ip[CONFIG_PWM_CHANNEL_NUM]; /*!< PWM CHANNEL. <i>Offset: 100h</i>. */ 413 volatile pwm_ip_t pwm_ip_reserv1[BIT16 - CONFIG_PWM_CHANNEL_NUM]; 414 volatile uint32_t pwm_abnor_state0; /*!< pwm_abnor_state0. <i>Offset: 500h</i>. */ 415 volatile uint32_t pwm_abnor_state1; /*!< pwm_abnor_state1. <i>Offset: 504h</i>. */ 416 volatile uint32_t pwm_abnor_state_clr0; /*!< pwm_abnor_state_clr0.<i>Offset: 508h</i>. */ 417 volatile uint32_t pwm_abnor_state_clr1; /*!< pwm_abnor_state_clr1.<i>Offset: 50Ch</i>. */ 418 volatile uint32_t pwm_int_mask; /*!< pwm_int_mask. <i>Offset: 510h</i>. */ 419 volatile uint32_t pwm_dma_en; /*!< pwm_dma_en. <i>Offset: 514h</i>. */ 420 volatile uint32_t pwm_cfg_int_clr0; /*!< pwm_cfg_int_clr0. <i>Offset: 518h</i>. */ 421 } pwm_v151_regs_t; 422 423 /** 424 * @} 425 */ 426 427 #ifdef __cplusplus 428 #if __cplusplus 429 } 430 #endif /* __cplusplus */ 431 #endif /* __cplusplus */ 432 433 #endif