1 /**
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 *
15 * Description: Provides pwm port \n
16 *
17 * History: \n
18 * 2022-09-16， Create file. \n
19 */
20
21 #include "chip_core_irq.h"
22 #include "soc_osal.h"
23 #include "common_def.h"
24 #include "hal_pwm_v151.h"
25 #include "platform_core.h"
26 #include "pwm_porting.h"
27
28 #define BUS_CLOCK_TIME_40M 40000000UL
29 #define BIT_WIDTH_LIMIT 0xFFFF
30 #define CLDO_CRG_CLK_SEL 0x44001134
31 #define PWM_CKSEL_BIT 7
32
33 uintptr_t g_pwm_base_addr = (uintptr_t)PWM_0_BASE;
34
pwm_porting_base_addr_get(void)35 uintptr_t pwm_porting_base_addr_get(void)
36 {
37 return g_pwm_base_addr;
38 }
39
pwm_handler(int a,const void * tmp)40 static int pwm_handler(int a, const void *tmp)
41 {
42 unused(a);
43 unused(tmp);
44 hal_pwm_v151_irq_handler();
45 return 0;
46 }
47
48
pwm_port_register_hal_funcs(void)49 void pwm_port_register_hal_funcs(void)
50 {
51 hal_pwm_register_funcs(hal_pwm_v151_funcs_get());
52 }
53
pwm_port_unregister_hal_funcs(void)54 void pwm_port_unregister_hal_funcs(void)
55 {
56 hal_pwm_unregister_funcs();
57 }
58
pwm_port_clock_enable(bool on)59 void pwm_port_clock_enable(bool on)
60 {
61 if (on == true) {
62 uapi_reg_setbit(CLDO_CRG_CLK_SEL, PWM_CKSEL_BIT); // chose the clock source :PLL
63 }
64 }
65
pwm_port_register_irq(pwm_channel_t channel)66 void pwm_port_register_irq(pwm_channel_t channel)
67 {
68 unused(channel);
69 osal_irq_request((uintptr_t)PWM_ABNOR_IRQN, (osal_irq_handler)pwm_handler, NULL, NULL, NULL);
70
71 osal_irq_enable((uintptr_t)PWM_ABNOR_IRQN);
72 }
73
pwm_port_unregister_irq(pwm_channel_t channel)74 void pwm_port_unregister_irq(pwm_channel_t channel)
75 {
76 unused(channel);
77 osal_irq_disable((uintptr_t)PWM_ABNOR_IRQN);
78 osal_irq_disable((uintptr_t)PWM_CFG_IRQN);
79 osal_irq_free((uintptr_t)PWM_ABNOR_IRQN, NULL);
80 osal_irq_free((uintptr_t)PWM_CFG_IRQN, NULL);
81 }
82
pwm_irq_lock(uint8_t channel)83 void pwm_irq_lock(uint8_t channel)
84 {
85 unused(channel);
86 osal_irq_lock();
87 }
88
pwm_irq_unlock(uint8_t channel)89 void pwm_irq_unlock(uint8_t channel)
90 {
91 unused(channel);
92 osal_irq_unlock();
93 }
94
pwm_port_get_clock_value(pwm_channel_t channel)95 uint32_t pwm_port_get_clock_value(pwm_channel_t channel)
96 {
97 if (channel >= PWM_MAX_NUMBER) {
98 return 0;
99 }
100 return BUS_CLOCK_TIME_40M;
101 }
102
pwm_port_param_check(const pwm_config_t * cfg)103 errcode_t pwm_port_param_check(const pwm_config_t *cfg)
104 {
105 if ((cfg->low_time + cfg->high_time > BIT_WIDTH_LIMIT) || (cfg->offset_time > cfg->low_time)) {
106 return ERRCODE_PWM_INVALID_PARAMETER;
107 }
108 return ERRCODE_SUCC;
109 }