| /arkcompiler/runtime_core/static_core/compiler/tests/aarch64/ |
| D | register64_test.cpp | 92 ScopedTmpRegU32 reg2(&encoder); in TEST_F() local
96 ScopedTmpReg reg2(&encoder, floatType); in TEST_F() local
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| /arkcompiler/runtime_core/static_core/compiler/tests/aarch32/ |
| D | register32_test.cpp | 95 ScopedTmpRegU32 reg2(&encoder); in TEST_F() local
99 ScopedTmpReg reg2(&encoder, floatType); in TEST_F() local
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| /arkcompiler/runtime_core/static_core/compiler/tests/amd64/ |
| D | register64_test.cpp | 95 ScopedTmpRegU32 reg2(&encoder); in TEST_F() local
99 ScopedTmpReg reg2(&encoder, floatType); in TEST_F() local
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| /arkcompiler/runtime_core/compiler/tests/aarch32/ |
| D | register32_test.cpp | 98 ScopedTmpRegU32 reg2(&encoder); in TEST_F() local
102 ScopedTmpReg reg2(&encoder, FloatType); in TEST_F() local
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| /arkcompiler/runtime_core/compiler/tests/aarch64/ |
| D | register64_test.cpp | 95 ScopedTmpRegU32 reg2(&encoder); in TEST_F() local
99 ScopedTmpReg reg2(&encoder, FloatType); in TEST_F() local
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| /arkcompiler/runtime_core/compiler/tests/amd64/ |
| D | register64_test.cpp | 98 ScopedTmpRegU32 reg2(&encoder); in TEST_F() local
102 ScopedTmpReg reg2(&encoder, FloatType); in TEST_F() local
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/x86_64/ |
| D | x64_peep.cpp | 37 auto ®2 = static_cast<RegOperand &>(insn.GetOperand(kInsnSecondOpnd)); in CheckCondition() local
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| D | x64_args.cpp | 119 void X64MoveRegArgs::GenerateMovInsn(X64ArgInfo &argInfo, X64reg reg2) in GenerateMovInsn()
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| D | elf_assembler.cpp | 397 void ElfAssembler::OpRR(Reg reg1, Reg reg2, uint8 opCode1, uint8 opCode2, bool extInsn) in OpRR()
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/aarch64/ |
| D | aarch64_memlayout.h | 45 AArch64reg reg2 = kRinvalid; variable
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| /arkcompiler/runtime_core/assembler/tests/ |
| D | assembler_ins_test.cpp | 124 uint16_t reg2 = 3U; variable
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/x86_64/assembler/ |
| D | elf_assembler.h | 480 uint8 GetRex(Reg reg1, Reg reg2) const in GetRex()
527 uint8 GetModRM(Reg reg1, Reg reg2) const in GetModRM()
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/ |
| D | codegen.h | 512 Reg reg2; member
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| D | codegen.cpp | 1942 void Codegen::CreatePostWRB(Inst *inst, MemRef mem, Reg reg1, Reg reg2, RegMask preserved) in CreatePostWRB()
2000 void Codegen::CreatePostWRBForDynamic(Inst *inst, MemRef mem, Reg reg1, Reg reg2, RegMask preserved) in CreatePostWRBForDynamic()
2638 void PostWriteBarrier::Encode(MemRef mem, Reg reg1, Reg reg2, bool checkObject, RegMask preserved) in Encode()
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/ |
| D | call_conv.h | 29 regno_t reg2 = 0; /* can have up to 4 single precision fp registers */ member
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| /arkcompiler/runtime_core/bytecode_optimizer/tests/ |
| D | codegen_test.cpp | 309 Register reg2 = INVALID_REG; in __anon65c7fb950502() local
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| /arkcompiler/ets_runtime/test/moduletest/regexp/ |
| D | regexp.js | 66 var reg2 = /^[Α-ώ]+$/i variable
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/aarch64/ |
| D | aarch64_peep.cpp | 319 auto ®2 = static_cast<RegOperand &>(insn.GetOperand(kInsnSecondOpnd)); in CheckCondition() local
364 auto ®2 = static_cast<RegOperand &>(insn.GetOperand(kInsnSecondOpnd)); in Run() local
1646 auto ®2 = static_cast<RegOperand &>(prevInsn->GetOperand(kInsnFirstOpnd)); in Run() local
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| D | aarch64_cgfunc.cpp | 3425 auto ®2 = insn2->GetOperand(kInsnFirstOpnd); in DoOptForStackStrInsns() local
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| /arkcompiler/runtime_core/static_core/plugins/ets/compiler/ |
| D | codegen_intrinsics_ets.cpp | 198 auto reg2 = INVALID_REGISTER; in EncodeSbAppendString() local
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch32/ |
| D | encode.cpp | 150 auto reg2 = GetMasm()->GetScratchVRegisterList()->GetFirstAvailableSRegister(); in AcquireScratchRegister() local
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