1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19 #include "tde_hal_k.h"
20 #ifdef HI_BUILD_IN_BOOT
21 #include "higo_list.h"
22 #endif
23 #include "tde_hal.h"
24 #include "wmalloc.h"
25 #include "securec.h"
26 #include "hi_common.h"
27 #include "hi_math.h"
28 #include "tde_filterpara.h"
29 #include "tde_adp.h"
30 #include "tde_osictl_k.h"
31 #include "hi_osal.h"
32
33 /* compute struct member's offset */
34 #define tde_offset_of(type, member) ((hi_u32)(&((type *)0)->member))
35
36 #define UPDATE_SIZE 64
37
38 #define NO_HSCALE_STEP 0x100000
39 #define NO_VSCALE_STEP 0x1000
40
41 #ifndef HI_BUILD_IN_BOOT
42 #define drv_tde_node_blend_mode(node, a, b) \
43 do { \
44 (node)->src1_cbmpara.bits.s1_blendmode = (a); \
45 (node)->src2_cbmpara.bits.s2_blendmode = (b); \
46 } while (0)
47 #endif
48
49 /* R/W register's encapsulation */
50 #define tde_read_reg(base, offset) (*(volatile hi_u32 *)((hi_u8 *)(base) + (offset)))
51 #define tde_write_reg(base, offset, val) (*(volatile hi_u32 *)((hi_u8 *)(base) + (offset)) = val)
52 /* TDE register's Address range */
53 #define TDE_REG_SIZE 0x4100
54
55 /* Step range's type by algorithm team */
56 #define TDE_RESIZE_PARA_AREA_0 4096 /* 1.0 */
57 #define TDE_RESIZE_PARA_AREA_1 5461 /* 0.75 */
58 #define TDE_RESIZE_PARA_AREA_2 8192 /* 0.5 */
59 #define TDE_RESIZE_PARA_AREA_3 12412 /* 0.33 */
60 #define TDE_RESIZE_PARA_AREA_4 16384 /* 0.25 */
61
62 /* coefficient table rangle of 8*32 area */
63 #define TDE_RESIZE_8X32_AREA_0 1048576 /* 1.0 */
64 #define TDE_RESIZE_8X32_AREA_1 1398101 /* 0.75 */
65 #define TDE_RESIZE_8X32_AREA_2 2097152 /* 0.5 */
66 #define TDE_RESIZE_8X32_AREA_3 3177503 /* 0.33 */
67 #define TDE_RESIZE_8X32_AREA_4 4194304 /* 0.25 */
68
69 /* Colorkey mode of CMOS chip */
70 #define TDE_COLORKEY_IGNORE 2
71 #define TDE_COLORKEY_AREA_OUT 1
72 #define TDE_COLORKEY_AREA_IN 0
73
74 /* Aq control mode */
75 #define TDE_AQ_CTRL_COMP_LIST 0x0 /* start next AQ list, after complete current list's operations */
76 #define TDE_AQ_CTRL_COMP_LINE 0x4 /* start next AQ list, after complete current node and line */
77
78 #define TDE_MAX_READ_STATUS_TIME 10
79
80 #define TDE_TWENTYFOUR_BITS_SHIFT 24
81 #define TDE_EIGHT_BITS_SHIFT 8
82 #define TDE_SIXTEEN_BITS_SHIFT 16
83
84 /* Head address of argument table used as config */
85 typedef struct {
86 hi_u64 hf_coef_addr;
87 hi_u64 vf_coef_addr;
88 #ifndef HI_BUILD_IN_BOOT
89
90 #if (TDE_CAPABILITY & DEFLICKER)
91 hi_u64 deflicker_vf_coef_addr;
92 #endif
93
94 #endif
95 } tde_para_table;
96
97 typedef struct {
98 hi_u32 alpha_en;
99 hi_u32 luma_en;
100 hi_u32 chrome_en;
101 } tde_filtermode;
102
103 /* Base addr of register after mapping */
104 volatile hi_u32 *g_base_vir_addr = HI_NULL;
105 static hi_bool g_use_dtsi = HI_TRUE;
106
107 /* Pointer of TDE clock register after mapping */
108 static volatile hi_u32 *g_tde_clock_vir = HI_NULL;
109 /* Head address of config argument table */
110 static tde_para_table g_para_table = {0};
111
112 /* Deflicker level, default is auto */
113 #ifndef HI_BUILD_IN_BOOT
114
115 #if (TDE_CAPABILITY & DEFLICKER)
116 static hi_tde_deflicker_level g_deflicker_level = HI_TDE_DEFLICKER_LEVEL_AUTO;
117 #endif
118
119 #endif
120 /* alpha threshold switch */
121 static hi_bool g_alpha_threshold = HI_FALSE;
122
123 /* alpha threshold value */
124 static hi_u8 g_alpha_threshold_value = 0xff;
125
126 static tde_alu_mode g_cbmctrl_alu_mode[TDE_BUTT + 1] = {
127 TDE_SRC2_BYPASS, TDE_ALU_NONE, TDE_ALU_ROP, TDE_SRC2_BYPASS, TDE_ALU_MASK_ROP1, TDE_ALU_MASK_ROP2,
128 TDE_ALU_MASK_BLEND, TDE_SRC2_BYPASS, TDE_SRC2_BYPASS, TDE_SRC2_BYPASS, TDE_SRC2_BYPASS, TDE_BUTT
129 };
130
131 static hi_s32 tde_hal_init_para_table(hi_void);
132
133 #ifndef HI_BUILD_IN_BOOT
134 static hi_void tde_hal_node_set_clutcolor_key_para(tde_hw_node *hw_node, tde_color_key_cmd *color_key);
135 static hi_void tde_hal_node_set_ycbcr_color_key_para(tde_hw_node *hw_node, tde_color_key_cmd *color_key);
136 static hi_void tde_hal_node_set_argbcolor_key_para(tde_hw_node *hw_node, tde_color_key_cmd *color_key);
137
138 static hi_u32 tde_hal_get_color_key_mode(hi_tde_color_key_comp *color_key);
139 static hi_u32 tde_hal_get_ycb_cr_key_mask(hi_u8 cr, hi_u8 cb, hi_u8 cy, hi_u8 alpha);
140 static hi_u32 tde_hal_get_clut_key_mask(hi_u8 clut, hi_u8 alpha);
141 static hi_u32 tde_hal_get_argb_key_mask(hi_u8 blue, hi_u8 green, hi_u8 red, hi_u8 alpha);
142
143 #endif
144
145 static hi_s32 tde_hal_getbpp_by_fmt(tde_color_fmt fmt);
146 static hi_u32 tde_hal_get_resize_para_htable(hi_u32 step);
147 static hi_u32 tde_hal_get_resize_para_vtable(hi_u32 step);
148
149 static hi_void tde_hal_init_queue(hi_void);
150 hi_void tde_hal_set_clock(hi_bool enable);
151 static hi_s32 tde_hal_getbpp_by_fmt1(tde_color_fmt fmt);
152 static hi_s32 tde_hal_getbpp_by_fmt2(tde_color_fmt fmt);
153 static hi_s32 tde_hal_getbpp_by_fmt4(tde_color_fmt fmt);
154 static hi_s32 tde_hal_getbpp_by_fmt8(tde_color_fmt fmt);
155 static hi_s32 tde_hal_getbpp_by_fmt16(tde_color_fmt fmt);
156 static hi_s32 tde_hal_getbpp_by_fmt24(tde_color_fmt fmt);
157 static hi_s32 tde_hal_getbpp_by_fmt32(tde_color_fmt fmt);
158 #ifndef HI_BUILD_IN_BOOT
159 #define registder_flush() mb()
160 #else
161 #define registder_flush() \
162 { \
163 do { \
164 } while (0); \
165 }
166 #endif
167 static hi_bool tde_hal_is_operation_support(tde_alu_mode alu_mode, hi_u32 capability, hi_u32 oper_mode);
168 static hi_u32 tde_hal_get_zme_in_fmt(tde_color_fmt in_drv_fmt);
169 static hi_u32 tde_hal_get_hpzme_mode(hi_u32 out_rect_width, hi_u32 in_rect_width);
170 static hi_void tde_hal_get_filter_mode(hi_tde_filter_mode filter_mode, tde_filtermode *flt_mode);
171 static hi_s32 tde_hal_get_ver_scale_coeff(hi_u32 out_rect_height, hi_u32 in_rect_height, hi_s32 *ver_scale_coeff);
172
tde_fill_data_by_fmt(tde_hw_node * hw_node,hi_u32 data,tde_color_fmt fmt,hi_u8 flag)173 static hi_void tde_fill_data_by_fmt(tde_hw_node *hw_node, hi_u32 data, tde_color_fmt fmt, hi_u8 flag)
174 {
175 hi_u32 bpp, i, cell;
176 bpp = tde_hal_getbpp_by_fmt(fmt);
177 if (bpp != 0xffffffff) {
178 cell = data & (0xffffffff >> (32 - bpp)); /* 32 bpp The not, 0xffffffff mask */
179 for (i = 0; i < (32 / bpp); i++) { /* 32 bpp fmt */
180 if (flag) {
181 (hw_node->src2_fill.bits.src2_color_fill) |= (cell << (i * bpp));
182 } else {
183 (hw_node->src1_fill.bits.src1_color_fill) |= (cell << (i * bpp));
184 }
185 }
186 } else {
187 if (flag) {
188 (hw_node->src2_fill.bits.src2_color_fill) = data;
189 } else {
190 (hw_node->src1_fill.bits.src1_color_fill) = data;
191 }
192 }
193 return;
194 }
195
tde_hal_set_base_vir_addr(hi_u32 * temp_base_vir_addr)196 hi_void tde_hal_set_base_vir_addr(hi_u32 *temp_base_vir_addr)
197 {
198 g_base_vir_addr = temp_base_vir_addr;
199 }
200
tde_hal_get_base_vir_addr(hi_void)201 volatile hi_u32 *tde_hal_get_base_vir_addr(hi_void)
202 {
203 return g_base_vir_addr;
204 }
205
206 /*
207 * Function: tde_hal_init
208 * Description: map the base address for tde
209 * Input: base_addr: the base address of tde
210 * Return: success/fail
211 */
tde_hal_init(hi_u32 base_addr)212 hi_s32 tde_hal_init(hi_u32 base_addr)
213 {
214 /* init the pool memory of tde, CNcomment: Initialize the TDE memory pool */
215 if (wmeminit() != HI_SUCCESS) {
216 goto TDE_INIT_ERR;
217 }
218 /* config start address for the parameter, CNcomment: The first address configuration parameter table */
219 if (tde_hal_init_para_table() != HI_SUCCESS) {
220 wmemterm();
221 goto TDE_INIT_ERR;
222 }
223 #ifndef HI_BUILD_IN_BOOT
224 /* map address for the register, CNcomment: Register mapping */
225 g_use_dtsi = HI_TRUE;
226 if (g_base_vir_addr == HI_NULL) {
227 g_base_vir_addr = (volatile hi_u32 *)tde_reg_map(base_addr, TDE_REG_SIZE);
228 g_use_dtsi = HI_FALSE;
229 }
230
231 if (g_base_vir_addr == HI_NULL) {
232 wmemterm();
233 goto TDE_INIT_ERR;
234 }
235 /* set limit of clock and div, CNcomment: Set the clock threshold, clock frequency division */
236 g_tde_clock_vir = (volatile hi_u32 *)tde_reg_map(TDE_REG_CLOCK, 4); /* 4 size */
237 if (g_tde_clock_vir == HI_NULL) {
238 wmemterm();
239 tde_reg_unmap(g_base_vir_addr);
240 goto TDE_INIT_ERR;
241 }
242 #else
243 g_base_vir_addr = (hi_u32 *)base_addr;
244 #endif
245 tde_hal_set_clock(HI_TRUE);
246 return HI_SUCCESS;
247
248 TDE_INIT_ERR:
249 return HI_FAILURE;
250 }
251
252 #ifndef HI_BUILD_IN_BOOT
tde_hal_resume_init(hi_void)253 hi_void tde_hal_resume_init(hi_void)
254 {
255 tde_hal_set_clock(HI_TRUE);
256
257 tde_hal_ctl_reset();
258
259 tde_hal_init_queue();
260
261 return;
262 }
263
tde_hal_suspend(hi_void)264 hi_void tde_hal_suspend(hi_void)
265 {
266 tde_hal_set_clock(HI_FALSE);
267 return;
268 }
269
tde_hal_close(hi_void)270 hi_s32 tde_hal_close(hi_void)
271 {
272 tde_hal_set_clock(HI_FALSE);
273 return HI_SUCCESS;
274 }
275
tde_hal_open(hi_void)276 hi_s32 tde_hal_open(hi_void)
277 {
278 return HI_SUCCESS;
279 }
280
281 /*
282 * Function: tde_hal_release
283 * Description: release the address that had map
284 * Return: success/fail
285 */
tde_hal_release(hi_void)286 hi_void tde_hal_release(hi_void)
287 {
288 hi_void *buf = HI_NULL;
289 if (g_para_table.hf_coef_addr != 0) {
290 buf = (hi_void *)wgetvrt(g_para_table.hf_coef_addr);
291 if (buf != HI_NULL) {
292 tde_free(buf);
293 buf = HI_NULL;
294 g_para_table.hf_coef_addr = 0;
295 }
296 }
297 if (g_para_table.vf_coef_addr != 0) {
298 buf = (hi_void *)wgetvrt(g_para_table.vf_coef_addr);
299 if (buf != HI_NULL) {
300 tde_free(buf);
301 buf = HI_NULL;
302 g_para_table.vf_coef_addr = 0;
303 }
304 }
305 #ifndef HI_BUILD_IN_BOOT
306
307 #if (TDE_CAPABILITY & DEFLICKER)
308 if (g_para_table.deflicker_vf_coef_addr != 0) {
309 buf = (hi_void *)wgetvrt(g_para_table.deflicker_vf_coef_addr);
310 if (buf != HI_NULL) {
311 tde_free(buf);
312 buf = HI_NULL;
313 g_para_table.deflicker_vf_coef_addr = 0;
314 }
315 }
316 #endif
317
318 #endif
319 /* unmap, CNcomment: Remove the mapping */
320 if (g_tde_clock_vir != HI_NULL) {
321 tde_reg_unmap(g_tde_clock_vir);
322 }
323 g_tde_clock_vir = HI_NULL;
324 /* unmap the base address, CNcomment: Reflect the base address */
325 if (g_use_dtsi == HI_FALSE) {
326 tde_reg_unmap(g_base_vir_addr);
327 }
328 g_base_vir_addr = HI_NULL;
329
330 /* free the pool of memory, CNcomment: TDE memory pool to initialize */
331 wmemterm();
332
333 return;
334 }
335 #endif /* HI_BUILD_IN_BOOT */
336
337 #if (HICHIP == HI3516C_V500)
tde_hal_ctl_is_idle(hi_void)338 hi_bool tde_hal_ctl_is_idle(hi_void)
339 {
340 return (hi_bool)(!(tde_read_reg(g_base_vir_addr, TDE_STA) & 0xff));
341 }
342 #else
tde_hal_ctl_is_idle(hi_void)343 hi_bool tde_hal_ctl_is_idle(hi_void)
344 {
345 return (hi_bool)(!(tde_read_reg(g_base_vir_addr, TDE_STA) & 0x1));
346 }
347 #endif
348
349 /*
350 * Function: tde_hal_ctl_is_idle_safely
351 * Description: get the state of tde one more time ,make sure it's idle
352 * Return: True: Idle/False: Busy
353 */
tde_hal_ctl_is_idle_safely(hi_void)354 hi_bool tde_hal_ctl_is_idle_safely(hi_void)
355 {
356 hi_u32 i;
357
358 /*
359 * get the state of tde one more time ,make sure it's idle
360 * CNcomment: Continuous read hardware status for many times, make sure complete TDE
361 */
362 for (i = 0; i < TDE_MAX_READ_STATUS_TIME; i++) {
363 if (!tde_hal_ctl_is_idle()) {
364 return HI_FALSE;
365 }
366 }
367 return HI_TRUE;
368 }
369
tde_hal_ctl_int_status(hi_void)370 hi_u32 tde_hal_ctl_int_status(hi_void)
371 {
372 hi_u32 value;
373
374 value = tde_read_reg(g_base_vir_addr, TDE_INT);
375 /* clear all status */
376 tde_write_reg(g_base_vir_addr, TDE_INTCLR, value);
377 return value;
378 }
379
tde_hal_ctl_reset(hi_void)380 hi_void tde_hal_ctl_reset(hi_void)
381 {
382 tde_write_reg(g_base_vir_addr, TDE_INTCLR, 0xf);
383 tde_write_reg(g_base_vir_addr, TDE_MISCELLANEOUS, 0x0100647f);
384 return;
385 }
386
387 /*
388 * Function: tde_hal_set_clock
389 * Description: enable or disable the clock of TDE
390 * Input: hi_bool enable:enable/disable
391 */
tde_hal_set_clock(hi_bool enable)392 hi_void tde_hal_set_clock(hi_bool enable)
393 {
394 if (enable) {
395 /* cancel reset */
396 *g_tde_clock_vir &= ~0x1;
397
398 /* 0x2 enable clock */
399 *g_tde_clock_vir |= 0x2;
400 } else {
401 #ifdef TDE_LOWPOWER
402 /* 0x2 disable clock */
403 *g_tde_clock_vir &= ~0x2;
404
405 /* reset */
406 *g_tde_clock_vir |= 0x1;
407 #endif
408 }
409 }
410
411 #ifndef HI_BUILD_IN_BOOT
412 /*
413 * Function: tde_hal_ctl_int_clear
414 * Description: clear the state of interrupt
415 * Input: stats: state that need clear
416 */
tde_hal_ctl_int_clear(hi_u32 stats)417 hi_void tde_hal_ctl_int_clear(hi_u32 stats)
418 {
419 hi_u32 read_stats;
420
421 read_stats = tde_read_reg(g_base_vir_addr, TDE_INT);
422 /* 16 left to the highest level, 0x0000ffff 0xffff0000 mask */
423 read_stats = (read_stats & 0x0000ffff) | ((stats << 16) & 0xffff0000);
424
425 tde_write_reg(g_base_vir_addr, TDE_INT, read_stats);
426 }
427 #endif
428
429 /*
430 * Function: tde_hal_node_init_nd
431 * Description: init the software node struct for tde
432 * Input: hw_node: the pointer of software node struct
433 */
tde_hal_node_init_nd(tde_hw_node ** hw_node)434 hi_s32 tde_hal_node_init_nd(tde_hw_node **hw_node)
435 {
436 hi_void *buf = HI_NULL;
437
438 if (hw_node == HI_NULL) {
439 return HI_FAILURE;
440 }
441 buf = (hi_void *)tde_malloc(sizeof(tde_hw_node) + TDE_NODE_HEAD_BYTE + TDE_NODE_TAIL_BYTE);
442 if (buf == HI_NULL) {
443 tde_error("malloc (%lu) failed, wgetfreenum(%u)!\n",
444 (unsigned long)(sizeof(tde_hw_node) + TDE_NODE_HEAD_BYTE + TDE_NODE_TAIL_BYTE), wgetfreenum());
445 return HI_ERR_TDE_NO_MEM;
446 }
447
448 *hw_node = (tde_hw_node *)((hi_u8 *)buf + TDE_NODE_HEAD_BYTE);
449
450 return HI_SUCCESS;
451 }
452
453 #ifdef CONFIG_GFX_MMU_SUPPORT
tde_hal_free_tmp_buf(tde_hw_node * hw_node)454 hi_void tde_hal_free_tmp_buf(tde_hw_node *hw_node)
455 {
456 return;
457 }
458 #endif
459
460 /*
461 * Function: tde_hal_free_node_buf
462 * Description: Free TDE operate node buffer
463 * Input: hw_node:Node struct pointer.
464 */
tde_hal_free_node_buf(tde_hw_node * hw_node)465 hi_void tde_hal_free_node_buf(tde_hw_node *hw_node)
466 {
467 hi_void *buf = HI_NULL;
468
469 if (hw_node == HI_NULL) {
470 return;
471 }
472 buf = (hi_u8 *)hw_node - TDE_NODE_HEAD_BYTE;
473
474 #ifdef CONFIG_GFX_MMU_SUPPORT
475 tde_hal_free_tmp_buf(hw_node);
476 #endif
477
478 tde_free(buf);
479 return;
480 }
481
482 /*
483 * Function: tde_hal_node_execute
484 * Description: start list of tde
485 * Input: nodephy_addr: the start address of head node address
486 * update:the head node update set
487 * aq_use_buff: whether use temp buffer
488 */
tde_hal_node_execute(hi_u64 nodephy_addr,hi_u64 update,hi_bool aq_use_buff)489 hi_s32 tde_hal_node_execute(hi_u64 nodephy_addr, hi_u64 update, hi_bool aq_use_buff)
490 {
491 hi_unused(update);
492 hi_unused(aq_use_buff);
493 /* tde is idle */
494 if (tde_hal_ctl_is_idle_safely()) {
495 tde_hal_set_clock(HI_TRUE);
496 tde_hal_ctl_reset();
497 tde_hal_init_queue();
498
499 /* write the first node address */
500 tde_write_reg(g_base_vir_addr, TDE_AQ_NADDR_LOW, GetLowAddr(nodephy_addr));
501 tde_write_reg(g_base_vir_addr, TDE_AQ_NADDR_HI, GetHighAddr(nodephy_addr));
502 #ifndef HI_BUILD_IN_BOOT
503 osal_dmb();
504 #endif
505 osal_udelay(100); /* 100 time out */
506 /* start Aq list, CNcomment : Start the Aq */
507 tde_write_reg(g_base_vir_addr, TDE_CTRL, 0x1);
508 } else {
509 return HI_FAILURE;
510 }
511
512 return HI_SUCCESS;
513 }
514
515 /*
516 * Function: tde_hal_node_enable_complete_int
517 * Description: enable the finish interrupt of node
518 * Input: buf: buffer of node
519 */
tde_hal_node_enable_complete_int(hi_void * buf)520 hi_void tde_hal_node_enable_complete_int(hi_void *buf)
521 {
522 tde_hw_node *hw_node = (tde_hw_node *)buf;
523 if (buf == HI_NULL) {
524 tde_error("pBuf is null %s(line=%d)\n", __FUNCTION__, __LINE__);
525 return;
526 }
527 hw_node->tde_intmask.bits.eof_mask = 0;
528 hw_node->tde_intmask.bits.timeout_mask = 0x1;
529 hw_node->tde_intmask.bits.bus_err_mask = 0x1;
530 #ifdef TDE_HWC_COOPERATE
531 hw_node->tde_intmask.bits.eof_end_mask = 0x0;
532 #else
533 hw_node->tde_intmask.bits.eof_end_mask = 0x1;
534 #endif
535 return;
536 }
537
tde_hal_next_node_addr(hi_void * buf,hi_u64 phy_addr)538 hi_void tde_hal_next_node_addr(hi_void *buf, hi_u64 phy_addr)
539 {
540 tde_hw_node *hw_node = (tde_hw_node *)buf;
541 if (buf == HI_NULL) {
542 tde_error("pBuf is null %s(line=%d)\n", __FUNCTION__, __LINE__);
543 return;
544 }
545 hw_node->tde_pnext_low.bits.next_low = GetLowAddr(phy_addr);
546 hw_node->tde_pnext_hi.bits.next_hi = GetHighAddr(phy_addr);
547 return;
548 }
549
550 #if (TDE_CAPABILITY & SYNC)
tde_hal_node_enable_sync(hi_void * buf)551 hi_void tde_hal_node_enable_sync(hi_void *buf)
552 {
553 tde_hw_node *hw_node = (tde_hw_node *)buf;
554 if (buf == HI_NULL) {
555 tde_error("pBuf is null %s(line=%d)\n", __FUNCTION__, __LINE__);
556 return;
557 }
558 hw_node->des_ctrl.bits.des_bind_en = 0x1;
559 if ((hw_node->des_ctrl.bits.des_fmt == TDE_DRV_COLOR_FMT_YCBCR888) ||
560 (hw_node->des_ctrl.bits.des_fmt == TDE_DRV_COLOR_FMT_YCBCR422)) {
561 hw_node->des_ctrl.bits.des_bind_mode = 0x0;
562 } else {
563 hw_node->des_ctrl.bits.des_bind_mode = 0x1;
564 }
565 hw_node->DES_SAFE_DIST.all = hw_node->des_ch0_stride.all / 4; /* 4 buf narrow */
566 hw_node->DES_SAFE_DIST_INVERSE.all = hw_node->des_ch0_stride.all / 4; /* 4 buf narrow */
567 return;
568 }
569 #endif
570
571 /*
572 * Function: tde_hal_node_set_src1
573 * Description: set the info for source of bitmap 1
574 * Input: hw_node: pointer of node
575 * drv_surface: bitmap info
576 */
tde_hal_node_set_src1(tde_hw_node * hw_node,tde_surface_msg * drv_surface)577 hi_void tde_hal_node_set_src1(tde_hw_node *hw_node, tde_surface_msg *drv_surface)
578 {
579 hi_u32 bpp;
580 hi_u64 phy_addr;
581 if (hw_node == HI_NULL) {
582 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
583 return;
584 }
585 if (drv_surface == HI_NULL) {
586 tde_error("pDrvSurface is null %s(line=%d)\n", __FUNCTION__, __LINE__);
587 return;
588 }
589 /* set the source bitmap attribute info, CNcomment: Configure attribute information source bitmap */
590 hw_node->src1_ctrl.bits.src1_fmt = (hi_u32)drv_surface->color_fmt;
591 hw_node->src1_ctrl.bits.src1_alpha_range = 1 - (hi_u32)drv_surface->alpha_max_is_255;
592 hw_node->src1_ctrl.bits.src1_h_scan_ord = (hi_u32)drv_surface->h_scan;
593 hw_node->src1_ctrl.bits.src1_v_scan_ord = (hi_u32)drv_surface->v_scan;
594 /*
595 * file zero of low area and top area use low area extend
596 * CNcomment: Have been using low filling is 0, high use low expansion mode
597 */
598 hw_node->src1_ctrl.bits.src1_rgb_exp = 0;
599
600 hw_node->src1_imgsize.bits.src1_width = drv_surface->width - 1;
601 hw_node->src1_imgsize.bits.src1_height = drv_surface->height - 1;
602
603 bpp = tde_hal_getbpp_by_fmt(drv_surface->color_fmt);
604
605 phy_addr = drv_surface->phy_addr + (hi_u64)(drv_surface->ypos) * (hi_u64)(drv_surface->pitch) +
606 (((hi_u64)(drv_surface->xpos) * (hi_u64)(bpp)) >> 3); /* bpp 2^3 */
607
608 hw_node->src1_ch0_addr_low.bits.src1_ch0_addr_low = GetLowAddr(phy_addr);
609 hw_node->src1_ch0_addr_high.bits.src1_ch0_addr_high = GetHighAddr(phy_addr);
610
611 if (drv_surface->color_fmt <= TDE_DRV_COLOR_FMT_RGB565) {
612 hw_node->src1_ctrl.bits.src1_argb_order = drv_surface->rgb_order;
613 }
614 /*
615 * target bitmapis same with source bitmap 1,so not need set.
616 * config the node, CNcomment: Configure the cache node
617 */
618 hw_node->src1_ch0_stride.bits.src1_ch0_stride = drv_surface->pitch;
619 return;
620 }
621
tde_hal_set_src2_ctrl(tde_hw_node * hw_node,tde_surface_msg * drv_surface)622 static hi_void tde_hal_set_src2_ctrl(tde_hw_node *hw_node, tde_surface_msg *drv_surface)
623 {
624 hw_node->src2_ctrl.bits.src2_fmt = (hi_u32)drv_surface->color_fmt;
625 hw_node->src2_ctrl.bits.src2_alpha_range = 0;
626 hw_node->src2_ctrl.bits.src2_h_scan_ord = (hi_u32)drv_surface->h_scan;
627 hw_node->src2_ctrl.bits.src2_v_scan_ord = (hi_u32)drv_surface->v_scan;
628 }
629
tde_hal_set_src2_img_size(tde_hw_node * hw_node,tde_surface_msg * drv_surface)630 static hi_void tde_hal_set_src2_img_size(tde_hw_node *hw_node, tde_surface_msg *drv_surface)
631 {
632 hw_node->src2_imgsize.bits.src2_width = drv_surface->width - 1;
633 hw_node->src2_imgsize.bits.src2_height = drv_surface->height - 1;
634 }
635
tde_hal_set_src2_addr(tde_hw_node * hw_node,tde_surface_msg * drv_surface,hi_u64 * phy_addr,hi_u64 * cb_crphy_addr)636 static hi_void tde_hal_set_src2_addr(tde_hw_node *hw_node, tde_surface_msg *drv_surface, hi_u64 *phy_addr,
637 hi_u64 *cb_crphy_addr)
638 {
639 hi_u32 bpp = tde_hal_getbpp_by_fmt(drv_surface->color_fmt);
640 if (drv_surface->color_fmt >= TDE_DRV_COLOR_FMT_YCBCR400MBP) {
641 *phy_addr = drv_surface->phy_addr + (hi_u64)(drv_surface->ypos) *
642 (hi_u64)(drv_surface->pitch) + (((hi_u64)(drv_surface->xpos) * 8) >> 3); /* 3 8 xpos alg data */
643
644 hw_node->src2_ch0_addr_low.bits.src2_ch0_addr_low = GetLowAddr(*phy_addr);
645 hw_node->src2_ch0_addr_high.bits.src2_ch0_addr_high = GetHighAddr(*phy_addr);
646 switch (drv_surface->color_fmt) {
647 case TDE_DRV_COLOR_FMT_YCBCR422MBH:
648 *cb_crphy_addr = drv_surface->cbcr_phy_addr +
649 (hi_u64)(drv_surface->ypos) * (hi_u64)(drv_surface->cb_cr_pitch) +
650 ((hi_u64)(drv_surface->xpos) / 2 * 2); /* 2 xpos alg data cb_crphy_addr */
651 break;
652 case TDE_DRV_COLOR_FMT_YCBCR422MBV:
653 *cb_crphy_addr = drv_surface->cbcr_phy_addr +
654 /* 2 ypos size */
655 (hi_u64)(drv_surface->ypos / 2) * (hi_u64)(drv_surface->cb_cr_pitch) +
656 (((hi_u64)(drv_surface->xpos) * 16) >> 3); /* 16 3 alg data cb_crphy_addr */
657 break;
658 case TDE_DRV_COLOR_FMT_YCBCR420MB:
659 *cb_crphy_addr = drv_surface->cbcr_phy_addr +
660 /* 2 alg data */
661 (hi_u64)(drv_surface->ypos / 2) * (hi_u64)(drv_surface->cb_cr_pitch) +
662 ((hi_u64)(drv_surface->xpos) / 2 * 2); /* 2 xpos alg data cb_crphy_addr */
663 break;
664 case TDE_DRV_COLOR_FMT_YCBCR444MB:
665 *cb_crphy_addr = drv_surface->cbcr_phy_addr +
666 (hi_u64)(drv_surface->ypos) * (hi_u64)(drv_surface->cb_cr_pitch) +
667 (((hi_u64)(drv_surface->xpos) * 16) >> 3); /* 16 3 alg data */
668 break;
669 default:;
670 }
671
672 hw_node->src2_ch1_addr_low.bits.src2_ch1_addr_low = GetLowAddr(*cb_crphy_addr);
673 hw_node->src2_ch1_addr_high.bits.src2_ch1_addr_high = GetHighAddr(*cb_crphy_addr);
674
675 if (drv_surface->color_fmt == TDE_DRV_COLOR_FMT_YCBCR422MBV) {
676 hw_node->src2_ctrl.bits.src2_422v_pro = 1;
677 }
678 } else {
679 *phy_addr = drv_surface->phy_addr + (hi_u64)(drv_surface->ypos) *
680 /* alg data 2^3 */
681 (hi_u64)(drv_surface->pitch) + (((hi_u64)(drv_surface->xpos) * (hi_u64)(bpp)) >> 3);
682 hw_node->src2_ch0_addr_low.bits.src2_ch0_addr_low = GetLowAddr(*phy_addr);
683 hw_node->src2_ch0_addr_high.bits.src2_ch0_addr_high = GetHighAddr(*phy_addr);
684
685 if (drv_surface->color_fmt <= TDE_DRV_COLOR_FMT_RGB565) {
686 hw_node->src2_ctrl.bits.src2_argb_order = drv_surface->rgb_order;
687 }
688 }
689 }
690
691 /*
692 * Function: tde_hal_node_set_src2
693 * Description: set the source bitmap 2
694 * Input: hw_node: pointer of node
695 * drv_surface: bitmap info
696 */
tde_hal_node_set_src2(tde_hw_node * hw_node,tde_surface_msg * drv_surface)697 hi_void tde_hal_node_set_src2(tde_hw_node *hw_node, tde_surface_msg *drv_surface)
698 {
699 hi_u64 phy_addr;
700 hi_u64 cb_crphy_addr;
701
702 if (hw_node == HI_NULL) {
703 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
704 return;
705 }
706 if (drv_surface == HI_NULL) {
707 tde_error("pDrvSurface is null %s(line=%d)\n", __FUNCTION__, __LINE__);
708 return;
709 }
710
711 /* set attribute info for source bitmap, CNcomment:Configure attribute information source bitmap */
712 tde_hal_set_src2_ctrl(hw_node, drv_surface);
713 /*
714 * file zero of low area and top area use low area extend
715 * CNcomment: Have been using low filling is 0, high use low expansion mode
716 */
717 hw_node->src2_ctrl.bits.src2_rgb_exp = 0;
718
719 tde_hal_set_src2_img_size(hw_node, drv_surface);
720
721 phy_addr = drv_surface->phy_addr;
722 cb_crphy_addr = drv_surface->cbcr_phy_addr;
723
724 tde_hal_set_src2_addr(hw_node, drv_surface, &phy_addr, &cb_crphy_addr);
725 if (drv_surface->color_fmt <= TDE_DRV_COLOR_FMT_A1) {
726 hw_node->src2_alpha.bits.src2_alpha0 = 0x00;
727 hw_node->src2_alpha.bits.src2_alpha1 = 0xff;
728 }
729 hw_node->src2_ch0_stride.bits.src2_ch0_stride = drv_surface->pitch;
730 hw_node->src2_ch1_stride.bits.src2_ch1_stride = drv_surface->cb_cr_pitch;
731
732 return;
733 }
734
735 #if (TDE_CAPABILITY & COMPRESS)
tde_hal_node_set_src_to_decompress(tde_hw_node * hw_node,tde_surface_msg * drv_surface)736 hi_void tde_hal_node_set_src_to_decompress(tde_hw_node *hw_node, tde_surface_msg *drv_surface)
737 {
738 if (hw_node == HI_NULL) {
739 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
740 return;
741 }
742 tde_hal_node_set_src2(hw_node, drv_surface);
743
744 hw_node->src2_ctrl.bits.src2_is_lossless = 0;
745 hw_node->src2_ctrl.bits.src2_is_lossless_a = 0;
746 hw_node->src2_ctrl.bits.src2_dcmp_en = 1;
747 hw_node->src2_ctrl.bits.src2_top_pred_en = 1;
748
749 return;
750 }
751 #endif
752
tde_hal_node_set_hw_node(tde_hw_node * hw_node,tde_surface_msg * drv_surface,hi_tde_out_alpha_from alpha_from)753 static hi_void tde_hal_node_set_hw_node(tde_hw_node *hw_node, tde_surface_msg *drv_surface,
754 hi_tde_out_alpha_from alpha_from)
755 {
756 /* set bitmap attribute info, CNcomment:Configure attribute information source bitmap */
757 hw_node->des_ctrl.bits.des_en = 1;
758 hw_node->des_ctrl.bits.des_fmt = drv_surface->color_fmt;
759 hw_node->des_ctrl.bits.des_alpha_range = 1 - (hi_u32)drv_surface->alpha_max_is_255;
760 hw_node->des_ctrl.bits.des_h_scan_ord = (hi_u32)drv_surface->h_scan;
761 hw_node->des_ctrl.bits.des_v_scan_ord = (hi_u32)drv_surface->v_scan;
762 hw_node->des_ctrl.bits.des_alpha_range = 1 - (hi_u32)drv_surface->alpha_max_is_255;
763 hw_node->des_ctrl.bits.des_rgb_round = 1; /* CNcomment:Always use four shed no into the way of cutting bit */
764
765 hw_node->cbmalupara.bits.alpha_from = (hi_u32)alpha_from;
766 hw_node->des_alpha.bits.des_alpha_thd = g_alpha_threshold_value;
767
768 /* set bitmap size info, CNcomment: Configure the bitmap size information */
769 hw_node->des_imgsize.bits.des_width = (hi_u32)drv_surface->width - 1;
770 hw_node->des_imgsize.bits.des_height = (hi_u32)drv_surface->height - 1;
771 }
772
773 /*
774 * Function: tde_hal_node_set_tqt
775 * Description: set target bitmap info
776 * Input: hw_node: pointer of node
777 * drv_surface: bitmap info
778 * alpha_from: alpha from
779 */
tde_hal_node_set_tqt(tde_hw_node * hw_node,tde_surface_msg * drv_surface,hi_tde_out_alpha_from alpha_from)780 hi_void tde_hal_node_set_tqt(tde_hw_node *hw_node, tde_surface_msg *drv_surface,
781 hi_tde_out_alpha_from alpha_from)
782 {
783 hi_u32 bpp;
784 hi_u64 phy_addr;
785 hi_u64 cb_crphy_addr;
786
787 if (hw_node == HI_NULL) {
788 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
789 return;
790 }
791 tde_hal_node_set_hw_node(hw_node, drv_surface, alpha_from);
792 if (drv_surface->color_fmt == TDE_DRV_COLOR_FMT_AYCBCR8888) {
793 drv_surface->color_fmt = TDE_DRV_COLOR_FMT_ARGB8888;
794 hw_node->des_ctrl.bits.des_argb_order = 0x17;
795 }
796
797 if ((drv_surface->color_fmt <= TDE_DRV_COLOR_FMT_RGB565) ||
798 (drv_surface->color_fmt == TDE_DRV_COLOR_FMT_AYCBCR8888)) {
799 hw_node->des_ctrl.bits.des_argb_order = drv_surface->rgb_order;
800 if (drv_surface->color_fmt == TDE_DRV_COLOR_FMT_AYCBCR8888) {
801 drv_surface->color_fmt = TDE_DRV_COLOR_FMT_ARGB8888;
802 hw_node->des_ctrl.bits.des_argb_order = 0x17;
803 }
804 }
805 if (drv_surface->color_fmt == TDE_DRV_COLOR_FMT_RABG8888) {
806 hw_node->des_ctrl.bits.des_argb_order = TDE_DRV_ORDER_RABG; /* RABG */
807 hw_node->des_ctrl.bits.des_fmt = TDE_DRV_COLOR_FMT_ARGB8888;
808 }
809
810 bpp = tde_hal_getbpp_by_fmt(drv_surface->color_fmt);
811 phy_addr = drv_surface->phy_addr + (hi_u64)(drv_surface->ypos) * (hi_u64)(drv_surface->pitch) +
812 (((hi_u64)(drv_surface->xpos) * (hi_u64)(bpp)) >> 3); /* 3 bpp narrow 8 */
813 hw_node->des_ch0_addr_low.bits.des_ch0_addr_low = GetLowAddr(phy_addr);
814 hw_node->des_ch0_addr_high.bits.des_ch0_addr_high = GetHighAddr(phy_addr);
815
816 cb_crphy_addr = drv_surface->cbcr_phy_addr + (hi_u64)(drv_surface->ypos) * (hi_u64)(drv_surface->pitch) +
817 (((hi_u64)(drv_surface->xpos) * (hi_u64)(bpp)) >> 3); /* 3 bpp narrow 8 */
818 hw_node->des_ch1_addr_low.bits.des_ch1_addr_low = GetLowAddr(cb_crphy_addr);
819 hw_node->des_ch1_addr_high.bits.des_ch1_addr_hi = GetHighAddr(cb_crphy_addr);
820
821 hw_node->des_ch1_stride.bits.des_ch1_stride = (hi_u32)drv_surface->pitch;
822
823 if (drv_surface->color_fmt == TDE_DRV_COLOR_FMT_YCBCR422) {
824 hw_node->des_dswm.bits.des_h_dswm_mode = 1;
825 }
826 hw_node->des_ch0_stride.bits.des_ch0_stride = (hi_u32)drv_surface->pitch;
827 return;
828 }
829
830 #if (TDE_CAPABILITY & COMPRESS)
831 #if (HICHIP == HI3519A_V100)
tde_hal_node_set_argb8888_320(tde_hw_node * hw_node)832 static hi_void tde_hal_node_set_argb8888_320(tde_hw_node *hw_node)
833 {
834 hw_node->tde_od_pic_osd_rc_cfg0.bits.budget_bits_mb = 994; /* 994 budget_bits_mb data */
835 hw_node->tde_od_pic_osd_rc_cfg0.bits.min_mb_bits = 750; /* 750 min_mb_bits data */
836
837 hw_node->tde_od_pic_osd_rc_cfg1.bits.budget_bits_mb_cap = 512; /* 512 budget_bits_mb_cap data */
838 hw_node->tde_od_pic_osd_rc_cfg7.bits.max_trow_bits = 0;
839
840 hw_node->tde_od_pic_osd_rc_cfg2.bits.max_qp = 5; /* 5 max_qp data */
841 hw_node->tde_od_pic_osd_rc_cfg2.bits.smth_qp = 2; /* 2 smth_qp data */
842 hw_node->tde_od_pic_osd_rc_cfg2.bits.sad_bits_ngain = 10; /* 10 sad_bits_ngain data */
843 hw_node->tde_od_pic_osd_rc_cfg2.bits.rc_smth_ngain = 4; /* 4 rc_smth_ngain data */
844 hw_node->tde_od_pic_osd_rc_cfg2.bits.special_bits_gain = 0;
845
846 hw_node->tde_od_pic_osd_rc_cfg3.bits.max_sad_thr = 64; /* 64 max_sad_thr data */
847 hw_node->tde_od_pic_osd_rc_cfg3.bits.min_sad_thr = 12; /* 12 min_sad_thr data */
848
849 hw_node->tde_od_pic_osd_rc_cfg4.bits.smth_thr = 3; /* 3 smth_thr data */
850 hw_node->tde_od_pic_osd_rc_cfg4.bits.still_thr = 1;
851 hw_node->tde_od_pic_osd_rc_cfg4.bits.big_grad_thr = 16; /* 16 big_grad_thr data */
852
853 hw_node->tde_od_pic_osd_rc_cfg5.bits.smth_pix_num_thr = 6; /* 6 smth_pix_num_thr data */
854 hw_node->tde_od_pic_osd_rc_cfg5.bits.still_pix_num_thr = 3; /* 3 still_pix_num_thr data */
855 hw_node->tde_od_pic_osd_rc_cfg5.bits.noise_pix_num_thr = 24; /* 24 noise_pix_num_thr data */
856 hw_node->tde_od_pic_osd_rc_cfg5.bits.large_smth_pix_num_thr = 10; /* 10 large_smth_pix_num_thr data */
857
858 hw_node->tde_od_pic_osd_rc_cfg6.bits.noise_sad = 32; /* 32 noise_sad data */
859 hw_node->tde_od_pic_osd_rc_cfg6.bits.pix_diff_thr = 50; /* 50 pix_diff_thr data */
860
861 hw_node->tde_od_pic_osd_rc_cfg7.bits.adj_sad_bits_thr = 0;
862
863 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_inc1_bits_thr = 0;
864 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec1_bits_thr = 60; /* 60 qp_dec1_bits_thr data */
865 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec2_bits_thr = 130; /* 130 qp_dec2_bits_thr data */
866 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec3_bits_thr = 250; /* 250 qp_dec3_bits_thr data */
867
868 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr = 70; /* 70 force_qp_thr data */
869 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr_cap = 20; /* 20 force_qp_thr_cap data */
870 }
871
tde_hal_node_set_argb8888_720(tde_hw_node * hw_node)872 static hi_void tde_hal_node_set_argb8888_720(tde_hw_node *hw_node)
873 {
874 hw_node->tde_od_pic_osd_rc_cfg0.bits.budget_bits_mb = 492; /* 492 budget_bits_mb data */
875 hw_node->tde_od_pic_osd_rc_cfg0.bits.min_mb_bits = 375; /* 375 min_mb_bits data */
876
877 hw_node->tde_od_pic_osd_rc_cfg1.bits.budget_bits_mb_cap = 512; /* 512 budget_bits_mb_cap data */
878 hw_node->tde_od_pic_osd_rc_cfg7.bits.max_trow_bits = 0;
879
880 hw_node->tde_od_pic_osd_rc_cfg2.bits.max_qp = 5; /* 5 max_qp data */
881 hw_node->tde_od_pic_osd_rc_cfg2.bits.smth_qp = 2; /* 2 smth_qp data */
882 hw_node->tde_od_pic_osd_rc_cfg2.bits.sad_bits_ngain = 10; /* 10 sad_bits_ngain data */
883 hw_node->tde_od_pic_osd_rc_cfg2.bits.rc_smth_ngain = 3; /* 3 rc_smth_ngain data */
884 hw_node->tde_od_pic_osd_rc_cfg2.bits.special_bits_gain = 0;
885
886 hw_node->tde_od_pic_osd_rc_cfg3.bits.max_sad_thr = 64; /* 64 max_sad_thr data */
887 hw_node->tde_od_pic_osd_rc_cfg3.bits.min_sad_thr = 12; /* 12 min_sad_thr data */
888
889 hw_node->tde_od_pic_osd_rc_cfg4.bits.smth_thr = 3; /* 3 smth_thr data */
890 hw_node->tde_od_pic_osd_rc_cfg4.bits.still_thr = 1;
891 hw_node->tde_od_pic_osd_rc_cfg4.bits.big_grad_thr = 16; /* 16 big_grad_thr data */
892
893 hw_node->tde_od_pic_osd_rc_cfg5.bits.smth_pix_num_thr = 6; /* 6 smth_pix_num_thr data */
894 hw_node->tde_od_pic_osd_rc_cfg5.bits.still_pix_num_thr = 3; /* 3 still_pix_num_thr data */
895 hw_node->tde_od_pic_osd_rc_cfg5.bits.noise_pix_num_thr = 24; /* 24 noise_pix_num_thr data */
896 hw_node->tde_od_pic_osd_rc_cfg5.bits.large_smth_pix_num_thr = 10; /* 10 large_smth_pix_num_thr data */
897
898 hw_node->tde_od_pic_osd_rc_cfg6.bits.noise_sad = 32; /* 32 noise_sad data */
899 hw_node->tde_od_pic_osd_rc_cfg6.bits.pix_diff_thr = 50; /* 50 pix_diff_thr data */
900
901 hw_node->tde_od_pic_osd_rc_cfg7.bits.adj_sad_bits_thr = 8; /* 8 adj_sad_bits_thr data */
902
903 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_inc1_bits_thr = 20; /* 20 qp_inc1_bits_thr data */
904 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec1_bits_thr = 60; /* 60 qp_dec1_bits_thr data */
905 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec2_bits_thr = 130; /* 130 qp_dec2_bits_thr data */
906 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec3_bits_thr = 250; /* 250 qp_dec3_bits_thr data */
907
908 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr = 70; /* 70 force_qp_thr data */
909 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr_cap = 20; /* 20 force_qp_thr_cap data */
910 }
911
tde_hal_node_set_argb8888_3840(tde_hw_node * hw_node)912 static hi_void tde_hal_node_set_argb8888_3840(tde_hw_node *hw_node)
913 {
914 hw_node->tde_od_pic_osd_rc_cfg0.bits.budget_bits_mb = 492; /* 492 budget_bits_mb data */
915 hw_node->tde_od_pic_osd_rc_cfg0.bits.min_mb_bits = 375; /* 375 min_mb_bits data */
916
917 hw_node->tde_od_pic_osd_rc_cfg1.bits.budget_bits_mb_cap = 512; /* 512 budget_bits_mb_cap data */
918 hw_node->tde_od_pic_osd_rc_cfg7.bits.max_trow_bits = 10; /* 10 max_trow_bits data */
919
920 hw_node->tde_od_pic_osd_rc_cfg2.bits.max_qp = 5; /* 5 max_qp data */
921 hw_node->tde_od_pic_osd_rc_cfg2.bits.smth_qp = 2; /* 2 smth_qp data */
922 hw_node->tde_od_pic_osd_rc_cfg2.bits.sad_bits_ngain = 10; /* 10 sad_bits_ngain data */
923 hw_node->tde_od_pic_osd_rc_cfg2.bits.rc_smth_ngain = 4; /* 4 rc_smth_ngain data */
924 hw_node->tde_od_pic_osd_rc_cfg2.bits.special_bits_gain = 4; /* 4 special_bits_gain data */
925
926 hw_node->tde_od_pic_osd_rc_cfg3.bits.max_sad_thr = 64; /* 64 max_sad_thr data */
927 hw_node->tde_od_pic_osd_rc_cfg3.bits.min_sad_thr = 12; /* 12 min_sad_thr data */
928
929 hw_node->tde_od_pic_osd_rc_cfg4.bits.smth_thr = 3; /* 3 smth_thr data */
930 hw_node->tde_od_pic_osd_rc_cfg4.bits.still_thr = 1;
931 hw_node->tde_od_pic_osd_rc_cfg4.bits.big_grad_thr = 16; /* 16 big_grad_thr data */
932
933 hw_node->tde_od_pic_osd_rc_cfg5.bits.smth_pix_num_thr = 6; /* 6 smth_pix_num_thr data */
934 hw_node->tde_od_pic_osd_rc_cfg5.bits.still_pix_num_thr = 3; /* 3 still_pix_num_thr data */
935 hw_node->tde_od_pic_osd_rc_cfg5.bits.noise_pix_num_thr = 24; /* 24 noise_pix_num_thr data */
936 hw_node->tde_od_pic_osd_rc_cfg5.bits.large_smth_pix_num_thr = 10; /* 10 large_smth_pix_num_thr data */
937
938 hw_node->tde_od_pic_osd_rc_cfg6.bits.noise_sad = 32; /* 32 noise_sad data */
939 hw_node->tde_od_pic_osd_rc_cfg6.bits.pix_diff_thr = 50; /* 50 pix_diff_thr data */
940
941 hw_node->tde_od_pic_osd_rc_cfg7.bits.adj_sad_bits_thr = 30; /* 30 adj_sad_bits_thr data */
942
943 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_inc1_bits_thr = 40; /* 40 qp_inc1_bits_thr data */
944 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec1_bits_thr = 60; /* 60 qp_dec1_bits_thr data */
945 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec2_bits_thr = 100; /* 100 qp_dec2_bits_thr data */
946 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec3_bits_thr = 250; /* 250 qp_dec3_bits_thr data */
947
948 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr = 70; /* 70 force_qp_thr data */
949 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr_cap = 20; /* 20 force_qp_thr_cap data */
950 }
951
tde_hal_node_set_rgb888_320(tde_hw_node * hw_node)952 static hi_void tde_hal_node_set_rgb888_320(tde_hw_node *hw_node)
953 {
954 hw_node->tde_od_pic_osd_rc_cfg0.bits.budget_bits_mb = 930; /* 930 budget_bits_mb data */
955 hw_node->tde_od_pic_osd_rc_cfg0.bits.min_mb_bits = 702; /* 702 min_mb_bits data */
956
957 hw_node->tde_od_pic_osd_rc_cfg1.bits.budget_bits_mb_cap = 512; /* 512 budget_bits_mb_cap data */
958 hw_node->tde_od_pic_osd_rc_cfg7.bits.max_trow_bits = 0;
959
960 hw_node->tde_od_pic_osd_rc_cfg2.bits.max_qp = 4; /* 4 max_qp data */
961 hw_node->tde_od_pic_osd_rc_cfg2.bits.smth_qp = 2; /* 2 smth_qp data */
962 hw_node->tde_od_pic_osd_rc_cfg2.bits.sad_bits_ngain = 10; /* 10 sad_bits_ngain data */
963 hw_node->tde_od_pic_osd_rc_cfg2.bits.rc_smth_ngain = 4; /* 4 rc_smth_ngain data */
964 hw_node->tde_od_pic_osd_rc_cfg2.bits.special_bits_gain = 0;
965
966 hw_node->tde_od_pic_osd_rc_cfg3.bits.max_sad_thr = 64; /* 64 max_sad_thr data */
967 hw_node->tde_od_pic_osd_rc_cfg3.bits.min_sad_thr = 12; /* 12 min_sad_thr data */
968
969 hw_node->tde_od_pic_osd_rc_cfg4.bits.smth_thr = 3; /* 3 smth_thr data */
970 hw_node->tde_od_pic_osd_rc_cfg4.bits.still_thr = 1;
971 hw_node->tde_od_pic_osd_rc_cfg4.bits.big_grad_thr = 16; /* 16 big_grad_thr data */
972
973 hw_node->tde_od_pic_osd_rc_cfg5.bits.smth_pix_num_thr = 6; /* 6 smth_pix_num_thr data */
974 hw_node->tde_od_pic_osd_rc_cfg5.bits.still_pix_num_thr = 3; /* 3 still_pix_num_thr data */
975 hw_node->tde_od_pic_osd_rc_cfg5.bits.noise_pix_num_thr = 24; /* 24 noise_pix_num_thr data */
976 hw_node->tde_od_pic_osd_rc_cfg5.bits.large_smth_pix_num_thr = 10; /* 10 large_smth_pix_num_thr data */
977
978 hw_node->tde_od_pic_osd_rc_cfg6.bits.noise_sad = 32; /* 32 noise_sad data */
979 hw_node->tde_od_pic_osd_rc_cfg6.bits.pix_diff_thr = 50; /* 50 pix_diff_thr data */
980
981 hw_node->tde_od_pic_osd_rc_cfg7.bits.adj_sad_bits_thr = 0;
982
983 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_inc1_bits_thr = 0;
984 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec1_bits_thr = 60; /* 60 qp_dec1_bits_thr data */
985 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec2_bits_thr = 130; /* 130 qp_dec2_bits_thr data */
986 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec3_bits_thr = 250; /* 250 qp_dec3_bits_thr data */
987
988 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr = 70; /* 70 force_qp_thr data */
989 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr_cap = 20; /* 20 force_qp_thr_cap data */
990 }
991
tde_hal_node_set_rgb888_720(tde_hw_node * hw_node)992 static hi_void tde_hal_node_set_rgb888_720(tde_hw_node *hw_node)
993 {
994 hw_node->tde_od_pic_osd_rc_cfg0.bits.budget_bits_mb = 500; /* 500 budget_bits_mb data */
995 hw_node->tde_od_pic_osd_rc_cfg0.bits.min_mb_bits = 375; /* 375 min_mb_bits data */
996
997 hw_node->tde_od_pic_osd_rc_cfg1.bits.budget_bits_mb_cap = 512; /* 512 budget_bits_mb_cap data */
998 hw_node->tde_od_pic_osd_rc_cfg7.bits.max_trow_bits = 0;
999
1000 hw_node->tde_od_pic_osd_rc_cfg2.bits.max_qp = 4; /* 4 max_qp data */
1001 hw_node->tde_od_pic_osd_rc_cfg2.bits.smth_qp = 2; /* 2 smth_qp data */
1002 hw_node->tde_od_pic_osd_rc_cfg2.bits.sad_bits_ngain = 10; /* 10 sad_bits_ngain data */
1003 hw_node->tde_od_pic_osd_rc_cfg2.bits.rc_smth_ngain = 3; /* 3 rc_smth_ngain data */
1004 hw_node->tde_od_pic_osd_rc_cfg2.bits.special_bits_gain = 0;
1005
1006 hw_node->tde_od_pic_osd_rc_cfg3.bits.max_sad_thr = 64; /* 64 max_sad_thr data */
1007 hw_node->tde_od_pic_osd_rc_cfg3.bits.min_sad_thr = 12; /* 12 min_sad_thr data */
1008
1009 hw_node->tde_od_pic_osd_rc_cfg4.bits.smth_thr = 3; /* 3 smth_thr data */
1010 hw_node->tde_od_pic_osd_rc_cfg4.bits.still_thr = 1;
1011 hw_node->tde_od_pic_osd_rc_cfg4.bits.big_grad_thr = 16; /* 16 big_grad_thr data */
1012
1013 hw_node->tde_od_pic_osd_rc_cfg5.bits.smth_pix_num_thr = 6; /* 6 smth_pix_num_thr data */
1014 hw_node->tde_od_pic_osd_rc_cfg5.bits.still_pix_num_thr = 3; /* 3 still_pix_num_thr data */
1015 hw_node->tde_od_pic_osd_rc_cfg5.bits.noise_pix_num_thr = 24; /* 24 noise_pix_num_thr data */
1016 hw_node->tde_od_pic_osd_rc_cfg5.bits.large_smth_pix_num_thr = 10; /* 10 large_smth_pix_num_thr data */
1017
1018 hw_node->tde_od_pic_osd_rc_cfg6.bits.noise_sad = 32; /* 32 noise_sad data */
1019 hw_node->tde_od_pic_osd_rc_cfg6.bits.pix_diff_thr = 50; /* 50 pix_diff_thr data */
1020
1021 hw_node->tde_od_pic_osd_rc_cfg7.bits.adj_sad_bits_thr = 8; /* 8 adj_sad_bits_thr data */
1022
1023 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_inc1_bits_thr = 20; /* 20 qp_inc1_bits_thr data */
1024 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec1_bits_thr = 60; /* 60 qp_dec1_bits_thr data */
1025 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec2_bits_thr = 130; /* 130 qp_dec2_bits_thr data */
1026 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec3_bits_thr = 250; /* 250 qp_dec3_bits_thr data */
1027
1028 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr = 70; /* 70 force_qp_thr data */
1029 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr_cap = 20; /* 20 force_qp_thr_cap data */
1030 }
1031
tde_hal_node_set_rgb888_3840(tde_hw_node * hw_node)1032 static hi_void tde_hal_node_set_rgb888_3840(tde_hw_node *hw_node)
1033 {
1034 hw_node->tde_od_pic_osd_rc_cfg0.bits.budget_bits_mb = 500; /* 500 budget_bits_mb data */
1035 hw_node->tde_od_pic_osd_rc_cfg0.bits.min_mb_bits = 375; /* 375 min_mb_bits data */
1036
1037 hw_node->tde_od_pic_osd_rc_cfg1.bits.budget_bits_mb_cap = 512; /* 512 budget_bits_mb_cap data */
1038 hw_node->tde_od_pic_osd_rc_cfg7.bits.max_trow_bits = 10; /* 10 max_trow_bits data */
1039
1040 hw_node->tde_od_pic_osd_rc_cfg2.bits.max_qp = 4; /* 4 max_qp data */
1041 hw_node->tde_od_pic_osd_rc_cfg2.bits.smth_qp = 2; /* 2 smth_qp data */
1042 hw_node->tde_od_pic_osd_rc_cfg2.bits.sad_bits_ngain = 10; /* 10 sad_bits_ngain data */
1043 hw_node->tde_od_pic_osd_rc_cfg2.bits.rc_smth_ngain = 4; /* 4 rc_smth_ngain data */
1044 hw_node->tde_od_pic_osd_rc_cfg2.bits.special_bits_gain = 4; /* 4 special_bits_gain data */
1045
1046 hw_node->tde_od_pic_osd_rc_cfg3.bits.max_sad_thr = 64; /* 64 max_sad_thr data */
1047 hw_node->tde_od_pic_osd_rc_cfg3.bits.min_sad_thr = 12; /* 12 min_sad_thr data */
1048
1049 hw_node->tde_od_pic_osd_rc_cfg4.bits.smth_thr = 3; /* 3 smth_thr data */
1050 hw_node->tde_od_pic_osd_rc_cfg4.bits.still_thr = 1;
1051 hw_node->tde_od_pic_osd_rc_cfg4.bits.big_grad_thr = 16; /* 16 big_grad_thr data */
1052
1053 hw_node->tde_od_pic_osd_rc_cfg5.bits.smth_pix_num_thr = 6; /* 6 smth_pix_num_thr data */
1054 hw_node->tde_od_pic_osd_rc_cfg5.bits.still_pix_num_thr = 3; /* 3 still_pix_num_thr data */
1055 hw_node->tde_od_pic_osd_rc_cfg5.bits.noise_pix_num_thr = 24; /* 24 noise_pix_num_thr data */
1056 hw_node->tde_od_pic_osd_rc_cfg5.bits.large_smth_pix_num_thr = 10; /* 10 large_smth_pix_num_thr data */
1057
1058 hw_node->tde_od_pic_osd_rc_cfg6.bits.noise_sad = 32; /* 32 noise_sad data */
1059 hw_node->tde_od_pic_osd_rc_cfg6.bits.pix_diff_thr = 50; /* 50 pix_diff_thr data */
1060
1061 hw_node->tde_od_pic_osd_rc_cfg7.bits.adj_sad_bits_thr = 30; /* 30 adj_sad_bits_thr data */
1062
1063 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_inc1_bits_thr = 40; /* 40 qp_inc1_bits_thr data */
1064 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec1_bits_thr = 60; /* 60 qp_dec1_bits_thr data */
1065 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec2_bits_thr = 100; /* 100 qp_dec2_bits_thr data */
1066 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec3_bits_thr = 250; /* 250 qp_dec3_bits_thr data */
1067
1068 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr = 70; /* 70 force_qp_thr data */
1069 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr_cap = 20; /* 20 force_qp_thr_cap data */
1070 }
1071
tde_hal_node_set_argb15555_or_argb4444_720(tde_hw_node * hw_node)1072 static hi_void tde_hal_node_set_argb15555_or_argb4444_720(tde_hw_node *hw_node)
1073 {
1074 hw_node->tde_od_pic_osd_rc_cfg0.bits.budget_bits_mb = 492; /* 492 budget_bits_mb data */
1075 hw_node->tde_od_pic_osd_rc_cfg0.bits.min_mb_bits = 375; /* 375 min_mb_bits data */
1076
1077 hw_node->tde_od_pic_osd_rc_cfg1.bits.budget_bits_mb_cap = 512; /* 512 budget_bits_mb_cap data */
1078 hw_node->tde_od_pic_osd_rc_cfg7.bits.max_trow_bits = 10; /* 10 max_trow_bits data */
1079
1080 hw_node->tde_od_pic_osd_rc_cfg2.bits.max_qp = 1;
1081 hw_node->tde_od_pic_osd_rc_cfg2.bits.smth_qp = 2; /* 2 smth_qp data */
1082 hw_node->tde_od_pic_osd_rc_cfg2.bits.sad_bits_ngain = 10; /* 10 sad_bits_ngain data */
1083 hw_node->tde_od_pic_osd_rc_cfg2.bits.rc_smth_ngain = 3; /* 3 rc_smth_ngain data */
1084 hw_node->tde_od_pic_osd_rc_cfg2.bits.special_bits_gain = 2; /* 2 special_bits_gain data */
1085
1086 hw_node->tde_od_pic_osd_rc_cfg3.bits.max_sad_thr = 64; /* 64 max_sad_thr data */
1087 hw_node->tde_od_pic_osd_rc_cfg3.bits.min_sad_thr = 12; /* 12 min_sad_thr data */
1088
1089 hw_node->tde_od_pic_osd_rc_cfg4.bits.smth_thr = 3; /* 3 smth_thr data */
1090 hw_node->tde_od_pic_osd_rc_cfg4.bits.still_thr = 1;
1091 hw_node->tde_od_pic_osd_rc_cfg4.bits.big_grad_thr = 16; /* 16 big_grad_thr data */
1092
1093 hw_node->tde_od_pic_osd_rc_cfg5.bits.smth_pix_num_thr = 6; /* 6 smth_pix_num_thr data */
1094 hw_node->tde_od_pic_osd_rc_cfg5.bits.still_pix_num_thr = 3; /* 3 still_pix_num_thr data */
1095 hw_node->tde_od_pic_osd_rc_cfg5.bits.noise_pix_num_thr = 24; /* 24 noise_pix_num_thr data */
1096 hw_node->tde_od_pic_osd_rc_cfg5.bits.large_smth_pix_num_thr = 10; /* 10 large_smth_pix_num_thr data */
1097
1098 hw_node->tde_od_pic_osd_rc_cfg6.bits.noise_sad = 32; /* 32 noise_sad data */
1099 hw_node->tde_od_pic_osd_rc_cfg6.bits.pix_diff_thr = 50; /* 50 pix_diff_thr data */
1100
1101 hw_node->tde_od_pic_osd_rc_cfg7.bits.adj_sad_bits_thr = 10; /* 10 adj_sad_bits_thr data */
1102
1103 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_inc1_bits_thr = 20; /* 20 qp_inc1_bits_thr data */
1104 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec1_bits_thr = 60; /* 60 qp_dec1_bits_thr data */
1105 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec2_bits_thr = 100; /* 100 qp_dec2_bits_thr data */
1106 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec3_bits_thr = 130; /* 130 qp_dec3_bits_thr data */
1107
1108 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr = 70; /* 70 force_qp_thr data */
1109 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr_cap = 20; /* 20 force_qp_thr_cap data */
1110 }
1111
tde_hal_node_set_argb15555_or_argb4444_3840(tde_hw_node * hw_node)1112 static hi_void tde_hal_node_set_argb15555_or_argb4444_3840(tde_hw_node *hw_node)
1113 {
1114 hw_node->tde_od_pic_osd_rc_cfg0.bits.budget_bits_mb = 492; /* 492 budget_bits_mb data */
1115 hw_node->tde_od_pic_osd_rc_cfg0.bits.min_mb_bits = 375; /* 375 min_mb_bits data */
1116
1117 hw_node->tde_od_pic_osd_rc_cfg1.bits.budget_bits_mb_cap = 512; /* 512 budget_bits_mb_cap data */
1118 hw_node->tde_od_pic_osd_rc_cfg7.bits.max_trow_bits = 10; /* 10 max_trow_bits data */
1119
1120 hw_node->tde_od_pic_osd_rc_cfg2.bits.max_qp = 1;
1121 hw_node->tde_od_pic_osd_rc_cfg2.bits.smth_qp = 2; /* 2 smth_qp data */
1122
1123 hw_node->tde_od_pic_osd_rc_cfg2.bits.sad_bits_ngain = 10; /* 10 sad_bits_ngain data */
1124 hw_node->tde_od_pic_osd_rc_cfg2.bits.rc_smth_ngain = 3; /* 3 rc_smth_ngain data */
1125 hw_node->tde_od_pic_osd_rc_cfg2.bits.special_bits_gain = 2; /* 2 special_bits_gain data */
1126
1127 hw_node->tde_od_pic_osd_rc_cfg3.bits.max_sad_thr = 64; /* 64 max_sad_thr data */
1128 hw_node->tde_od_pic_osd_rc_cfg3.bits.min_sad_thr = 12; /* 12 min_sad_thr data */
1129
1130 hw_node->tde_od_pic_osd_rc_cfg4.bits.smth_thr = 3; /* 3 smth_thr data */
1131 hw_node->tde_od_pic_osd_rc_cfg4.bits.still_thr = 1;
1132 hw_node->tde_od_pic_osd_rc_cfg4.bits.big_grad_thr = 16; /* 16 big_grad_thr data */
1133
1134 hw_node->tde_od_pic_osd_rc_cfg5.bits.smth_pix_num_thr = 6; /* 6 smth_pix_num_thr data */
1135 hw_node->tde_od_pic_osd_rc_cfg5.bits.still_pix_num_thr = 3; /* 3 still_pix_num_thr data */
1136 hw_node->tde_od_pic_osd_rc_cfg5.bits.noise_pix_num_thr = 24; /* 24 noise_pix_num_thr data */
1137 hw_node->tde_od_pic_osd_rc_cfg5.bits.large_smth_pix_num_thr = 10; /* 10 large_smth_pix_num_thr data */
1138
1139 hw_node->tde_od_pic_osd_rc_cfg6.bits.noise_sad = 32; /* 32 noise_sad data */
1140 hw_node->tde_od_pic_osd_rc_cfg6.bits.pix_diff_thr = 50; /* 50 pix_diff_thr data */
1141
1142 hw_node->tde_od_pic_osd_rc_cfg7.bits.adj_sad_bits_thr = 10; /* 10 adj_sad_bits_thr data */
1143
1144 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_inc1_bits_thr = 20; /* 20 qp_inc1_bits_thr data */
1145 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec1_bits_thr = 60; /* 60 qp_dec1_bits_thr data */
1146 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec2_bits_thr = 100; /* 100 qp_dec2_bits_thr data */
1147 hw_node->tde_od_pic_osd_rc_cfg8.bits.qp_dec3_bits_thr = 130; /* 130 qp_dec3_bits_thr data */
1148
1149 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr = 70; /* 70 force_qp_thr data */
1150 hw_node->tde_od_pic_osd_rc_cfg9.bits.force_qp_thr_cap = 20; /* 20 force_qp_thr_cap data */
1151 }
1152
tde_hal_node_set_compress(tde_hw_node * hw_node)1153 hi_void tde_hal_node_set_compress(tde_hw_node *hw_node)
1154 {
1155 if (hw_node == HI_NULL) {
1156 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1157 return;
1158 }
1159
1160 hw_node->tde_od_pic_osd_glb_info.bits.is_lossless = 0;
1161 hw_node->tde_od_pic_osd_glb_info.bits.is_lossless_alpha = hw_node->tde_od_pic_osd_glb_info.bits.is_lossless;
1162 hw_node->tde_od_pic_osd_glb_info.bits.cmp_mode = 0;
1163 hw_node->tde_od_pic_osd_glb_info.bits.osd_mode =
1164 (hw_node->des_ctrl.bits.des_fmt == TDE_DRV_COLOR_FMT_ARGB8888) ? 0 :
1165 (hw_node->des_ctrl.bits.des_fmt == TDE_DRV_COLOR_FMT_RGB888 ? 1 :
1166 ((hw_node->des_ctrl.bits.des_fmt == TDE_DRV_COLOR_FMT_ARGB1555) ? 2 : 3)); /* 2 3 des_fmt value */
1167 hw_node->tde_od_pic_osd_glb_info.bits.partition_en = 0;
1168 hw_node->tde_od_pic_osd_glb_info.bits.part_num = 1;
1169
1170 hw_node->tde_od_pic_osd_frame_size.bits.frame_width = hw_node->des_imgsize.bits.des_width;
1171 hw_node->tde_od_pic_osd_frame_size.bits.frame_height = hw_node->des_imgsize.bits.des_height;
1172
1173 if (hw_node->des_ctrl.bits.des_fmt == TDE_DRV_COLOR_FMT_ARGB8888) {
1174 if (hw_node->des_imgsize.bits.des_width <= 320) { /* 320 set argb8888 */
1175 tde_hal_node_set_argb8888_320(hw_node);
1176 } else if (hw_node->des_imgsize.bits.des_width <= 720) { /* 720 set argb8888 */
1177 tde_hal_node_set_argb8888_720(hw_node);
1178 } else if (hw_node->des_imgsize.bits.des_width <= 3840) { /* 3840 set argb8888 */
1179 tde_hal_node_set_argb8888_3840(hw_node);
1180 }
1181 } else if (hw_node->des_ctrl.bits.des_fmt == TDE_DRV_COLOR_FMT_RGB888) {
1182 if (hw_node->des_imgsize.bits.des_width <= 320) { /* 320 set rgb888 */
1183 tde_hal_node_set_rgb888_320(hw_node);
1184 } else if (hw_node->des_imgsize.bits.des_width <= 720) { /* 720 set rgb888 */
1185 tde_hal_node_set_rgb888_720(hw_node);
1186 } else if (hw_node->des_imgsize.bits.des_width <= 3840) { /* 3840 set rgb888 */
1187 tde_hal_node_set_rgb888_3840(hw_node);
1188 }
1189 } else if ((hw_node->des_ctrl.bits.des_fmt == TDE_DRV_COLOR_FMT_ARGB1555) ||
1190 (hw_node->des_ctrl.bits.des_fmt == TDE_DRV_COLOR_FMT_ARGB4444)) {
1191 if (hw_node->des_imgsize.bits.des_width <= 720) { /* 720 set argb15555 or argb4444 */
1192 tde_hal_node_set_argb15555_or_argb4444_720(hw_node);
1193 } else if (hw_node->des_imgsize.bits.des_width <= 3840) { /* 3840 set argb15555 or argb4444 */
1194 tde_hal_node_set_argb15555_or_argb4444_3840(hw_node);
1195 }
1196 }
1197 }
1198 #else
tde_hal_node_set_cfgxx(tde_hw_node * hw_node)1199 static hi_void tde_hal_node_set_cfgxx(tde_hw_node *hw_node)
1200 {
1201 hw_node->tde_od_pic_osd_rc_cfg10.bits.qp_thr0 = 2; /* 2 qp_thr0 data */
1202 hw_node->tde_od_pic_osd_rc_cfg10.bits.qp_thr1 = 1;
1203 /* 2 3 qp_thr2 data */
1204 hw_node->tde_od_pic_osd_rc_cfg10.bits.qp_thr2 = ((hw_node->tde_od_pic_osd_glb_info.bits.source_mode == 2) ? 2 : 3);
1205
1206 hw_node->tde_od_pic_osd_rc_cfg11.bits.grph_bias_bit_thr0 = 20; /* 20 grph_bias_bit_thr0 data */
1207 hw_node->tde_od_pic_osd_rc_cfg11.bits.grph_bias_bit_thr1 = 50; /* 50 grph_bias_bit_thr1 data */
1208
1209 hw_node->tde_od_pic_osd_rc_cfg12.bits.force_rc_en = 0;
1210 hw_node->tde_od_pic_osd_rc_cfg12.bits.forcerc_bits_diff_thr = 80; /* 80 forcerc_bits_diff_thr data */
1211
1212 hw_node->tde_od_pic_osd_rc_cfg13.bits.maxdiff_ctrl_en = 1;
1213
1214 hw_node->tde_od_pic_osd_rc_cfg14.bits.init_buf_bits_cap = 2047; /* 2047 init_buf_bits_cap data */
1215
1216 hw_node->tde_od_pic_osd_rc_cfg15.bits.cmplx_sad_thr = 10; /* 10 cmplx_sad_thr data */
1217 hw_node->tde_od_pic_osd_rc_cfg15.bits.err_thr0 = 2; /* 2 err_thr0 data */
1218 hw_node->tde_od_pic_osd_rc_cfg15.bits.err_thr1 = 5; /* 5 err_thr1 data */
1219
1220 hw_node->tde_od_pic_osd_rc_cfg16.bits.sim_num_thr = 3; /* 3 sim_num_thr data */
1221 hw_node->tde_od_pic_osd_rc_cfg16.bits.sum_y_err_thr = 40; /* 40 sum_y_err_thr data */
1222 hw_node->tde_od_pic_osd_rc_cfg16.bits.sum_c_err_thr = 24; /* 24 sum_c_err_thr data */
1223
1224 hw_node->tde_od_pic_osd_rc_cfg17.bits.cpmlx_sad_thr_y = 12; /* 12 cpmlx_sad_thr_y data */
1225 hw_node->tde_od_pic_osd_rc_cfg17.bits.smpl_sad_thr_c = 3; /* 3 smpl_sad_thr_c data */
1226 hw_node->tde_od_pic_osd_rc_cfg17.bits.smpl_sumsad_thr_y = 50; /* 50 smpl_sumsad_thr_y data */
1227 hw_node->tde_od_pic_osd_rc_cfg17.bits.smpl_sumsad_thr_c = 40; /* 40 smpl_sumsad_thr_c data */
1228
1229 hw_node->tde_od_pic_osd_rc_cfg18.bits.future_sad_y_thr0 = 14; /* 14 future_sad_y_thr0 data */
1230 hw_node->tde_od_pic_osd_rc_cfg18.bits.future_sad_c_thr0 = 14; /* 14 future_sad_c_thr0 data */
1231 hw_node->tde_od_pic_osd_rc_cfg18.bits.future_sad_y_thr1 = 14; /* 14 future_sad_y_thr1 data */
1232 hw_node->tde_od_pic_osd_rc_cfg18.bits.future_sad_c_thr1 = 4; /* 4 future_sad_c_thr1 data */
1233
1234 hw_node->tde_od_pic_osd_rc_cfg19.bits.cmplx_sumsad_thr_y = 160; /* 160 cmplx_sumsad_thr_y data */
1235 hw_node->tde_od_pic_osd_rc_cfg19.bits.cmplx_sumsad_thr_c = 100; /* 100 cmplx_sumsad_thr_c data */
1236
1237 hw_node->tde_od_pic_osd_rc_cfg20.bits.buffer_up_lmt_thr = 4095; /* 4095 buffer_up_lmt_thr data */
1238 hw_node->tde_od_pic_osd_rc_cfg20.bits.buffer_low_lmt_thr = 2048; /* 2048 buffer_low_lmt_thr data */
1239
1240 hw_node->tde_od_pic_osd_rc_cfg21.bits.buffer_adj_qp_thr0 = 2; /* 2 buffer_adj_qp_thr0 data */
1241 hw_node->tde_od_pic_osd_rc_cfg21.bits.buffer_adj_qp_thr1 = 3; /* 3 buffer_adj_qp_thr1 data */
1242 hw_node->tde_od_pic_osd_rc_cfg21.bits.buffer_adj_qp_thr2 = 4; /* 4 buffer_adj_qp_thr2 data */
1243
1244 hw_node->tde_od_pic_osd_rc_cfg22.bits.buffer_surplus_thr0 = 180; /* 180 buffer_surplus_thr0 data */
1245 hw_node->tde_od_pic_osd_rc_cfg22.bits.buffer_surplus_thr1 = 50; /* 50 buffer_surplus_thr1 data */
1246 hw_node->tde_od_pic_osd_rc_cfg22.bits.buffer_surplus_thr2 = 10; /* 10 buffer_surplus_thr2 data */
1247
1248 hw_node->tde_od_pic_osd_rc_cfg23.bits.offset_bits_thr = 128; /* 128 offset_bits_thr data */
1249
1250 hw_node->tde_od_pic_osd_stat_thr.bits.max_gap_bw_row_len_thr = 0x40;
1251 }
1252
tde_hal_node_set_cfg0x(tde_hw_node * hw_node)1253 static hi_void tde_hal_node_set_cfg0x(tde_hw_node *hw_node)
1254 {
1255 hw_node->tde_od_pic_osd_glb_info.bits.cmp_mode = 0;
1256 hw_node->tde_od_pic_osd_glb_info.bits.top_pred_en = 1;
1257 hw_node->tde_od_pic_osd_glb_info.bits.is_lossless = 0;
1258 hw_node->tde_od_pic_osd_glb_info.bits.is_lossless_a = 0;
1259 hw_node->tde_od_pic_osd_glb_info.bits.graphic_en = 1;
1260
1261 hw_node->tde_od_pic_osd_frame_size.bits.frame_width = hw_node->des_imgsize.bits.des_width;
1262 hw_node->tde_od_pic_osd_frame_size.bits.frame_height = hw_node->des_imgsize.bits.des_height;
1263
1264 hw_node->tde_od_pic_osd_rc_cfg1.bits.sad_bits_gain = 8; /* 8 sad_bits_gain data */
1265 hw_node->tde_od_pic_osd_rc_cfg1.bits.rc_smth_ngain = 4; /* 4 rc_smth_ngain data */
1266 hw_node->tde_od_pic_osd_rc_cfg1.bits.max_trow_bits = 10; /* 10 max_trow_bits data */
1267
1268 hw_node->tde_od_pic_osd_rc_cfg2.bits.max_sad_thr = 64; /* 64 max_sad_thr data */
1269 hw_node->tde_od_pic_osd_rc_cfg2.bits.min_sad_thr = 16; /* 16 min_sad_thr data */
1270
1271 hw_node->tde_od_pic_osd_rc_cfg3.bits.smth_thr = 3; /* 3 smth_thr data */
1272 hw_node->tde_od_pic_osd_rc_cfg3.bits.still_thr = 1;
1273 hw_node->tde_od_pic_osd_rc_cfg3.bits.big_grad_thr = 16; /* 16 big_grad_thr data */
1274
1275 hw_node->tde_od_pic_osd_rc_cfg4.bits.smth_pix_num_thr = 32; /* 32 smth_pix_num_thr data */
1276 hw_node->tde_od_pic_osd_rc_cfg4.bits.still_pix_num_thr = 32; /* 32 still_pix_num_thr data */
1277 hw_node->tde_od_pic_osd_rc_cfg4.bits.noise_pix_num_thr = 32; /* 32 noise_pix_num_thr data */
1278
1279 hw_node->tde_od_pic_osd_rc_cfg5.bits.noise_sad = 32; /* 32 noise_sad data */
1280 hw_node->tde_od_pic_osd_rc_cfg5.bits.pix_diff_thr = 50; /* 50 pix_diff_thr data */
1281
1282 hw_node->tde_od_pic_osd_rc_cfg6.bits.adj_sad_bits_thr = 0;
1283
1284 hw_node->tde_od_pic_osd_rc_cfg7.bits.qp_inc1_bits_thr = 62; /* 62 qp_inc1_bits_thr data */
1285 hw_node->tde_od_pic_osd_rc_cfg7.bits.qp_inc2_bits_thr = 180; /* 180 qp_inc2_bits_thr data */
1286 hw_node->tde_od_pic_osd_rc_cfg7.bits.qp_dec1_bits_thr = 64; /* 64 qp_dec1_bits_thr data */
1287 hw_node->tde_od_pic_osd_rc_cfg7.bits.qp_dec2_bits_thr = 150; /* 150 qp_dec2_bits_thr data */
1288
1289 hw_node->tde_od_pic_osd_rc_cfg8.bits.est_err_gain = 7; /* 7 est_err_gain data */
1290 hw_node->tde_od_pic_osd_rc_cfg8.bits.max_est_err_level = 128; /* 128 max_est_err_level data */
1291
1292 hw_node->tde_od_pic_osd_rc_cfg9.bits.vbv_buf_loss1_thr = 62; /* 62 vbv_buf_loss1_thr data */
1293 hw_node->tde_od_pic_osd_rc_cfg9.bits.vbv_buf_loss2_thr = 67; /* 67 vbv_buf_loss2_thr data */
1294 }
1295
tde_hal_node_get_ratio(tde_hw_node * hw_node,hi_u32 * cmp_ratio,hi_u32 * cmp_ratio_frm,hi_s32 * mb_org_bits)1296 static hi_s32 tde_hal_node_get_ratio(tde_hw_node *hw_node, hi_u32 *cmp_ratio, hi_u32 *cmp_ratio_frm,
1297 hi_s32 *mb_org_bits)
1298 {
1299 if (hw_node->des_ctrl.bits.des_fmt == TDE_DRV_COLOR_FMT_ARGB8888) {
1300 hw_node->tde_od_pic_osd_glb_info.bits.source_mode = 0;
1301 *cmp_ratio = 10 * 100; /* 10 1000 s32cmp_ratio data */
1302 *cmp_ratio_frm = 20 * 100; /* 20 100 s32cmp_ratio_frm data */
1303 *mb_org_bits = 32 * (8 + 8 + 8 + 8); /* 8 32 mb_org_bits data */
1304 } else if (hw_node->des_ctrl.bits.des_fmt == TDE_DRV_COLOR_FMT_ARGB1555) {
1305 hw_node->tde_od_pic_osd_glb_info.bits.source_mode = 1;
1306 *cmp_ratio = 20 * 100; /* 20 100 s32cmp_ratio data */
1307 *cmp_ratio_frm = 2.0 * 100; /* 2.0 100 s32cmp_ratio_frm data */
1308 *mb_org_bits = 32 * (1 + 5 + 5 + 5); /* 32 5 mb_org_bits data */
1309 } else if (hw_node->des_ctrl.bits.des_fmt == TDE_DRV_COLOR_FMT_ARGB4444) {
1310 hw_node->tde_od_pic_osd_glb_info.bits.source_mode = 2; /* 2 source_mode data */
1311 *cmp_ratio = 1.5 * 100; /* 1.5 * 100 s32cmp_ratio data */
1312 *cmp_ratio_frm = 1.92 * 100; /* 1.92 * 100 s32cmp_ratio_frm data */
1313 *mb_org_bits = 32 * (4 + 4 + 4 + 4); /* 4 32 mb_org_bits data */
1314 } else {
1315 tde_error("compress unsupported format except argb\n");
1316 return HI_FAILURE;
1317 }
1318 return HI_SUCCESS;
1319 }
1320
tde_hal_node_frm_width(tde_hw_node * hw_node,hi_s32 * frm_width,hi_s32 * frm_width_r)1321 static hi_void tde_hal_node_frm_width(tde_hw_node *hw_node, hi_s32 *frm_width, hi_s32 *frm_width_r)
1322 {
1323 hi_s32 spilt_num;
1324 spilt_num = (hw_node->tde_od_pic_osd_frame_size.bits.frame_width + 15) / 16; /* 15 16 for more than */
1325 if (((hi_u32)spilt_num & 0x1) == 0) {
1326 *frm_width = (spilt_num / 2) * 16; /* 2 16 four left data */
1327 *frm_width_r = hw_node->tde_od_pic_osd_frame_size.bits.frame_width - *frm_width;
1328 } else {
1329 *frm_width_r = (spilt_num / 2) * 16; /* 2 16 four left data */
1330 *frm_width = hw_node->tde_od_pic_osd_frame_size.bits.frame_width - *frm_width_r;
1331 }
1332 }
1333
tde_hal_node_set_compress(tde_hw_node * hw_node)1334 hi_void tde_hal_node_set_compress(tde_hw_node *hw_node)
1335 {
1336 hi_u32 mb_num_x, cmp_ratio, cmp_ratio_frm;
1337 hi_s32 mb_minu10, mb_bits, mb_bits_cap, ctl_delta, mb_org_bits, line_delta, ret;
1338 hi_s32 frm_width, frm_width_r;
1339
1340 /* set bitmap attribute info, CNcomment: Configure attribute information source bitmap */
1341 if (hw_node == HI_NULL) {
1342 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1343 return;
1344 }
1345
1346 ret = tde_hal_node_get_ratio(hw_node, &cmp_ratio, &cmp_ratio_frm, &mb_org_bits);
1347 if ((ret != HI_SUCCESS) || (cmp_ratio_frm == 0) || (cmp_ratio == 0)) {
1348 return;
1349 }
1350 tde_hal_node_set_cfg0x(hw_node);
1351 tde_hal_node_set_cfgxx(hw_node);
1352 if (hw_node->tde_od_pic_osd_frame_size.bits.frame_height == 0) {
1353 return;
1354 }
1355
1356 tde_hal_node_frm_width(hw_node, &frm_width, &frm_width_r);
1357 mb_num_x = (osal_min(frm_width, frm_width_r) + 31) / 32; /* 31 32 for more than */
1358 if (mb_num_x == 0) {
1359 mb_num_x = 1;
1360 }
1361
1362 mb_minu10 = mb_num_x - 10; /* 10 narrow alg data */
1363
1364 hw_node->tde_od_pic_osd_rc_cfg1.bits.max_qp = (hw_node->tde_od_pic_osd_glb_info.bits.source_mode == 0) ?
1365 6 : ((hw_node->tde_od_pic_osd_glb_info.bits.source_mode == 2) ? 2 : 3); /* 2 3 6 max_qp data */
1366 /* 16 280 alg data */
1367 line_delta = hw_node->tde_od_pic_osd_rc_cfg7.bits.qp_inc1_bits_thr * 16 / mb_num_x + 280 / mb_num_x;
1368 /* 127 1000 alg data */
1369 ctl_delta = (mb_org_bits * 1000 / cmp_ratio) / 127 + osal_max((hi_u32)1,
1370 (hi_u32)(hw_node->tde_od_pic_osd_rc_cfg14.bits.init_buf_bits_cap +
1371 hw_node->tde_od_pic_osd_rc_cfg7.bits.qp_inc1_bits_thr * 16 + 280) / /* 16 280 alg data */
1372 (hw_node->tde_od_pic_osd_frame_size.bits.frame_height * mb_num_x));
1373 /* 0 3 ctl_delta data */
1374 ctl_delta = (hw_node->tde_od_pic_osd_glb_info.bits.source_mode == 0) ? (ctl_delta + 3) : ctl_delta;
1375
1376 mb_bits = (hi_s32)(mb_org_bits * 1000 / cmp_ratio); /* 1000 alg data */
1377 mb_bits = mb_bits - line_delta;
1378 hw_node->tde_od_pic_osd_rc_cfg0.bits.mb_bits =
1379 (hw_node->tde_od_pic_osd_glb_info.bits.is_lossless || hw_node->tde_od_pic_osd_glb_info.bits.cmp_mode) ?
1380 osal_min((hi_u32)1023, (hi_u32)mb_org_bits) : (hi_u32)mb_bits; /* 1023 alg data */
1381
1382 mb_bits_cap = (hi_s32)(mb_org_bits * 1000 / cmp_ratio_frm); /* 1000 alg data */
1383 mb_bits_cap = mb_bits_cap - ctl_delta;
1384 mb_bits_cap = osal_max((hi_u32)170, osal_min((hi_u32)mb_bits, (hi_u32)mb_bits_cap)); /* 170 alg data */
1385 hw_node->tde_od_pic_osd_rc_cfg14.bits.mb_bits_cap =
1386 (hw_node->tde_od_pic_osd_glb_info.bits.is_lossless || hw_node->tde_od_pic_osd_glb_info.bits.cmp_mode) ?
1387 osal_min((hi_u32)1023, (hi_u32)mb_org_bits) : (hi_u32)mb_bits_cap; /* 1023 alg data */
1388
1389 hw_node->tde_od_pic_osd_rc_cfg0.bits.min_mb_bits =
1390 osal_min((hi_u32)(hw_node->tde_od_pic_osd_rc_cfg14.bits.mb_bits_cap - 20), /* 20 alg data */
1391 (hi_u32)(hw_node->tde_od_pic_osd_rc_cfg0.bits.mb_bits * 3 / 4)); /* 4 3 alg data */
1392
1393 hw_node->tde_od_pic_osd_rc_cfg15.bits.lfw_mb_len =
1394 /* 2 alg data */
1395 osal_max((hi_u32)0, osal_min((hi_u32)(mb_num_x / 2), (hi_u32)(mb_minu10 < 0 ? 0 : mb_minu10)));
1396 /* 20 alg data */
1397 hw_node->tde_od_pic_osd_rc_cfg11.bits.grph_ideal_bit_thr = hw_node->tde_od_pic_osd_rc_cfg0.bits.mb_bits - 20;
1398 }
1399 #endif
1400
tde_hal_node_set_compress_tqt(tde_hw_node * hw_node,tde_surface_msg * drv_surface,hi_tde_out_alpha_from alpha_from)1401 hi_void tde_hal_node_set_compress_tqt(tde_hw_node *hw_node, tde_surface_msg *drv_surface,
1402 hi_tde_out_alpha_from alpha_from)
1403 {
1404 if (hw_node == HI_NULL) {
1405 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1406 return;
1407 }
1408 tde_hal_node_set_tqt(hw_node, drv_surface, alpha_from);
1409 #if (HICHIP != HI3519A_V100)
1410 hw_node->tde_od_pic_osd_glb_info.bits.hq_cmp_en = 1;
1411 #endif
1412 hw_node->des_ctrl.bits.cmp_en = 1;
1413 return;
1414 }
1415 #endif
1416
1417 #if (TDE_CAPABILITY & ROTATE)
tde_hal_node_set_rotate(tde_hw_node * hw_node,hi_tde_rotate_angle rotate_angle)1418 hi_void tde_hal_node_set_rotate(tde_hw_node *hw_node, hi_tde_rotate_angle rotate_angle)
1419 {
1420 if (hw_node == HI_NULL) {
1421 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1422 return;
1423 }
1424 hw_node->src2_rtt_ctrl.bits.s2_rtt_en = 1;
1425 /* set bitmap attribute info, CNcomment: Configure attribute information source bitmap */
1426 if (TDE_DRV_COLOR_FMT_YCBCR422 == hw_node->src2_ctrl.bits.src2_fmt) {
1427 hw_node->src2_rtt_ctrl.bits.s2_rtt_fmt = 0;
1428 }
1429 if ((hw_node->src2_ctrl.bits.src2_fmt == TDE_DRV_COLOR_FMT_RGB888) ||
1430 (TDE_DRV_COLOR_FMT_YCBCR888 == hw_node->src2_ctrl.bits.src2_fmt)) {
1431 hw_node->src2_rtt_ctrl.bits.s2_rtt_fmt = 1;
1432 }
1433 if ((hw_node->src2_ctrl.bits.src2_fmt == TDE_DRV_COLOR_FMT_ARGB4444) ||
1434 (hw_node->src2_ctrl.bits.src2_fmt == TDE_DRV_COLOR_FMT_ARGB1555)) {
1435 hw_node->src2_rtt_ctrl.bits.s2_rtt_fmt = 2; /* 2 ARGB4444 ARGB1555 */
1436 }
1437 if (hw_node->src2_ctrl.bits.src2_fmt == TDE_DRV_COLOR_FMT_ARGB8888) {
1438 hw_node->src2_rtt_ctrl.bits.s2_rtt_fmt = 3; /* 3 ARGB8888 */
1439 }
1440 if (rotate_angle == HI_TDE_ROTATE_CLOCKWISE_90) {
1441 hw_node->src2_rtt_ctrl.bits.s2_rtt_dir = 0;
1442 } else {
1443 hw_node->src2_rtt_ctrl.bits.s2_rtt_dir = 1;
1444 }
1445
1446 return;
1447 }
1448 #endif
1449
1450 #ifndef HI_BUILD_IN_BOOT
tde_hal_node_file(tde_hw_node * hw_node,tde_base_opt_mode mode,tde_alu_mode alu,tde_color_fill * color_fill,hi_u32 capability)1451 static hi_s32 tde_hal_node_file(tde_hw_node *hw_node, tde_base_opt_mode mode, tde_alu_mode alu,
1452 tde_color_fill *color_fill, hi_u32 capability)
1453 {
1454 if (mode == TDE_QUIKE_COPY) {
1455 if (!tde_hal_is_operation_support(alu, capability, QUICKCOPY)) {
1456 tde_error("It does not support QuickCopy\n");
1457 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
1458 }
1459 hw_node->src1_ctrl.bits.src1_en = 1;
1460 hw_node->src1_ctrl.bits.src1_dma = 1;
1461 }
1462 if (mode == TDE_NORM_FILL_1OPT) {
1463 if (color_fill == HI_NULL) {
1464 tde_error("pstColorFill is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1465 return HI_ERR_TDE_NULL_PTR;
1466 }
1467 tde_fill_data_by_fmt(hw_node, color_fill->fill_data, color_fill->drv_color_fmt, 1);
1468 hw_node->src2_ctrl.bits.src2_en = 1;
1469 hw_node->src2_ctrl.bits.src2_mode = 1;
1470 hw_node->cbmctrl.bits.cbm_en = 1;
1471 hw_node->cbmctrl.bits.cbm_mode = 1;
1472 hw_node->cbmctrl.bits.alu_mode = 1;
1473 }
1474 if (mode == TDE_NORM_FILL_2OPT) {
1475 if (color_fill == HI_NULL) {
1476 tde_error("pstColorFill is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1477 return HI_ERR_TDE_NULL_PTR;
1478 }
1479 tde_fill_data_by_fmt(hw_node, color_fill->fill_data, color_fill->drv_color_fmt, 1);
1480 hw_node->src1_ctrl.bits.src1_en = 1;
1481 hw_node->src1_ctrl.bits.src1_mode = 0;
1482 hw_node->src2_ctrl.bits.src2_en = 1;
1483 hw_node->src2_ctrl.bits.src2_mode = 1;
1484 hw_node->cbmctrl.bits.cbm_en = 1;
1485 hw_node->cbmctrl.bits.cbm_mode = 1;
1486
1487 hw_node->cbmctrl.bits.alu_mode = g_cbmctrl_alu_mode[alu];
1488 }
1489 return HI_SUCCESS;
1490 }
1491
tde_hal_node_opt(tde_hw_node * hw_node,tde_base_opt_mode mode,tde_alu_mode alu,hi_u32 capability)1492 static hi_s32 tde_hal_node_opt(tde_hw_node *hw_node, tde_base_opt_mode mode, tde_alu_mode alu,
1493 hi_u32 capability)
1494 {
1495 if (mode == TDE_SINGLE_SRC_PATTERN_FILL_OPT) {
1496 if (!tde_hal_is_operation_support(alu, capability, PATTERFILL)) {
1497 tde_error("It deos not support PatternFill\n");
1498 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
1499 }
1500
1501 hw_node->src2_ctrl.bits.src2_en = 1;
1502 hw_node->src2_ctrl.bits.src2_mode = 2; /* 2 mode */
1503 hw_node->cbmctrl.bits.cbm_en = 1;
1504 hw_node->cbmctrl.bits.cbm_mode = 1;
1505
1506 hw_node->cbmctrl.bits.alu_mode = g_cbmctrl_alu_mode[alu];
1507 }
1508 if (mode == TDE_DOUBLE_SRC_PATTERN_FILL_OPT) {
1509 if (!tde_hal_is_operation_support(alu, capability, PATTERFILL)) {
1510 tde_error("It deos not support PatternFill\n");
1511 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
1512 }
1513
1514 hw_node->src1_ctrl.bits.src1_en = 1;
1515 hw_node->src1_ctrl.bits.src1_mode = 0;
1516
1517 hw_node->src2_ctrl.bits.src2_en = 1;
1518 hw_node->src2_ctrl.bits.src2_mode = 2; /* 2 mode */
1519 hw_node->cbmctrl.bits.cbm_en = 1;
1520 hw_node->cbmctrl.bits.cbm_mode = 1;
1521
1522 hw_node->cbmctrl.bits.alu_mode = g_cbmctrl_alu_mode[alu];
1523 }
1524 return HI_SUCCESS;
1525 }
1526 #endif
1527
tde_hal_node_set_base_hw(tde_hw_node * hw_node,tde_base_opt_mode mode,tde_alu_mode alu)1528 static hi_void tde_hal_node_set_base_hw(tde_hw_node *hw_node, tde_base_opt_mode mode, tde_alu_mode alu)
1529 {
1530 if (mode == TDE_QUIKE_FILL) {
1531 hw_node->src1_ctrl.bits.src1_en = 1;
1532 hw_node->src1_ctrl.bits.src1_mode = 1;
1533 hw_node->src1_ctrl.bits.src1_dma = 1;
1534 return;
1535 }
1536 if (mode == TDE_NORM_BLIT_1OPT) {
1537 hw_node->src2_ctrl.bits.src2_en = 1;
1538 hw_node->src2_ctrl.bits.src2_mode = 0;
1539 hw_node->cbmctrl.bits.cbm_en = 1;
1540 hw_node->cbmctrl.bits.cbm_mode = 1;
1541 hw_node->cbmctrl.bits.alu_mode = 1;
1542 return;
1543 }
1544
1545 if (mode == TDE_NORM_BLIT_2OPT) {
1546 hw_node->src1_ctrl.bits.src1_en = 1;
1547 hw_node->src1_ctrl.bits.src1_mode = 0;
1548
1549 hw_node->src2_ctrl.bits.src2_en = 1;
1550 hw_node->src2_ctrl.bits.src2_mode = 0;
1551
1552 hw_node->cbmctrl.bits.cbm_en = 1;
1553 hw_node->cbmctrl.bits.cbm_mode = 1;
1554
1555 hw_node->cbmctrl.bits.alu_mode = g_cbmctrl_alu_mode[alu];
1556 return;
1557 }
1558 if (mode == TDE_MB_2OPT) {
1559 hw_node->src2_ctrl.bits.src2_en = 1;
1560 hw_node->src2_ctrl.bits.src2_mode = 0;
1561
1562 hw_node->cbmctrl.bits.cbm_en = 1;
1563 hw_node->cbmctrl.bits.cbm_mode = 1;
1564 hw_node->cbmctrl.bits.alu_mode = 0x1;
1565 }
1566 return;
1567 }
1568
tde_hal_quike_fill(tde_hw_node * hw_node,tde_base_opt_mode mode,tde_alu_mode alu,tde_color_fill * color_fill,hi_u32 capability)1569 static hi_s32 tde_hal_quike_fill(tde_hw_node *hw_node, tde_base_opt_mode mode, tde_alu_mode alu,
1570 tde_color_fill *color_fill, hi_u32 capability)
1571 {
1572 if (color_fill == HI_NULL) {
1573 tde_error("pstColorFill is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1574 return HI_ERR_TDE_NULL_PTR;
1575 }
1576 if (!tde_hal_is_operation_support(alu, capability, QUICKFILL)) {
1577 tde_error("It deos not support QuickFill\n");
1578 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
1579 }
1580 tde_fill_data_by_fmt(hw_node, color_fill->fill_data, color_fill->drv_color_fmt, 0);
1581 tde_hal_node_set_base_hw(hw_node, mode, alu);
1582 return HI_SUCCESS;
1583 }
1584
tde_hal_node_operation_support(tde_alu_mode alu,hi_u32 capability)1585 static hi_s32 tde_hal_node_operation_support(tde_alu_mode alu, hi_u32 capability)
1586 {
1587 #if (TDE_CAPABILITY & ROP)
1588 if (!tde_hal_is_operation_support(alu, capability, MASKROP)) {
1589 tde_error("It deos not support MaskRop\n");
1590 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
1591 }
1592 #endif
1593 #if (TDE_CAPABILITY & MASKBLEND)
1594 if (!tde_hal_is_operation_support(alu, capability, MASKBLEND)) {
1595 tde_error("It deos not support MaskBlend\n");
1596 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
1597 }
1598 #endif
1599 return HI_SUCCESS;
1600 }
1601
tde_hal_node_set_base_operate(tde_hw_node * hw_node,tde_base_opt_mode mode,tde_alu_mode alu,tde_color_fill * color_fill)1602 hi_s32 tde_hal_node_set_base_operate(tde_hw_node *hw_node, tde_base_opt_mode mode, tde_alu_mode alu,
1603 tde_color_fill *color_fill)
1604 {
1605 hi_u32 capability = 0;
1606 hi_s32 ret;
1607
1608 if (hw_node == HI_NULL) {
1609 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1610 return HI_ERR_TDE_NULL_PTR;
1611 }
1612 tde_hal_get_capability(&capability);
1613
1614 switch (mode) {
1615 case TDE_QUIKE_FILL: /* quick file, CNcomment:Rapid filling */
1616 ret = tde_hal_quike_fill(hw_node, mode, alu, color_fill, capability);
1617 if (ret != HI_SUCCESS) {
1618 return ret;
1619 }
1620 break;
1621 #ifndef HI_BUILD_IN_BOOT
1622 case TDE_QUIKE_COPY:
1623 case TDE_NORM_FILL_1OPT:
1624 case TDE_NORM_FILL_2OPT:
1625 ret = tde_hal_node_file(hw_node, mode, alu, color_fill, capability);
1626 if (ret != HI_SUCCESS) {
1627 return ret;
1628 }
1629 break;
1630 case TDE_SINGLE_SRC_PATTERN_FILL_OPT:
1631 case TDE_DOUBLE_SRC_PATTERN_FILL_OPT:
1632 ret = tde_hal_node_opt(hw_node, mode, alu, capability);
1633 if (ret != HI_SUCCESS) {
1634 return ret;
1635 }
1636 break;
1637 #endif
1638 case TDE_NORM_BLIT_2OPT:
1639 ret = tde_hal_node_operation_support(alu, capability);
1640 if (ret != HI_SUCCESS) {
1641 return ret;
1642 }
1643 /* fall-through */
1644 case TDE_NORM_BLIT_1OPT:
1645 case TDE_MB_2OPT:
1646 tde_hal_node_set_base_hw(hw_node, mode, alu);
1647 break;
1648 default:
1649 break;
1650 }
1651 return HI_SUCCESS;
1652 }
1653
tde_hal_is_operation_support(tde_alu_mode alu_mode,hi_u32 capability,hi_u32 oper_mode)1654 static hi_bool tde_hal_is_operation_support(tde_alu_mode alu_mode, hi_u32 capability, hi_u32 oper_mode)
1655 {
1656 if (!((hi_u32)MASKBLEND & oper_mode) && !((hi_u32)MASKROP & oper_mode)) {
1657 return (hi_bool)((capability & oper_mode) ? HI_TRUE : HI_FALSE);
1658 }
1659
1660 #if (TDE_CAPABILITY & MASKBLEND)
1661 if ((hi_u32)MASKBLEND & oper_mode) {
1662 return (hi_bool)(!((alu_mode == TDE_ALU_MASK_BLEND) && (!(capability & oper_mode))));
1663 }
1664 #endif
1665
1666 #if (TDE_CAPABILITY & ROP)
1667 if ((hi_u32)MASKROP & oper_mode) {
1668 return (hi_bool)(!(((alu_mode == TDE_ALU_MASK_ROP1) || (alu_mode == TDE_ALU_MASK_ROP2)) &&
1669 (!(capability & oper_mode))));
1670 }
1671 #endif
1672
1673 return HI_TRUE;
1674 }
1675
tde_hal_node_set_global_alpha(tde_hw_node * hw_node,hi_u8 alpha,hi_bool enable)1676 hi_void tde_hal_node_set_global_alpha(tde_hw_node *hw_node, hi_u8 alpha, hi_bool enable)
1677 {
1678 #ifndef HI_BUILD_IN_BOOT
1679 hi_unused(enable);
1680 if (hw_node == HI_NULL) {
1681 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1682 return;
1683 }
1684
1685 /* set node, CNcomment: Configure the cache node */
1686 hw_node->src2_cbmpara.bits.s2_galpha = alpha;
1687
1688 #endif
1689 return;
1690 }
1691
tde_hal_node_set_src1_alpha(tde_hw_node * hw_node)1692 hi_void tde_hal_node_set_src1_alpha(tde_hw_node *hw_node)
1693 {
1694 if (hw_node == HI_NULL) {
1695 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1696 return;
1697 }
1698
1699 /* set alpha0 alpha1, CNcomment:alpha0, alpha1 */
1700 hw_node->src1_alpha.bits.src1_alpha0 = 0;
1701 hw_node->src1_alpha.bits.src1_alpha1 = 0xff; /* 0xff alpha1 value */
1702
1703 return;
1704 }
1705
tde_hal_node_set_src2_alpha(tde_hw_node * hw_node)1706 hi_void tde_hal_node_set_src2_alpha(tde_hw_node *hw_node)
1707 {
1708 if (hw_node == HI_NULL) {
1709 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1710 return;
1711 }
1712
1713 /* set alpha0 alpha1, CNcomment:alpha0, alpha1 */
1714 hw_node->src2_alpha.bits.src2_alpha0 = 0;
1715 hw_node->src2_alpha.bits.src2_alpha1 = 0xff; /* 0xff alpha1 value */
1716
1717 return;
1718 }
1719
1720 /*
1721 * Function: tde_hal_node_set_exp_alpha
1722 * Description: extend to alpha0 and alpha1 operation when extend alpha for RGB5551
1723 * Input: hw_node:pointer of node
1724 * alpha0: Alpha0 value
1725 * alpha1: Alpha1 value
1726 */
tde_hal_node_set_exp_alpha(tde_hw_node * hw_node,tde_src_mode src,hi_u8 alpha0,hi_u8 alpha1)1727 hi_void tde_hal_node_set_exp_alpha(tde_hw_node *hw_node, tde_src_mode src, hi_u8 alpha0, hi_u8 alpha1)
1728 {
1729 if (hw_node == HI_NULL) {
1730 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1731 return;
1732 }
1733
1734 /* set alpha0 alpha1, CNcomment:alpha0, alpha1 */
1735 if ((hi_u32)src & TDE_DRV_SRC_S1) {
1736 hw_node->src1_alpha.bits.src1_alpha0 = alpha0;
1737 hw_node->src1_alpha.bits.src1_alpha1 = alpha1;
1738 hw_node->src1_ctrl.bits.src1_rgb_exp = 3; /* 3 set alpha0 alpha1 */
1739 }
1740
1741 if ((hi_u32)src & TDE_DRV_SRC_S2) {
1742 hw_node->src2_alpha.bits.src2_alpha0 = alpha0;
1743 hw_node->src2_alpha.bits.src2_alpha1 = alpha1;
1744 hw_node->src2_ctrl.bits.src2_rgb_exp = 3; /* 3 set alpha0 alpha1 */
1745 }
1746
1747 return;
1748 }
1749
1750 #if (TDE_CAPABILITY & ROP)
tde_hal_node_set_rop(tde_hw_node * hw_node,hi_tde_rop_mode rgb_rop,hi_tde_rop_mode alpha_rop)1751 hi_s32 tde_hal_node_set_rop(tde_hw_node *hw_node, hi_tde_rop_mode rgb_rop, hi_tde_rop_mode alpha_rop)
1752 {
1753 #ifndef HI_BUILD_IN_BOOT
1754 hi_u32 capability;
1755 if (hw_node == HI_NULL) {
1756 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1757 return HI_ERR_TDE_NULL_PTR;
1758 }
1759 tde_hal_get_capability(&capability);
1760 if (!(capability & ROP)) {
1761 tde_error("It deos not support Rop\n");
1762 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
1763 }
1764 /* set node, CNcomment: Configure the cache node */
1765 hw_node->cbmctrl.bits.cbm_en = 1;
1766 hw_node->cbmctrl.bits.cbm_mode = 1;
1767
1768 hw_node->cbmalupara.bits.rgb_rop = (hi_u32)rgb_rop;
1769 hw_node->cbmalupara.bits.rop = (hi_u32)alpha_rop;
1770 #endif
1771 return HI_SUCCESS;
1772 }
1773 #endif
1774
1775 #ifndef HI_BUILD_IN_BOOT
tde_hal_node_blend_mode(tde_hw_node * hw_node,hi_tde_blend_opt * blend_opt)1776 static hi_void tde_hal_node_blend_mode(tde_hw_node *hw_node, hi_tde_blend_opt *blend_opt)
1777 {
1778 if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_NONE) {
1779 /* fs: sa fd: 1.0-sa */
1780 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_INVSRC2ALPHA, HI_TDE_BLEND_SRC2ALPHA);
1781 } else if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_CLEAR) {
1782 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_ZERO, HI_TDE_BLEND_ZERO);
1783 } else if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_SRC) {
1784 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_ZERO, HI_TDE_BLEND_ONE);
1785 } else if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_SRCOVER) {
1786 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_INVSRC2ALPHA, HI_TDE_BLEND_ONE);
1787 } else if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_DSTOVER) {
1788 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_ONE, HI_TDE_BLEND_INVSRC1ALPHA);
1789 } else if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_SRCIN) {
1790 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_ZERO, HI_TDE_BLEND_SRC1ALPHA);
1791 } else if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_DSTIN) {
1792 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_SRC2ALPHA, HI_TDE_BLEND_ZERO);
1793 } else if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_SRCOUT) {
1794 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_ZERO, HI_TDE_BLEND_INVSRC1ALPHA);
1795 } else if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_DSTOUT) {
1796 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_INVSRC2ALPHA, HI_TDE_BLEND_ZERO);
1797 } else if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_SRCATOP) {
1798 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_INVSRC2ALPHA, HI_TDE_BLEND_SRC1ALPHA);
1799 } else if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_DSTATOP) {
1800 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_SRC2ALPHA, HI_TDE_BLEND_INVSRC1ALPHA);
1801 } else if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_ADD) {
1802 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_ONE, HI_TDE_BLEND_ONE);
1803 } else if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_XOR) {
1804 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_INVSRC2ALPHA, HI_TDE_BLEND_INVSRC1ALPHA);
1805 } else if (blend_opt->blend_cmd == HI_TDE_BLEND_CMD_DST) {
1806 drv_tde_node_blend_mode(hw_node, HI_TDE_BLEND_ONE, HI_TDE_BLEND_ZERO);
1807 } else {
1808 /* user parameter, CNcomment: The user's own configuration parameters */
1809 drv_tde_node_blend_mode(hw_node, blend_opt->src1_blend_mode, blend_opt->src2_blend_mode);
1810 }
1811 }
1812 #endif
1813
tde_hal_node_set_blend(tde_hw_node * hw_node,hi_tde_blend_opt * blend_opt)1814 hi_s32 tde_hal_node_set_blend(tde_hw_node *hw_node, hi_tde_blend_opt *blend_opt)
1815 {
1816 #ifndef HI_BUILD_IN_BOOT
1817 hi_u32 capability = 0;
1818
1819 if (hw_node == HI_NULL) {
1820 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1821 return HI_ERR_TDE_NULL_PTR;
1822 }
1823 if (blend_opt == HI_NULL) {
1824 tde_error("pstBlendOpt is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1825 return HI_ERR_TDE_NULL_PTR;
1826 }
1827 tde_hal_get_capability(&capability);
1828 if (!(capability & ALPHABLEND)) {
1829 tde_error("It deos not support Blend\n");
1830 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
1831 }
1832
1833 hw_node->src1_cbmpara.bits.s1_palphaen = HI_TRUE;
1834 hw_node->src1_cbmpara.bits.s1_galphaen = HI_FALSE;
1835 hw_node->src1_cbmpara.bits.s1_multiglobalen = HI_FALSE;
1836 hw_node->src2_cbmpara.bits.s2_multiglobalen = HI_FALSE;
1837
1838 hw_node->src1_cbmpara.bits.s1_premulten = blend_opt->src1_alpha_premulti;
1839 hw_node->src2_cbmpara.bits.s2_premulten = blend_opt->src2_alpha_premulti;
1840 hw_node->src2_cbmpara.bits.s2_palphaen = blend_opt->pixel_alpha_en;
1841 hw_node->src2_cbmpara.bits.s2_galphaen = blend_opt->global_alpha_en;
1842
1843 /* set mode for src1 and src2 , CNcomment: configuration Src1,€Src2 mode */
1844 tde_hal_node_blend_mode(hw_node, blend_opt);
1845 hw_node->cbmctrl.bits.cbm_en = 1;
1846 hw_node->cbmctrl.bits.cbm_mode = 1;
1847 #endif
1848 return HI_SUCCESS;
1849 }
1850
1851 #if (TDE_CAPABILITY & COLORIZE)
tde_hal_node_set_colorize(tde_hw_node * hw_node,hi_u32 colorize)1852 hi_s32 tde_hal_node_set_colorize(tde_hw_node *hw_node, hi_u32 colorize)
1853 {
1854 hi_u32 capability = 0;
1855 if (hw_node == HI_NULL) {
1856 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1857 return HI_ERR_TDE_NULL_PTR;
1858 }
1859 tde_hal_get_capability(&capability);
1860 if (!(capability & COLORIZE)) {
1861 tde_error("It deos not support Colorize\n");
1862 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
1863 }
1864 hw_node->cbmcolorize.bits.colorizeen = 1;
1865 hw_node->cbmcolorize.bits.colorizeb = colorize & 0xff;
1866 hw_node->cbmcolorize.bits.colorizeg = (colorize >> 8) & 0xff; /* 8 move to a minimum */
1867 hw_node->cbmcolorize.bits.colorizer = (colorize >> 16) & 0xff; /* 16 move to a minimum */
1868 return HI_SUCCESS;
1869 }
1870 #endif
1871
tde_hal_node_enable_alpha_rop(tde_hw_node * hw_node)1872 hi_void tde_hal_node_enable_alpha_rop(tde_hw_node *hw_node)
1873 {
1874 hw_node->cbmalupara.bits.blendropen = 1;
1875 return;
1876 }
1877
1878 /*
1879 * Function: tde_hal_node_set_clut_opt
1880 * Description: set color extend or color revise parameter
1881 * Input: hw_node: pointer of node
1882 * clut_cmd: Clut operation parameter
1883 */
tde_hal_node_set_clut_opt(tde_hw_node * hw_node,tde_clut_cmd * clut_cmd,hi_bool reload)1884 hi_s32 tde_hal_node_set_clut_opt(tde_hw_node *hw_node, tde_clut_cmd *clut_cmd, hi_bool reload)
1885 {
1886 #ifndef HI_BUILD_IN_BOOT
1887 hi_u32 capability = 0;
1888 hi_unused(reload);
1889 if (hw_node == HI_NULL) {
1890 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1891 return HI_ERR_TDE_NULL_PTR;
1892 }
1893 if (clut_cmd == HI_NULL) {
1894 tde_error("pClutCmd is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1895 return HI_ERR_TDE_NULL_PTR;
1896 }
1897 tde_hal_get_capability(&capability);
1898 if (!(capability & CLUT)) {
1899 tde_error("It deos not support Clut\n");
1900 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
1901 }
1902 hw_node->src2_ctrl.bits.src2_clut_mode = (hi_u32)clut_cmd->clut_mode;
1903 /* set node, CNcomment:Configure the cache node */
1904 if (clut_cmd->phy_clut_addr) {
1905 hw_node->tde_clut_addr_low = GetLowAddr(clut_cmd->phy_clut_addr);
1906 hw_node->tde_clut_addr_high = GetHighAddr(clut_cmd->phy_clut_addr);
1907 }
1908
1909 #endif
1910 return HI_SUCCESS;
1911 }
1912
1913 /*
1914 * Function: tde_hal_node_set_colorkey
1915 * Description: set parameter for color key operation according color format
1916 * Input: hw_node:pointer of node
1917 * fmt_cat: color format
1918 * color_key: pointer of color key value
1919 */
tde_hal_node_set_colorkey(tde_hw_node * hw_node,tde_colorfmt_category fmt_cat,tde_color_key_cmd * color_key)1920 hi_s32 tde_hal_node_set_colorkey(tde_hw_node *hw_node, tde_colorfmt_category fmt_cat, tde_color_key_cmd *color_key)
1921 {
1922 #ifndef HI_BUILD_IN_BOOT
1923 hi_u32 capability = 0;
1924
1925 if (hw_node == HI_NULL) {
1926 tde_error("hw_node is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1927 return HI_ERR_TDE_NULL_PTR;
1928 }
1929 if (color_key == HI_NULL) {
1930 tde_error("color_key is null %s(line=%d)\n", __FUNCTION__, __LINE__);
1931 return HI_ERR_TDE_NULL_PTR;
1932 }
1933
1934 tde_hal_get_capability(&capability);
1935 if (!(capability & COLORKEY)) {
1936 tde_error("It deos not support ColorKey\n");
1937 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
1938 }
1939 hw_node->cbmkeypara.bits.keysel = (hi_u32)color_key->color_key_mode;
1940 hw_node->cbmkeypara.bits.keyen = 1;
1941 if (fmt_cat == TDE_COLORFMT_CATEGORY_ARGB) {
1942 tde_hal_node_set_argbcolor_key_para(hw_node, color_key);
1943 } else if (fmt_cat == TDE_COLORFMT_CATEGORY_CLUT) {
1944 tde_hal_node_set_clutcolor_key_para(hw_node, color_key);
1945 } else if (fmt_cat == TDE_COLORFMT_CATEGORY_YCBCR) {
1946 tde_hal_node_set_ycbcr_color_key_para(hw_node, color_key);
1947 } else {
1948 tde_error("The clorfmt deos not support ColorKey\n");
1949 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
1950 }
1951
1952 hw_node->cbmctrl.bits.cbm_en = 1;
1953 hw_node->cbmctrl.bits.cbm_mode = 1;
1954
1955 #endif
1956 return HI_SUCCESS;
1957 }
1958
1959 #ifndef HI_BUILD_IN_BOOT
tde_hal_node_set_ycbcr_color_key_para(tde_hw_node * hw_node,tde_color_key_cmd * color_key)1960 static hi_void tde_hal_node_set_ycbcr_color_key_para(tde_hw_node *hw_node, tde_color_key_cmd *color_key)
1961 {
1962 hi_tde_color_key_comp cr = color_key->color_key_value.ycbcr_color_key.cr;
1963 hi_tde_color_key_comp cb = color_key->color_key_value.ycbcr_color_key.cb;
1964 hi_tde_color_key_comp y = color_key->color_key_value.ycbcr_color_key.y;
1965 hi_tde_color_key_comp alpha = color_key->color_key_value.ycbcr_color_key.alpha;
1966
1967 hw_node->cbmkeymin.all =
1968 tde_hal_get_ycb_cr_key_mask(cr.component_min, cb.component_min, y.component_min, alpha.component_min);
1969 hw_node->cbmkeymax.all =
1970 tde_hal_get_ycb_cr_key_mask(cr.component_max, cb.component_max, y.component_max, alpha.component_max);
1971 hw_node->cbmkeymask.all =
1972 tde_hal_get_ycb_cr_key_mask(cr.component_mask, cb.component_mask, y.component_mask, alpha.component_mask);
1973
1974 hw_node->cbmkeypara.bits.keybmode = tde_hal_get_color_key_mode(&cr);
1975 hw_node->cbmkeypara.bits.keygmode = tde_hal_get_color_key_mode(&cb);
1976 hw_node->cbmkeypara.bits.keyrmode = tde_hal_get_color_key_mode(&y);
1977 hw_node->cbmkeypara.bits.keyamode = tde_hal_get_color_key_mode(&alpha);
1978
1979 return;
1980 }
1981
tde_hal_node_set_clutcolor_key_para(tde_hw_node * hw_node,tde_color_key_cmd * color_key)1982 static hi_void tde_hal_node_set_clutcolor_key_para(tde_hw_node *hw_node, tde_color_key_cmd *color_key)
1983 {
1984 hi_tde_color_key_comp clut = color_key->color_key_value.clut_color_key.clut;
1985 hi_tde_color_key_comp alpha = color_key->color_key_value.clut_color_key.alpha;
1986
1987 hw_node->cbmkeymin.all = tde_hal_get_clut_key_mask(clut.component_min, alpha.component_min);
1988 hw_node->cbmkeymax.all = tde_hal_get_clut_key_mask(clut.component_max, alpha.component_max);
1989 hw_node->cbmkeymask.all = tde_hal_get_clut_key_mask(clut.component_mask, alpha.component_mask);
1990
1991 hw_node->cbmkeypara.bits.keybmode = tde_hal_get_color_key_mode(&clut);
1992 hw_node->cbmkeypara.bits.keyamode = tde_hal_get_color_key_mode(&alpha);
1993
1994 return;
1995 }
1996
tde_hal_node_set_argbcolor_key_para(tde_hw_node * hw_node,tde_color_key_cmd * color_key)1997 static hi_void tde_hal_node_set_argbcolor_key_para(tde_hw_node *hw_node, tde_color_key_cmd *color_key)
1998 {
1999 hi_tde_color_key_comp blue = color_key->color_key_value.argb_color_key.blue;
2000 hi_tde_color_key_comp green = color_key->color_key_value.argb_color_key.green;
2001 hi_tde_color_key_comp red = color_key->color_key_value.argb_color_key.red;
2002 hi_tde_color_key_comp alpha = color_key->color_key_value.argb_color_key.alpha;
2003
2004 hw_node->cbmkeymin.all =
2005 tde_hal_get_argb_key_mask(blue.component_min, green.component_min, red.component_min, alpha.component_min);
2006 hw_node->cbmkeymax.all =
2007 tde_hal_get_argb_key_mask(blue.component_max, green.component_max, red.component_max, alpha.component_max);
2008 hw_node->cbmkeymask.all =
2009 tde_hal_get_argb_key_mask(blue.component_mask, green.component_mask, red.component_mask, alpha.component_mask);
2010
2011 hw_node->cbmkeypara.bits.keybmode = tde_hal_get_color_key_mode(&blue);
2012 hw_node->cbmkeypara.bits.keygmode = tde_hal_get_color_key_mode(&green);
2013 hw_node->cbmkeypara.bits.keyrmode = tde_hal_get_color_key_mode(&red);
2014 hw_node->cbmkeypara.bits.keyamode = tde_hal_get_color_key_mode(&alpha);
2015 return;
2016 }
2017
tde_hal_get_color_key_mode(hi_tde_color_key_comp * color_key)2018 static hi_u32 tde_hal_get_color_key_mode(hi_tde_color_key_comp *color_key)
2019 {
2020 return (hi_u32)((color_key->is_component_ignore) ? TDE_COLORKEY_IGNORE :
2021 (color_key->is_component_out) ? TDE_COLORKEY_AREA_OUT : TDE_COLORKEY_AREA_IN);
2022 }
2023
tde_hal_get_ycb_cr_key_mask(hi_u8 cr,hi_u8 cb,hi_u8 cy,hi_u8 alpha)2024 static hi_u32 tde_hal_get_ycb_cr_key_mask(hi_u8 cr, hi_u8 cb, hi_u8 cy, hi_u8 alpha)
2025 {
2026 return (hi_u32)(cr | (cb << TDE_EIGHT_BITS_SHIFT) | (cy << TDE_SIXTEEN_BITS_SHIFT) |
2027 (alpha << TDE_TWENTYFOUR_BITS_SHIFT));
2028 }
2029
tde_hal_get_clut_key_mask(hi_u8 clut,hi_u8 alpha)2030 static hi_u32 tde_hal_get_clut_key_mask(hi_u8 clut, hi_u8 alpha)
2031 {
2032 return (hi_u32)(clut | (alpha << TDE_TWENTYFOUR_BITS_SHIFT));
2033 }
2034
tde_hal_get_argb_key_mask(hi_u8 blue,hi_u8 green,hi_u8 red,hi_u8 alpha)2035 static hi_u32 tde_hal_get_argb_key_mask(hi_u8 blue, hi_u8 green, hi_u8 red, hi_u8 alpha)
2036 {
2037 return (hi_u32)(blue | (green << TDE_EIGHT_BITS_SHIFT) | (red << TDE_SIXTEEN_BITS_SHIFT) |
2038 (alpha << TDE_TWENTYFOUR_BITS_SHIFT));
2039 }
2040 #endif
2041
tde_hal_node_set_clipping(tde_hw_node * hw_node,tde_clip_cmd * clip)2042 hi_s32 tde_hal_node_set_clipping(tde_hw_node *hw_node, tde_clip_cmd *clip)
2043 {
2044 #ifndef HI_BUILD_IN_BOOT
2045 hi_u32 capability = 0;
2046
2047 if (hw_node == HI_NULL) {
2048 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
2049 return HI_ERR_TDE_NULL_PTR;
2050 }
2051 if (clip == HI_NULL) {
2052 tde_error("pClip is null %s(line=%d)\n", __FUNCTION__, __LINE__);
2053 return HI_ERR_TDE_NULL_PTR;
2054 }
2055
2056 tde_hal_get_capability(&capability);
2057 if (!(capability & CLIP)) {
2058 tde_error("It deos not support Clip\n");
2059 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
2060 }
2061 hw_node->des_alpha.bits.des_crop_mode = 0;
2062 if (!clip->inside_clip) {
2063 /* over clip, CNcomment: Areas outside the clip */
2064 hw_node->des_alpha.bits.des_crop_mode = 1;
2065 }
2066 hw_node->des_alpha.bits.des_crop_en = 1;
2067 hw_node->des_crop_pos_st.bits.des_crop_start_x = clip->clip_start_x;
2068 hw_node->des_crop_pos_st.bits.des_crop_start_y = clip->clip_start_y;
2069 hw_node->des_crop_pos_ed.bits.des_crop_end_x = clip->clip_end_x;
2070 hw_node->des_crop_pos_ed.bits.des_crop_end_y = clip->clip_end_y;
2071 #endif
2072 return HI_SUCCESS;
2073 }
2074
2075 #if ((HICHIP != HI3516C_V500) && (HICHIP != HI3519A_V100))
tde_hal_calc_src1_set_zme(tde_hw_node * node,hi_tde_color_fmt in_fmt,hi_tde_rect * in_rect,hi_tde_rect * out_rect)2076 static hi_s32 tde_hal_calc_src1_set_zme(tde_hw_node *node, hi_tde_color_fmt in_fmt,
2077 hi_tde_rect *in_rect, hi_tde_rect *out_rect)
2078 {
2079 tde_color_fmt in_drv_fmt;
2080 if (in_rect == HI_NULL) {
2081 tde_error("pInRect is null %s(line=%d)\n", __FUNCTION__, __LINE__);
2082 return HI_FAILURE;
2083 }
2084
2085 if (out_rect == HI_NULL) {
2086 tde_error("pOutRect is null %s(line=%d)\n", __FUNCTION__, __LINE__);
2087 return HI_FAILURE;
2088 }
2089 if (in_fmt >= (HI_TDE_COLOR_FMT_MAX + 1)) {
2090 return HI_FAILURE;
2091 }
2092 in_drv_fmt = tde_get_common_drv_color_fmt((hi_u32)in_fmt);
2093
2094 node->src1_vsp.bits.zme_in_fmt = tde_hal_get_zme_in_fmt(in_drv_fmt);
2095
2096 node->src1_vsp.bits.zme_out_fmt = (node->src1_vsp.bits.zme_in_fmt == TDE_ZME_FMT_ARGB) ? TDE_ZME_FMT_ARGB :
2097 TDE_ZME_FMT_YUV444;
2098
2099 node->src1_imgsize.bits.src1_width = in_rect->width - 1;
2100 node->src1_zmeireso.bits.iw = in_rect->width - 1;
2101 node->src1_zmeoreso.bits.ow = out_rect->width - 1;
2102
2103 node->src1_imgsize.bits.src1_height = in_rect->height - 1;
2104 node->src1_zmeireso.bits.ih = in_rect->height - 1;
2105 node->src1_zmeoreso.bits.oh = out_rect->height - 1;
2106
2107 node->src1_hsp.bits.hratio = (out_rect->width <= 1) ? 0 : (osal_div_u64(((hi_u64)(in_rect->width) <<
2108 TDE_HAL_HSTEP_FLOATLEN), (out_rect->width)));
2109
2110 node->src1_vsr.bits.vratio = (out_rect->height <= 1) ? 0 : (osal_div_u64(((hi_u64)(in_rect->height) <<
2111 TDE_FLOAT_BITLEN), (out_rect->height)));
2112
2113 node->src1_hpzme_size.bits.src1_hpzme_width = in_rect->width;
2114 return HI_SUCCESS;
2115 }
2116
tde_hal_calc_src1_filter_opt(tde_hw_node * node,hi_tde_color_fmt in_fmt,hi_tde_rect * in_rect,hi_tde_rect * out_rect,hi_tde_deflicker_mode filter_mode)2117 hi_void tde_hal_calc_src1_filter_opt(tde_hw_node *node, hi_tde_color_fmt in_fmt,
2118 hi_tde_rect *in_rect, hi_tde_rect *out_rect, hi_tde_deflicker_mode filter_mode)
2119 {
2120 tde_filtermode flt_mode = {0};
2121 hi_s32 ret = tde_hal_calc_src1_set_zme(node, in_fmt, in_rect, out_rect);
2122 if (ret != HI_SUCCESS) {
2123 return;
2124 }
2125 if ((out_rect->width * 16) <= in_rect->width) { /* 16 width */
2126 node->src1_hpzme.bits.src1_hpzme_en = 1;
2127
2128 node->src1_hpzme.bits.src1_hpzme_mode = tde_hal_get_hpzme_mode(out_rect->width, in_rect->width);
2129
2130 node->src1_hpzme_size.bits.src1_hpzme_width = in_rect->width / (node->src1_hpzme.bits.src1_hpzme_mode + 1) +
2131 ((in_rect->width % (node->src1_hpzme.bits.src1_hpzme_mode + 1)) ? 1 : 0);
2132 }
2133
2134 node->src1_hsp.bits.hchmsc_en = 1;
2135 node->src1_hsp.bits.hlmsc_en = 1;
2136
2137 tde_hal_get_filter_mode(filter_mode, &flt_mode);
2138
2139 if (node->src1_hsp.bits.hratio != NO_HSCALE_STEP) {
2140 hi_u64 hf_coef_addr;
2141 node->src1_hsp.bits.hfir_order = 0;
2142
2143 node->src1_hsp.bits.hafir_en = flt_mode.alpha_en;
2144 node->src1_hsp.bits.hlfir_en = flt_mode.luma_en;
2145 node->src1_hsp.bits.hchfir_en = flt_mode.chrome_en;
2146
2147 hf_coef_addr = g_para_table.hf_coef_addr + tde_hal_get_resize_para_htable(node->src1_hsp.bits.hratio) *
2148 TDE_PARA_HTABLE_SIZE;
2149
2150 node->tde_src1_zme_chaddr_low = GetLowAddr(hf_coef_addr);
2151 node->tde_src1_zme_chaddr_high = GetHighAddr(hf_coef_addr);
2152
2153 node->tde_src1_zme_lhaddr_low = node->tde_src1_zme_chaddr_low;
2154 node->tde_src1_zme_lhaddr_high = node->tde_src1_zme_chaddr_high;
2155 }
2156
2157 node->src1_vsp.bits.vchmsc_en = 1;
2158 node->src1_vsp.bits.vlmsc_en = 1;
2159
2160 if (node->src1_vsr.bits.vratio != NO_VSCALE_STEP) {
2161 hi_u64 vf_coef_addr;
2162 node->src1_vsp.bits.vafir_en = flt_mode.alpha_en;
2163 node->src1_vsp.bits.vlfir_en = flt_mode.luma_en;
2164 node->src1_vsp.bits.vchfir_en = flt_mode.chrome_en;
2165
2166 vf_coef_addr = g_para_table.vf_coef_addr + tde_hal_get_resize_para_vtable(node->src1_vsr.bits.vratio) *
2167 TDE_PARA_VTABLE_SIZE;
2168
2169 node->tde_src1_zme_cvaddr_low = GetLowAddr(vf_coef_addr);
2170 node->tde_src1_zme_cvaddr_high = GetHighAddr(vf_coef_addr);
2171
2172 node->tde_src1_zme_lvaddr_low = node->tde_src1_zme_cvaddr_low;
2173 node->tde_src1_zme_lvaddr_high = node->tde_src1_zme_cvaddr_high;
2174 }
2175
2176 node->src1_zmeireso.bits.iw = node->src1_hpzme_size.bits.src1_hpzme_width - 1;
2177
2178 node->src1_hpzme_size.bits.src1_hpzme_width = node->src1_hpzme_size.bits.src1_hpzme_width - 1;
2179 return;
2180 }
2181 #endif
2182
tde_hal_calc_src2_filter_opt_chesk(tde_hw_node * node,tde_rect_opt * rect_opt)2183 static hi_s32 tde_hal_calc_src2_filter_opt_chesk(tde_hw_node *node, tde_rect_opt *rect_opt)
2184 {
2185 if (node == HI_NULL) {
2186 tde_error("pNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
2187 return HI_ERR_TDE_NULL_PTR;
2188 }
2189 if (rect_opt->in_rect == HI_NULL) {
2190 tde_error("rect_opt->pInRect is null %s(line=%d)\n", __FUNCTION__, __LINE__);
2191 return HI_ERR_TDE_NULL_PTR;
2192 }
2193 if (rect_opt->out_rect == HI_NULL) {
2194 tde_error("rect_opt->pOutRect is null %s(line=%d)\n", __FUNCTION__, __LINE__);
2195 return HI_ERR_TDE_NULL_PTR;
2196 }
2197 if (rect_opt->in_fmt >= (HI_TDE_COLOR_FMT_MAX + 1)) {
2198 return HI_ERR_TDE_INVALID_PARA;
2199 }
2200 return HI_SUCCESS;
2201 }
2202
tde_hal_set_zme_in_limit(tde_hw_node * node,tde_rect_opt * rect_opt)2203 hi_s32 tde_hal_set_zme_in_limit(tde_hw_node *node, tde_rect_opt *rect_opt)
2204 {
2205 hi_s32 ver_scale_coeff = 1;
2206 hi_s32 ret;
2207 if ((rect_opt->out_rect->width * 16) <= rect_opt->in_rect->width) { /* 16 2^4 alg data */
2208 node->src2_hpzme.bits.src2_hpzme_en = 1;
2209 node->src2_hpzme.bits.src2_hpzme_mode = tde_hal_get_hpzme_mode(rect_opt->out_rect->width,
2210 rect_opt->in_rect->width);
2211 if ((node->src2_hpzme.bits.src2_hpzme_mode + 1) == 0) {
2212 return HI_ERR_TDE_INVALID_PARA;
2213 }
2214 node->src2_hpzme_size.bits.src2_hpzme_width =
2215 rect_opt->in_rect->width / (node->src2_hpzme.bits.src2_hpzme_mode + 1) +
2216 ((rect_opt->in_rect->width % (node->src2_hpzme.bits.src2_hpzme_mode + 1)) ? 1 : 0);
2217 node->src2_hsp.bits.hratio = (rect_opt->out_rect->width <= 1) ? 0 :
2218 (osal_div_u64(((hi_u64)(node->src2_hpzme_size.bits.src2_hpzme_width) <<
2219 TDE_HAL_HSTEP_FLOATLEN), (rect_opt->out_rect->width)));
2220 }
2221
2222 if ((rect_opt->out_rect->height * 16) <= rect_opt->in_rect->height) { /* 16 2^4 alg data */
2223 ret = tde_hal_get_ver_scale_coeff(rect_opt->out_rect->height, rect_opt->in_rect->height, &ver_scale_coeff);
2224 if (ret != HI_SUCCESS) {
2225 return ret;
2226 }
2227 if (ver_scale_coeff == 0) {
2228 return HI_ERR_TDE_INVALID_PARA;
2229 }
2230 node->src2_zmeireso.bits.ih = rect_opt->in_rect->height / ver_scale_coeff - 1;
2231 node->src2_imgsize.bits.src2_height = rect_opt->in_rect->height / ver_scale_coeff - 1;
2232 node->src2_ch0_stride.bits.src2_ch0_stride = node->src2_ch0_stride.bits.src2_ch0_stride * ver_scale_coeff;
2233 if (rect_opt->out_rect->height == 0) {
2234 return HI_ERR_TDE_INVALID_PARA;
2235 }
2236 node->src2_vsr.bits.vratio = osal_div_u64(((hi_u64)(node->src2_imgsize.bits.src2_height) << TDE_FLOAT_BITLEN),
2237 (rect_opt->out_rect->height));
2238 } else {
2239 if (rect_opt->out_rect->height == 0) {
2240 return HI_ERR_TDE_INVALID_PARA;
2241 }
2242 node->src2_vsr.bits.vratio = (rect_opt->out_rect->height <= 1) ? 0 :
2243 (osal_div_u64(((hi_u64)(rect_opt->in_rect->height) << TDE_FLOAT_BITLEN), (rect_opt->out_rect->height)));
2244 }
2245 return HI_SUCCESS;
2246 }
2247
tde_hal_set_zme(tde_hw_node * node,tde_rect_opt * rect_opt,hi_tde_deflicker_mode filter_mode,hi_bool defilicker)2248 hi_void tde_hal_set_zme(tde_hw_node *node, tde_rect_opt *rect_opt, hi_tde_deflicker_mode filter_mode,
2249 hi_bool defilicker)
2250 {
2251 tde_filtermode flt_mode = {0};
2252 hi_u64 ch_coef_addr;
2253 hi_u64 cv_coef_addr;
2254
2255 node->src2_hsp.bits.hchmsc_en = 1;
2256 node->src2_hsp.bits.hlmsc_en = 1;
2257
2258 tde_hal_get_filter_mode(filter_mode, &flt_mode);
2259
2260 if (node->src2_hsp.bits.hratio != NO_HSCALE_STEP) {
2261 #if ((HICHIP == HI3516C_V500) || (HICHIP == HI3519A_V100))
2262 if (rect_opt->out_rect->width > MAX_LINE_BUFFER) {
2263 node->src2_hsp.bits.hfir_order = 1;
2264 }
2265 #else
2266 hi_unused(rect_opt);
2267 #endif
2268 if (node->src2_vsp.bits.zme_in_fmt == TDE_ZME_FMT_ARGB) {
2269 node->src2_hsp.bits.hlfir_en = flt_mode.alpha_en;
2270 } else {
2271 node->src2_hsp.bits.hlfir_en = flt_mode.luma_en;
2272 }
2273 node->src2_hsp.bits.hafir_en = flt_mode.alpha_en;
2274 node->src2_hsp.bits.hchfir_en = flt_mode.chrome_en;
2275 ch_coef_addr = g_para_table.hf_coef_addr + tde_hal_get_resize_para_htable(node->src2_hsp.bits.hratio) *
2276 TDE_PARA_HTABLE_SIZE;
2277
2278 node->tde_src2_zme_chaddr_low = GetLowAddr(ch_coef_addr);
2279 node->tde_src2_zme_chaddr_high = GetHighAddr(ch_coef_addr);
2280
2281 node->tde_src2_zme_lhaddr_low = node->tde_src2_zme_chaddr_low;
2282 node->tde_src2_zme_lhaddr_high = node->tde_src2_zme_chaddr_high;
2283 }
2284
2285 node->src2_vsp.bits.vchmsc_en = 1;
2286 node->src2_vsp.bits.vlmsc_en = 1;
2287
2288 if ((node->src2_vsr.bits.vratio != NO_VSCALE_STEP) && (!defilicker)) {
2289 node->src2_vsp.bits.vafir_en = flt_mode.alpha_en;
2290 if (node->src2_vsp.bits.zme_in_fmt == TDE_ZME_FMT_ARGB) {
2291 node->src2_vsp.bits.vlfir_en = flt_mode.alpha_en;
2292 } else {
2293 node->src2_vsp.bits.vlfir_en = flt_mode.luma_en;
2294 }
2295 node->src2_vsp.bits.vchfir_en = flt_mode.chrome_en;
2296
2297 cv_coef_addr = g_para_table.vf_coef_addr + tde_hal_get_resize_para_vtable(node->src2_vsr.bits.vratio) *
2298 TDE_PARA_VTABLE_SIZE;
2299 node->tde_src2_zme_cvaddr_low = GetLowAddr(cv_coef_addr);
2300 node->tde_src2_zme_cvaddr_high = GetHighAddr(cv_coef_addr);
2301
2302 node->tde_src2_zme_lvaddr_low = node->tde_src2_zme_cvaddr_low;
2303 node->tde_src2_zme_lvaddr_high = node->tde_src2_zme_cvaddr_high;
2304 }
2305 }
2306
2307 #ifndef HI_BUILD_IN_BOOT
2308 #if (TDE_CAPABILITY & DEFLICKER)
tde_hal_set_defilicker(tde_hw_node * node)2309 static hi_void tde_hal_set_defilicker(tde_hw_node *node)
2310 {
2311 hi_u64 cv_deflicker_coef_addr;
2312
2313 node->src2_vsp.bits.vchmsc_en = 1;
2314 node->src2_vsp.bits.vlmsc_en = 1;
2315 node->src2_vsp.bits.vafir_en = 1;
2316 node->src2_vsp.bits.vlfir_en = 1;
2317 node->src2_vsp.bits.vchfir_en = 1;
2318
2319 cv_deflicker_coef_addr = g_para_table.deflicker_vf_coef_addr +
2320 tde_hal_get_resize_para_vtable(node->src2_vsr.bits.vratio) * TDE_PARA_VTABLE_SIZE;
2321
2322 node->tde_src2_zme_cvaddr_low = GetLowAddr(cv_deflicker_coef_addr);
2323 node->tde_src2_zme_cvaddr_high = GetHighAddr(cv_deflicker_coef_addr);
2324
2325 node->tde_src2_zme_lvaddr_low = node->tde_src2_zme_cvaddr_low;
2326 node->tde_src2_zme_lvaddr_high = node->tde_src2_zme_cvaddr_high;
2327 }
2328 #endif
2329 #endif
2330
tde_hal_calc_src2_filter_opt(tde_hw_node * node,tde_rect_opt * rect_opt,hi_bool defilicker,hi_tde_deflicker_mode filter_mode)2331 hi_s32 tde_hal_calc_src2_filter_opt(tde_hw_node *node, tde_rect_opt *rect_opt, hi_bool defilicker,
2332 hi_tde_deflicker_mode filter_mode)
2333 {
2334 tde_color_fmt in_drv_fmt;
2335 hi_s32 ret;
2336
2337 ret = tde_hal_calc_src2_filter_opt_chesk(node, rect_opt);
2338 if (ret != HI_SUCCESS) {
2339 return ret;
2340 }
2341 in_drv_fmt = tde_get_common_drv_color_fmt((hi_u32)rect_opt->in_fmt);
2342
2343 node->src2_vsp.bits.zme_in_fmt = tde_hal_get_zme_in_fmt(in_drv_fmt);
2344
2345 node->src2_vsp.bits.zme_out_fmt = (node->src2_vsp.bits.zme_in_fmt == TDE_ZME_FMT_ARGB) ? TDE_ZME_FMT_ARGB :
2346 TDE_ZME_FMT_YUV444;
2347
2348 node->src2_imgsize.bits.src2_width = rect_opt->in_rect->width - 1;
2349 node->src2_zmeireso.bits.iw = rect_opt->in_rect->width - 1;
2350 node->src2_zmeoreso.bits.ow = rect_opt->out_rect->width - 1;
2351 node->src2_zmeoreso.bits.oh = rect_opt->out_rect->height - 1;
2352 node->src2_imgsize.bits.src2_height = rect_opt->in_rect->height - 1;
2353 node->src2_zmeireso.bits.ih = rect_opt->in_rect->height - 1;
2354
2355 node->des_imgsize.bits.des_width = rect_opt->out_rect->width - 1;
2356 node->des_imgsize.bits.des_height = rect_opt->out_rect->height - 1;
2357
2358 node->src2_hsp.bits.hratio = (rect_opt->out_rect->width <= 1) ? 0 :
2359 (osal_div_u64(((hi_u64)(rect_opt->in_rect->width) << TDE_HAL_HSTEP_FLOATLEN), (rect_opt->out_rect->width)));
2360
2361 node->src2_hpzme_size.bits.src2_hpzme_width = rect_opt->in_rect->width;
2362
2363 ret = tde_hal_set_zme_in_limit(node, rect_opt);
2364 if (ret != HI_SUCCESS) {
2365 return ret;
2366 }
2367 tde_hal_set_zme(node, rect_opt, filter_mode, defilicker);
2368
2369 #ifndef HI_BUILD_IN_BOOT
2370 #if (TDE_CAPABILITY & DEFLICKER)
2371 if (defilicker) {
2372 tde_hal_set_defilicker(node);
2373 }
2374 #endif
2375 #endif
2376
2377 node->src2_zmeireso.bits.iw = node->src2_hpzme_size.bits.src2_hpzme_width - 1;
2378
2379 node->src2_hpzme_size.bits.src2_hpzme_width = node->src2_hpzme_size.bits.src2_hpzme_width - 1;
2380
2381 return HI_SUCCESS;
2382 }
2383
tde_hal_get_zme_in_fmt(tde_color_fmt in_drv_fmt)2384 static hi_u32 tde_hal_get_zme_in_fmt(tde_color_fmt in_drv_fmt)
2385 {
2386 hi_u32 zme_in_fmt = 0;
2387
2388 hi_bool fmt_argb = (in_drv_fmt <= TDE_DRV_COLOR_FMT_ACLUT88) || ((in_drv_fmt == TDE_DRV_COLOR_FMT_YCBCR444MB)) ||
2389 (in_drv_fmt == TDE_DRV_COLOR_FMT_YCBCR400MBP);
2390 hi_bool fmt_yuv422 = (in_drv_fmt == TDE_DRV_COLOR_FMT_YCBCR422MBH) || (in_drv_fmt == TDE_DRV_COLOR_FMT_YCBCR422);
2391 hi_bool fmt_yuv420 = (in_drv_fmt == TDE_DRV_COLOR_FMT_YCBCR420MB) || (in_drv_fmt == TDE_DRV_COLOR_FMT_YCBCR422MBV);
2392
2393 if (fmt_argb) {
2394 zme_in_fmt = TDE_ZME_FMT_ARGB;
2395 }
2396
2397 if (fmt_yuv422) {
2398 zme_in_fmt = TDE_ZME_FMT_YUV422;
2399 }
2400
2401 if (fmt_yuv420) {
2402 zme_in_fmt = TDE_ZME_FMT_YUV420;
2403 }
2404
2405 return zme_in_fmt;
2406 }
2407
tde_hal_get_hpzme_mode(hi_u32 out_rect_width,hi_u32 in_rect_width)2408 static hi_u32 tde_hal_get_hpzme_mode(hi_u32 out_rect_width, hi_u32 in_rect_width)
2409 {
2410 hi_u32 hpzme_mode;
2411
2412 if ((out_rect_width * 32) > in_rect_width) { /* 32 out ram */
2413 hpzme_mode = 1;
2414 } else if ((out_rect_width * 64) > in_rect_width) { /* 64 out ram */
2415 hpzme_mode = 3; /* 3 hpzme mode */
2416 } else if ((out_rect_width * 128) > in_rect_width) { /* 128 out ram */
2417 hpzme_mode = 7; /* 7 hpzme mode */
2418 } else {
2419 hpzme_mode = 15; /* 15 hpzme mode */
2420 }
2421
2422 return hpzme_mode;
2423 }
2424
tde_hal_get_filter_mode(hi_tde_filter_mode filter_mode,tde_filtermode * flt_mode)2425 static hi_void tde_hal_get_filter_mode(hi_tde_filter_mode filter_mode, tde_filtermode *flt_mode)
2426 {
2427 hi_bool filter_mode_color = (filter_mode == HI_TDE_FILTER_MODE_COLOR);
2428 hi_bool filter_mode_alpha = (filter_mode == HI_TDE_FILTER_MODE_ALPHA);
2429 hi_bool filter_mode_both = (filter_mode == HI_TDE_FILTER_MODE_BOTH);
2430 hi_u32 alpha_en;
2431 hi_u32 luma_en;
2432 hi_u32 chrome_en;
2433
2434 if (filter_mode_color) {
2435 chrome_en = 1;
2436 luma_en = 1;
2437 alpha_en = 0;
2438 } else if (filter_mode_alpha) {
2439 chrome_en = 0;
2440 luma_en = 0;
2441 alpha_en = 1;
2442 } else if (filter_mode_both) {
2443 chrome_en = 1;
2444 luma_en = 1;
2445 alpha_en = 1;
2446 } else {
2447 chrome_en = 0;
2448 luma_en = 0;
2449 alpha_en = 0;
2450 }
2451 flt_mode->alpha_en = alpha_en;
2452 flt_mode->luma_en = luma_en;
2453 flt_mode->chrome_en = chrome_en;
2454
2455 return;
2456 }
2457
tde_hal_get_ver_scale_coeff(hi_u32 out_rect_height,hi_u32 in_rect_height,hi_s32 * ver_scale_coeff)2458 static hi_s32 tde_hal_get_ver_scale_coeff(hi_u32 out_rect_height, hi_u32 in_rect_height, hi_s32 *ver_scale_coeff)
2459 {
2460 if ((out_rect_height * 32) >= in_rect_height) { /* 32 out ram */
2461 *ver_scale_coeff = 2; /* 2 ver scale coeff data */
2462 } else if ((out_rect_height * 64) >= in_rect_height) { /* 64 out ram */
2463 *ver_scale_coeff = 4; /* 4 ver scale coeff data */
2464 } else if ((out_rect_height * 128) >= in_rect_height) { /* 128 out ram */
2465 *ver_scale_coeff = 8; /* 8 ver scale coeff data */
2466 } else {
2467 tde_error("Invalid para input!\n");
2468 return HI_ERR_TDE_INVALID_PARA;
2469 }
2470
2471 return HI_SUCCESS;
2472 }
2473
tde_hal_node_set_color_cvt_in_rgb2yuv(tde_hw_node * hw_node)2474 static hi_void tde_hal_node_set_color_cvt_in_rgb2yuv(tde_hw_node *hw_node)
2475 {
2476 #if ((HICHIP == HI3519A_V100) || (HICHIP == HI3516C_V500))
2477 hw_node->src1_csc_idc0.bits.cscidc0 = 0;
2478 hw_node->src1_csc_idc0.bits.cscidc1 = 0;
2479 hw_node->src1_csc_idc1.bits.cscidc2 = 0;
2480 hw_node->src1_csc_odc0.bits.cscodc0 = 128 * 4; /* 4 * 128 cscodc0 */
2481 hw_node->src1_csc_odc0.bits.cscodc1 = 128 * 4; /* 4 * 128 cscodc1 */
2482 hw_node->src1_csc_odc1.bits.cscodc2 = 16 * 4; /* 4 * 16 cscodc2 */
2483 #else
2484 hw_node->src1_csc_idc.bits.cscidc0 = 0;
2485 hw_node->src1_csc_idc.bits.cscidc1 = 0;
2486 hw_node->src1_csc_idc.bits.cscidc2 = 0;
2487 hw_node->src1_csc_odc.bits.cscodc0 = 128; /* 128 cscodc0 */
2488 hw_node->src1_csc_odc.bits.cscodc1 = 128; /* 128 cscodc1 */
2489 hw_node->src1_csc_odc.bits.cscodc2 = 16; /* 16 cscodc2 */
2490 #endif
2491
2492 hw_node->src1_csc_p0.bits.cscp00 = 66 * 4; /* 4 * 66 cscp00 */
2493 hw_node->src1_csc_p0.bits.cscp01 = 129 * 4; /* 4 * 129 cscp01 data */
2494
2495 hw_node->src1_csc_p1.bits.cscp02 = 25 * 4; /* 4 * 25 cscp02 */
2496 hw_node->src1_csc_p1.bits.cscp10 = -38 * 4; /* 4 * -38 cscp10 data */
2497
2498 hw_node->src1_csc_p2.bits.cscp11 = -74 * 4; /* 4 * -74 cscp11 data */
2499 hw_node->src1_csc_p2.bits.cscp12 = 112 * 4; /* 112 * 4 cscp12 data */
2500
2501 hw_node->src1_csc_p3.bits.cscp20 = 112 * 4; /* 4 * 112 cscp20 data */
2502 hw_node->src1_csc_p3.bits.cscp21 = -94 * 4; /* 4 * -94 cscp21 data */
2503
2504 hw_node->src1_csc_p4.bits.cscp22 = -18 * 4; /* 4 * -18 cscp22 data */
2505 }
2506
tde_hal_node_set_color_cvt_in_yuv2rgb(tde_hw_node * hw_node)2507 static hi_void tde_hal_node_set_color_cvt_in_yuv2rgb(tde_hw_node *hw_node)
2508 {
2509 #if ((HICHIP == HI3519A_V100) || (HICHIP == HI3516C_V500))
2510 hw_node->src1_csc_idc0.bits.cscidc0 = -128 * 4; /* 4 * -128 cscidc0 data */
2511 hw_node->src1_csc_idc0.bits.cscidc1 = -128 * 4; /* 4 * -128 cscidc1 data */
2512 hw_node->src1_csc_idc1.bits.cscidc2 = -16 * 4; /* 4 * -16 cscidc2 data */
2513 hw_node->src1_csc_odc0.bits.cscodc0 = 0;
2514 hw_node->src1_csc_odc0.bits.cscodc1 = 0;
2515 hw_node->src1_csc_odc1.bits.cscodc2 = 0;
2516 #else
2517 hw_node->src1_csc_idc.bits.cscidc0 = -128; /* -128 cscidc0 data */
2518 hw_node->src1_csc_idc.bits.cscidc1 = -128; /* -128 cscidc1 data */
2519 hw_node->src1_csc_idc.bits.cscidc2 = -16; /* -16 cscidc2 data */
2520 hw_node->src1_csc_odc.bits.cscodc0 = 0;
2521 hw_node->src1_csc_odc.bits.cscodc1 = 0;
2522 hw_node->src1_csc_odc.bits.cscodc2 = 0;
2523 #endif
2524
2525 hw_node->src1_csc_p0.bits.cscp00 = 297 * 4; /* 4 * 297 cscp00 data */
2526 hw_node->src1_csc_p0.bits.cscp01 = 0;
2527
2528 hw_node->src1_csc_p1.bits.cscp02 = 408 * 4; /* 4 * 408 cscp02 data */
2529 hw_node->src1_csc_p1.bits.cscp10 = 297 * 4; /* 4 * 297 cscp10 data */
2530
2531 hw_node->src1_csc_p2.bits.cscp11 = -100 * 4; /* 4 * -100 cscp11 data */
2532 hw_node->src1_csc_p2.bits.cscp12 = -208 * 4; /* 4 * -208 cscp12 data */
2533
2534 hw_node->src1_csc_p3.bits.cscp20 = 297 * 4; /* 4 * 297 cscp20 data */
2535 hw_node->src1_csc_p3.bits.cscp21 = 516 * 4; /* 4 * 516 cscp21 data */
2536
2537 hw_node->src1_csc_p4.bits.cscp22 = 0;
2538 }
2539
tde_hal_node_set_color_cvt_out_rgb2yuv(tde_hw_node * hw_node)2540 static hi_void tde_hal_node_set_color_cvt_out_rgb2yuv(tde_hw_node *hw_node)
2541 {
2542 #if ((HICHIP == HI3519A_V100) || (HICHIP == HI3516C_V500))
2543 hw_node->des_csc_idc0.bits.cscidc0 = -128 * 4; /* 4 * -128 cscidc0 data */
2544 hw_node->des_csc_idc0.bits.cscidc1 = -128 * 4; /* 4 * -128 cscidc1 data */
2545 hw_node->des_csc_idc1.bits.cscidc2 = -16 * 4; /* 4 * -16 cscidc2 data */
2546 hw_node->des_csc_odc0.bits.cscodc0 = 0;
2547 hw_node->des_csc_odc0.bits.cscodc1 = 0;
2548 hw_node->des_csc_odc1.bits.cscodc2 = 0;
2549 #else
2550 hw_node->des_csc_idc.bits.cscidc0 = -128; /* -128 cscidc0 data */
2551 hw_node->des_csc_idc.bits.cscidc1 = -128; /* -128 cscidc1 data */
2552 hw_node->des_csc_idc.bits.cscidc2 = -16; /* -16 cscidc2 data */
2553 hw_node->des_csc_odc.bits.cscodc0 = 0;
2554 hw_node->des_csc_odc.bits.cscodc1 = 0;
2555 hw_node->des_csc_odc.bits.cscodc2 = 0;
2556 #endif
2557
2558 hw_node->des_csc_p0.bits.cscp00 = 297 * 4; /* 4 * 297 cscp00 data */
2559 hw_node->des_csc_p0.bits.cscp01 = 0;
2560
2561 hw_node->des_csc_p1.bits.cscp02 = 408 * 4; /* 4 * 408 cscp02 data */
2562 hw_node->des_csc_p1.bits.cscp10 = 297 * 4; /* 4 * 297 cscp10 data */
2563
2564 hw_node->des_csc_p2.bits.cscp11 = -100 * 4; /* 4 * -100 cscp11 data */
2565 hw_node->des_csc_p2.bits.cscp12 = -208 * 4; /* 4 * -208 cscp12 data */
2566
2567 hw_node->des_csc_p3.bits.cscp20 = 297 * 4; /* 4 * 297 cscp20 data */
2568 hw_node->des_csc_p3.bits.cscp21 = 516 * 4; /* 4 * 516 cscp21 data */
2569 hw_node->des_csc_p4.bits.cscp22 = 0;
2570 }
2571
tde_hal_node_set_color_cvt_out_yuv2rgb(tde_hw_node * hw_node)2572 static hi_void tde_hal_node_set_color_cvt_out_yuv2rgb(tde_hw_node *hw_node)
2573 {
2574 #if ((HICHIP == HI3519A_V100) || (HICHIP == HI3516C_V500))
2575 hw_node->des_csc_idc0.bits.cscidc0 = 0;
2576 hw_node->des_csc_idc0.bits.cscidc1 = 0;
2577 hw_node->des_csc_idc1.bits.cscidc2 = 0;
2578 hw_node->des_csc_odc0.bits.cscodc0 = 128 * 4; /* 4 * 128 cscodc0 data */
2579 hw_node->des_csc_odc0.bits.cscodc1 = 128 * 4; /* 4 * 128 cscodc1 data */
2580 hw_node->des_csc_odc1.bits.cscodc2 = 16 * 4; /* 4 * 16 cscodc2 data */
2581 #else
2582 hw_node->des_csc_idc.bits.cscidc0 = 0;
2583 hw_node->des_csc_idc.bits.cscidc1 = 0;
2584 hw_node->des_csc_idc.bits.cscidc2 = 0;
2585 hw_node->des_csc_odc.bits.cscodc0 = 128; /* 128 cscodc0 data */
2586 hw_node->des_csc_odc.bits.cscodc1 = 128; /* 128 cscodc1 data */
2587 hw_node->des_csc_odc.bits.cscodc2 = 16; /* 16 cscodc2 data */
2588 #endif
2589
2590 hw_node->des_csc_p0.bits.cscp00 = 66 * 4; /* 4 * 66 cscp00 data */
2591 hw_node->des_csc_p0.bits.cscp01 = 129 * 4; /* 4 * 129 cscp01 data */
2592
2593 hw_node->des_csc_p1.bits.cscp02 = 25 * 4; /* 4 * 25 cscp02 data */
2594 hw_node->des_csc_p1.bits.cscp10 = -38 * 4; /* 4 * -38 cscp10 data */
2595
2596 hw_node->des_csc_p2.bits.cscp11 = -74 * 4; /* 4 * -74 cscp11 data */
2597
2598 hw_node->des_csc_p2.bits.cscp12 = 112 * 4; /* 4 * 112 cscp12 data */
2599
2600 hw_node->des_csc_p3.bits.cscp20 = 112 * 4; /* 4 * 112 cscp20 data */
2601
2602 hw_node->des_csc_p3.bits.cscp21 = -94 * 4; /* 4 * -94 cscp21 data */
2603 hw_node->des_csc_p4.bits.cscp22 = -18 * 4; /* 4 * -18 cscp22 data */
2604 }
2605
2606 /*
2607 * Function: tde_hal_node_set_color_convert
2608 * Description: set parameter for color space change
2609 * Input: hw_node:pointer of node
2610 * conv: parameter of color space change
2611 */
tde_hal_node_set_color_convert(tde_hw_node * hw_node,tde_conv_mode_cmd * conv)2612 hi_s32 tde_hal_node_set_color_convert(tde_hw_node *hw_node, tde_conv_mode_cmd *conv)
2613 {
2614 hi_u32 capability = 0;
2615 if (hw_node == HI_NULL) {
2616 tde_error("pHWNode is null %s(line=%d)\n", __FUNCTION__, __LINE__);
2617 return HI_ERR_TDE_NULL_PTR;
2618 }
2619 if (conv == HI_NULL) {
2620 tde_error("pConv is null %s(line=%d)\n", __FUNCTION__, __LINE__);
2621 return HI_ERR_TDE_NULL_PTR;
2622 }
2623 tde_hal_get_capability(&capability);
2624 if (!(capability & CSCCOVERT)) {
2625 tde_error("It deos not support CSCCovert\n");
2626 return HI_ERR_TDE_UNSUPPORTED_OPERATION;
2627 }
2628
2629 if (conv->in_conv) {
2630 hw_node->src2_csc_mux.bits.src2_csc_mode = 1 - (hi_u32)conv->in_src1_conv;
2631 #if ((HICHIP == HI3519A_V100) || (HICHIP == HI3516C_V500))
2632 hw_node->src1_csc_idc0.bits.csc_en = 1;
2633 hw_node->src1_dither_ctrl.bits.dither_en = 1;
2634 hw_node->src1_dither_ctrl.bits.dither_round = 0;
2635 #else
2636 hw_node->src1_csc_idc.bits.csc_en = 1;
2637 #endif
2638 if (conv->in_rgb2_yc) {
2639 tde_hal_node_set_color_cvt_in_rgb2yuv(hw_node);
2640 } else {
2641 tde_hal_node_set_color_cvt_in_yuv2rgb(hw_node);
2642 }
2643 }
2644
2645 if (conv->out_conv) {
2646 hw_node->src2_csc_mux.bits.src2_csc_mode = 1 - (hi_u32)conv->in_src1_conv;
2647 #if ((HICHIP == HI3519A_V100) || (HICHIP == HI3516C_V500))
2648 hw_node->des_csc_idc0.bits.csc_en = 1;
2649 hw_node->dst_dither_ctrl.bits.dither_en = 1;
2650 hw_node->dst_dither_ctrl.bits.dither_round = 0;
2651 #else
2652 hw_node->des_csc_idc.bits.csc_en = 1;
2653 #endif
2654 if (conv->in_rgb2_yc) {
2655 tde_hal_node_set_color_cvt_out_rgb2yuv(hw_node);
2656 } else {
2657 tde_hal_node_set_color_cvt_out_yuv2rgb(hw_node);
2658 }
2659 }
2660 return HI_SUCCESS;
2661 }
2662
tde_set_node_csc(tde_hw_node * hw_node,hi_tde_csc_opt csc_opt)2663 hi_s32 tde_set_node_csc(tde_hw_node *hw_node, hi_tde_csc_opt csc_opt)
2664 {
2665 hi_unused(hw_node);
2666 hi_unused(csc_opt);
2667 return HI_SUCCESS;
2668 }
2669
tde_hal_make_hf_coef(hi_void)2670 static hi_u32 *tde_hal_make_hf_coef(hi_void)
2671 {
2672 hi_u32 i;
2673 hi_u32 *hf_coef = HI_NULL;
2674
2675 hf_coef = (hi_u32 *)tde_malloc(TDE_PARA_HTABLE_SIZE * TDE_PARA_HTABLE_NUM);
2676 if (hf_coef == HI_NULL) {
2677 tde_error("Alloc horizontal coef failed!HCoef table size:%d\n", TDE_PARA_HTABLE_SIZE * TDE_PARA_HTABLE_NUM);
2678 return HI_NULL;
2679 }
2680
2681 for (i = 0; i < TDE_PARA_HTABLE_NUM; i++) {
2682 /* 4 size value */
2683 if (memcpy_s(hf_coef + i * (TDE_PARA_HTABLE_SIZE / 4), TDE_PARA_HTABLE_SIZE, g_tde_6x32_coef +
2684 i * (TDE_PARA_HTABLE_ORG_SIZE), (TDE_PARA_HTABLE_ORG_SIZE) * 4) != EOK) { /* 4 size */
2685 tde_error("%s:%d:memcpy_s failure\n", __FUNCTION__, __LINE__);
2686 tde_free(hf_coef);
2687 return HI_NULL;
2688 }
2689 }
2690
2691 #ifndef __RTOS__
2692 g_para_table.hf_coef_addr = wgetphy((hi_void *)hf_coef);
2693 #else
2694 g_para_table.hf_coef_addr = (hi_u64)(hi_uintptr_t)hf_coef;
2695 #endif
2696 return hf_coef;
2697 }
2698
tde_hal_make_vf_coef(hi_void)2699 static hi_u32 *tde_hal_make_vf_coef(hi_void)
2700 {
2701 hi_u32 i;
2702 hi_u32 *vf_coef = HI_NULL;
2703
2704 vf_coef = (hi_u32 *)tde_malloc(TDE_PARA_VTABLE_SIZE * TDE_PARA_VTABLE_NUM);
2705 if (vf_coef == HI_NULL) {
2706 tde_error("Alloc vertical coef failed!VfCoef table size:%d\n", TDE_PARA_VTABLE_SIZE * TDE_PARA_VTABLE_NUM);
2707 return HI_NULL;
2708 }
2709 /*
2710 * copy parameter according other offer way , CNcomment :According to the parameter table algorithm
2711 * group provides the structure of the copies
2712 */
2713 for (i = 0; i < TDE_PARA_VTABLE_NUM; i++) {
2714 if (memcpy_s(vf_coef + i * (TDE_PARA_VTABLE_SIZE / 4), TDE_PARA_VTABLE_SIZE, g_org_vf_coef + /* 4 size value */
2715 i * (TDE_PARA_VTABLE_ORG_SIZE), (TDE_PARA_VTABLE_ORG_SIZE) * 4) != EOK) { /* 4 size value */
2716 tde_error("secure function failure\n");
2717 tde_free(vf_coef);
2718 return HI_NULL;
2719 }
2720 }
2721
2722 #ifndef __RTOS__
2723 g_para_table.vf_coef_addr = wgetphy((hi_void *)vf_coef);
2724 #else
2725 g_para_table.vf_coef_addr = (hi_u64)(hi_uintptr_t)vf_coef;
2726 #endif
2727 return vf_coef;
2728 }
2729
2730 #ifndef HI_BUILD_IN_BOOT
2731 #if (TDE_CAPABILITY & DEFLICKER)
tde_hal_make_deflicker_vf_coef(hi_void)2732 static hi_u32 *tde_hal_make_deflicker_vf_coef(hi_void)
2733 {
2734 hi_u32 i;
2735 hi_u32 *deflicker_vf_coef = HI_NULL;
2736
2737 deflicker_vf_coef = (hi_u32 *)tde_malloc(TDE_PARA_VTABLE_SIZE * TDE_PARA_VTABLE_NUM);
2738 if (deflicker_vf_coef == HI_NULL) {
2739 tde_error("Alloc Deflicker vertical coef failed!g_deflicker_vf_coef table size:%d\n",
2740 TDE_PARA_VTABLE_SIZE * TDE_PARA_VTABLE_NUM);
2741 return HI_NULL;
2742 }
2743
2744 for (i = 0; i < TDE_PARA_VTABLE_NUM; i++) {
2745 /* 4 alg data */
2746 if (memcpy_s(deflicker_vf_coef + i * (TDE_PARA_VTABLE_SIZE / 4), TDE_PARA_VTABLE_SIZE, g_deflicker_vf_coef +
2747 i * (TDE_PARA_VTABLE_ORG_SIZE), (TDE_PARA_VTABLE_ORG_SIZE) * 4) != EOK) { /* 4 alg data */
2748 tde_error("secure function failure\n");
2749 tde_free(deflicker_vf_coef);
2750 return HI_NULL;
2751 }
2752 }
2753
2754 #ifndef __RTOS__
2755 g_para_table.deflicker_vf_coef_addr = wgetphy((hi_void *)deflicker_vf_coef);
2756 #else
2757 g_para_table.deflicker_vf_coef_addr = (hi_u32)deflicker_vf_coef;
2758 #endif
2759 return deflicker_vf_coef;
2760 }
2761 #endif
2762 #endif
2763
tde_hal_init_para_table(hi_void)2764 static hi_s32 tde_hal_init_para_table(hi_void)
2765 {
2766 hi_u32 *hf_coef = HI_NULL;
2767 hi_u32 *vf_coef = HI_NULL;
2768 #ifndef HI_BUILD_IN_BOOT
2769 #if (TDE_CAPABILITY & DEFLICKER)
2770 hi_u32 *deflicker_vf_coef = HI_NULL;
2771 #endif
2772 #endif
2773 (hi_void)memset_s(&g_para_table, sizeof(g_para_table), 0, sizeof(g_para_table));
2774 hf_coef = tde_hal_make_hf_coef();
2775 if (hf_coef == HI_NULL) {
2776 return HI_FAILURE;
2777 }
2778 vf_coef = tde_hal_make_vf_coef();
2779 if (vf_coef == HI_NULL) {
2780 tde_free(hf_coef);
2781 return HI_FAILURE;
2782 }
2783 #ifndef HI_BUILD_IN_BOOT
2784 #if (TDE_CAPABILITY & DEFLICKER)
2785 deflicker_vf_coef = tde_hal_make_deflicker_vf_coef();
2786 if (deflicker_vf_coef == HI_NULL) {
2787 tde_free(hf_coef);
2788 tde_free(vf_coef);
2789 return HI_FAILURE;
2790 }
2791 #endif
2792 #endif
2793 return HI_SUCCESS;
2794 }
2795
2796 /*
2797 * Function: tde_hal_cur_node
2798 * Description: get the node physics address that is suspended
2799 * Return: the address of current running node
2800 */
tde_hal_cur_node()2801 hi_u64 tde_hal_cur_node()
2802 {
2803 hi_u32 low_addr;
2804 hi_u32 hi_addr;
2805 hi_u64 addr;
2806
2807 low_addr = tde_read_reg(g_base_vir_addr, TDE_AQ_ADDR_LOW);
2808 hi_addr = tde_read_reg(g_base_vir_addr, TDE_AQ_ADDR_HI);
2809 addr = ((hi_u64)hi_addr << 32) | low_addr; /* 32 alg data */
2810 return addr;
2811 }
2812
2813 /*
2814 * Function: tde_hal_getbpp_by_fmt
2815 * Description: get bpp according color of driver
2816 * Input: fmt: color type
2817 * Output: pitch width
2818 * Return: -1: wrong format
2819 */
tde_hal_getbpp_by_fmt(tde_color_fmt fmt)2820 static hi_s32 tde_hal_getbpp_by_fmt(tde_color_fmt fmt)
2821 {
2822 if (tde_hal_getbpp_by_fmt16(fmt) == 16) { /* 16 fmt data */
2823 return 16; /* 16 fmt data */
2824 } else if (tde_hal_getbpp_by_fmt24(fmt) == 24) { /* 24 fmt data */
2825 return 24; /* 24 fmt data */
2826 } else if (tde_hal_getbpp_by_fmt32(fmt) == 32) { /* 32 fmt data */
2827 return 32; /* 32 fmt data */
2828 } else if (tde_hal_getbpp_by_fmt1(fmt) == 1) {
2829 return 1;
2830 } else if (tde_hal_getbpp_by_fmt2(fmt) == 2) { /* 2 fmt data */
2831 return 2; /* 2 fmt data */
2832 } else if (tde_hal_getbpp_by_fmt4(fmt) == 4) { /* 4 fmt data */
2833 return 4; /* 4 fmt data */
2834 } else if (tde_hal_getbpp_by_fmt8(fmt) == 8) { /* 8 fmt data */
2835 return 8; /* 8 fmt data */
2836 } else {
2837 return -1;
2838 }
2839 }
2840
tde_hal_getbpp_by_fmt16(tde_color_fmt fmt)2841 static hi_s32 tde_hal_getbpp_by_fmt16(tde_color_fmt fmt)
2842 {
2843 switch (fmt) {
2844 case TDE_DRV_COLOR_FMT_RGB444:
2845 case TDE_DRV_COLOR_FMT_RGB555:
2846 case TDE_DRV_COLOR_FMT_RGB565:
2847 case TDE_DRV_COLOR_FMT_ARGB4444:
2848 case TDE_DRV_COLOR_FMT_ARGB1555:
2849 case TDE_DRV_COLOR_FMT_ACLUT88:
2850 case TDE_DRV_COLOR_FMT_YCBCR422:
2851 case TDE_DRV_COLOR_FMT_HALFWORD:
2852 case TDE_DRV_COLOR_FMT_PKGVYUY:
2853 return 16; /* 16 fmt data */
2854
2855 default:
2856 return -1;
2857 }
2858 }
2859
tde_hal_getbpp_by_fmt24(tde_color_fmt fmt)2860 static hi_s32 tde_hal_getbpp_by_fmt24(tde_color_fmt fmt)
2861 {
2862 switch (fmt) {
2863 case TDE_DRV_COLOR_FMT_RGB888:
2864 case TDE_DRV_COLOR_FMT_ARGB8565:
2865 case TDE_DRV_COLOR_FMT_YCBCR888:
2866 return 24; /* 24 fmt data */
2867 default:
2868 return -1;
2869 }
2870 }
2871
tde_hal_getbpp_by_fmt32(tde_color_fmt fmt)2872 static hi_s32 tde_hal_getbpp_by_fmt32(tde_color_fmt fmt)
2873 {
2874 switch (fmt) {
2875 case TDE_DRV_COLOR_FMT_ARGB8888:
2876 case TDE_DRV_COLOR_FMT_AYCBCR8888:
2877 case TDE_DRV_COLOR_FMT_RABG8888:
2878 return 32; /* 32 fmt data */
2879 default:
2880 return -1;
2881 }
2882 }
2883
tde_hal_getbpp_by_fmt1(tde_color_fmt fmt)2884 static hi_s32 tde_hal_getbpp_by_fmt1(tde_color_fmt fmt)
2885 {
2886 switch (fmt) {
2887 case TDE_DRV_COLOR_FMT_CLUT1:
2888 case TDE_DRV_COLOR_FMT_A1:
2889 case TDE_DRV_COLOR_FMT_CLUT1B:
2890 case TDE_DRV_COLOR_FMT_A1B:
2891 return 1;
2892 default:
2893 return -1;
2894 }
2895 }
2896
tde_hal_getbpp_by_fmt2(tde_color_fmt fmt)2897 static hi_s32 tde_hal_getbpp_by_fmt2(tde_color_fmt fmt)
2898 {
2899 switch (fmt) {
2900 case TDE_DRV_COLOR_FMT_CLUT2:
2901 case TDE_DRV_COLOR_FMT_CLUT2B:
2902 return 2; /* 2 function return bpp */
2903 default:
2904 return -1; /* -1 return failure */
2905 }
2906 }
2907
tde_hal_getbpp_by_fmt4(tde_color_fmt fmt)2908 static hi_s32 tde_hal_getbpp_by_fmt4(tde_color_fmt fmt)
2909 {
2910 switch (fmt) {
2911 case TDE_DRV_COLOR_FMT_CLUT4:
2912 case TDE_DRV_COLOR_FMT_CLUT4B:
2913 return 4; /* 4 alg data */
2914 default:
2915 return -1;
2916 }
2917 }
2918
tde_hal_getbpp_by_fmt8(tde_color_fmt fmt)2919 static hi_s32 tde_hal_getbpp_by_fmt8(tde_color_fmt fmt)
2920 {
2921 switch (fmt) {
2922 case TDE_DRV_COLOR_FMT_CLUT8:
2923 case TDE_DRV_COLOR_FMT_ACLUT44:
2924 case TDE_DRV_COLOR_FMT_A8:
2925 case TDE_DRV_COLOR_FMT_BYTE:
2926 return 8; /* 8 fmt data */
2927 default:
2928 return -1;
2929 }
2930 }
2931
2932 /*
2933 * Function: tde_hal_get_resize_para_htable
2934 * Description: get index table according the step
2935 * Input: step: input step
2936 * Return: index table address
2937 */
tde_hal_get_resize_para_htable(hi_u32 step)2938 static hi_u32 tde_hal_get_resize_para_htable(hi_u32 step)
2939 {
2940 hi_u32 index;
2941
2942 if (step < TDE_RESIZE_8X32_AREA_0) {
2943 index = 0;
2944 } else if (step == TDE_RESIZE_8X32_AREA_0) {
2945 index = 1;
2946 } else if ((step > TDE_RESIZE_8X32_AREA_0) && (step <= TDE_RESIZE_8X32_AREA_1)) {
2947 index = 2; /* 2 ResizeParaHTable */
2948 } else if ((step > TDE_RESIZE_8X32_AREA_1) && (step <= TDE_RESIZE_8X32_AREA_2)) {
2949 index = 3; /* 3 ResizeParaHTable */
2950 } else if ((step > TDE_RESIZE_8X32_AREA_2) && (step <= TDE_RESIZE_8X32_AREA_3)) {
2951 index = 4; /* 4 ResizeParaHTable */
2952 } else if ((step > TDE_RESIZE_8X32_AREA_3) && (step <= TDE_RESIZE_8X32_AREA_4)) {
2953 index = 5; /* 5 ResizeParaHTable */
2954 } else {
2955 index = 6; /* 6 ResizeParaHTable */
2956 }
2957 return index;
2958 }
2959
2960 /*
2961 * Function: tde_hal_get_resize_para_vtable
2962 * Description: get table of parameter for resize
2963 * Input: step:input step
2964 * Return: address of table
2965 */
tde_hal_get_resize_para_vtable(hi_u32 step)2966 static hi_u32 tde_hal_get_resize_para_vtable(hi_u32 step)
2967 {
2968 hi_u32 index;
2969
2970 /* get index table according step, CNcomment: According to the step length to find index table */
2971 if (step < TDE_RESIZE_PARA_AREA_0) {
2972 index = 0;
2973 } else if (step == TDE_RESIZE_PARA_AREA_0) {
2974 index = 1;
2975 } else if ((step > TDE_RESIZE_PARA_AREA_0) && (step <= TDE_RESIZE_PARA_AREA_1)) {
2976 index = 2; /* 2 index resize */
2977 } else if ((step > TDE_RESIZE_PARA_AREA_1) && (step <= TDE_RESIZE_PARA_AREA_2)) {
2978 index = 3; /* 3 index resize */
2979 } else if ((step > TDE_RESIZE_PARA_AREA_2) && (step <= TDE_RESIZE_PARA_AREA_3)) {
2980 index = 4; /* 4 index resize */
2981 } else if ((step > TDE_RESIZE_PARA_AREA_3) && (step <= TDE_RESIZE_PARA_AREA_4)) {
2982 index = 5; /* 5 index resize */
2983 } else {
2984 index = 6; /* 6 index resize */
2985 }
2986 return index;
2987 }
2988
2989 /*
2990 * Function: tde_hal_init_queue
2991 * Description: Initialize Aq list,config the operation which is needed
2992 */
tde_hal_init_queue(hi_void)2993 static hi_void tde_hal_init_queue(hi_void)
2994 {
2995 /*
2996 * write 0 to Aq list start address register
2997 * CNcomment: 0 will be written Aq list first address register
2998 */
2999 tde_write_reg(g_base_vir_addr, TDE_AQ_NADDR_HI, 0);
3000 tde_write_reg(g_base_vir_addr, TDE_AQ_NADDR_LOW, 0);
3001 }
3002
3003 #ifndef HI_BUILD_IN_BOOT
3004 /*
3005 * Function: tde_hal_set_deflicer_level
3006 * Description: SetDeflicerLevel
3007 * Input: deflicker_level:anti-flicker levels including:auto,low,middle,high
3008 */
3009 #if (TDE_CAPABILITY & DEFLICKER)
tde_hal_set_deflicer_level(hi_tde_deflicker_level deflicker_level)3010 hi_s32 tde_hal_set_deflicer_level(hi_tde_deflicker_level deflicker_level)
3011 {
3012 g_deflicker_level = deflicker_level;
3013 return HI_SUCCESS;
3014 }
3015
tde_hal_get_deflicer_level(hi_tde_deflicker_level * deflicker_level)3016 hi_s32 tde_hal_get_deflicer_level(hi_tde_deflicker_level *deflicker_level)
3017 {
3018 *deflicker_level = g_deflicker_level;
3019 return HI_SUCCESS;
3020 }
3021 #endif
3022 #endif
3023
tde_hal_set_alpha_threshold(hi_u8 alpha_threshold_value)3024 hi_s32 tde_hal_set_alpha_threshold(hi_u8 alpha_threshold_value)
3025 {
3026 g_alpha_threshold_value = alpha_threshold_value;
3027
3028 return HI_SUCCESS;
3029 }
3030
3031 #ifndef HI_BUILD_IN_BOOT
tde_hal_get_alpha_threshold(hi_u8 * alpha_threshold_value)3032 hi_s32 tde_hal_get_alpha_threshold(hi_u8 *alpha_threshold_value)
3033 {
3034 *alpha_threshold_value = g_alpha_threshold_value;
3035
3036 return HI_SUCCESS;
3037 }
3038 #endif
3039
tde_hal_set_alpha_threshold_state(hi_bool alpha_threshold_en)3040 hi_s32 tde_hal_set_alpha_threshold_state(hi_bool alpha_threshold_en)
3041 {
3042 g_alpha_threshold = alpha_threshold_en;
3043
3044 return HI_SUCCESS;
3045 }
3046
3047 #ifndef HI_BUILD_IN_BOOT
tde_hal_get_alpha_threshold_state(hi_bool * alpha_threshold_en)3048 hi_s32 tde_hal_get_alpha_threshold_state(hi_bool *alpha_threshold_en)
3049 {
3050 *alpha_threshold_en = g_alpha_threshold;
3051
3052 return HI_SUCCESS;
3053 }
3054
3055 #ifdef CONFIG_HI_PROC_SHOW_SUPPORT
3056 /* see define of TDE_HWNode_S */
3057 hi_char *g_update[] = {
3058 "SRC1_CTRL ", /* 0x100 */
3059 "SRC1_CH0_ADDR_HIGH ", /* 0x104 */
3060 "SRC1_CH0_ADDR_LOW ", /* 0x108 */
3061 "SRC1_CH1_ADDR_HIGH ", /* 0x10c */
3062 "SRC1_CH1_ADDR_LOW ", /* 0x110 */
3063 "SRC1_CH0_STRIDE ", /* 0x114 */
3064 "SRC1_CH1_STRIDE ", /* 0x118 */
3065 "SRC1_IMGSIZE ", /* 0x11c */
3066 "SRC1_FILL ", /* 0x120 */
3067 "SRC1_ALPHA ", /* 0x124 */
3068 "SRC1_PIX_OFFSET ", "SRC2_CTRL ", /* 0x150 */
3069 "SRC2_CH0_ADDR_HIGH ", /* 0x154 */
3070 "SRC2_CH0_ADDR_LOW ", /* 0x158 */
3071 "SRC2_CH1_ADDR_HIGH ", /* 0x15c */
3072 "SRC2_CH1_ADDR_LOW ", /* 0x160 */
3073 "SRC2_CH0_STRIDE ", /* 0x164 */
3074 "SRC2_CH1_STRIDE ", /* 0x168 */
3075 "SRC2_IMGSIZE ", /* 0x16c */
3076 "SRC2_FILL ", /* 0x170 */
3077 "SRC2_ALPHA ", /* 0x174 */
3078 "SRC2_PIX_OFFSET ", "DES_CTRL ", /* 0x2a0 */
3079 "DES_CH0_ADDR_HIGH ", /* 0x2a4 */
3080 "DES_CH0_ADDR_LOW ", /* 0x2a8 */
3081 "DES_CH1_ADDR_HIGH ", /* 0x2ac */
3082 "DES_CH1_ADDR_LOW ", /* 0x2b0 */
3083 "DES_CH0_STRIDE ", /* 0x2b4 */
3084 "DES_CH1_STRIDE ", /* 0x2b8 */
3085 "DES_IMGSIZE ", /* 0x2bc */
3086 "DES_ALPHA ", /* 0x2c0 */
3087 "DES_CROP_POS_ST ", /* 0x2c4 */
3088 "DES_CROP_POS_ED ", /* 0x2c8 */
3089 "DES_PIX_OFFSET ", "SRC1_HSP ", /* 0x300 */
3090 "SRC1_HLOFFSET ", /* 0x304 */
3091 "SRC1_HCOFFSET ", /* 0x308 */
3092 "SRC1_VSP ", /* 0x30c */
3093 "SRC1_VSR ", /* 0x310 */
3094 "SRC1_VOFFSET ", /* 0x314 */
3095 "SRC1_ZMEORESO ", /* 0x318 */
3096 "SRC1_ZMEIRESO ", /* 0x31c */
3097 "SRC1_HPZME ", /* 0x320 */
3098 "SRC1_HPZME_SIZE ", /* 0x324 */
3099 #if ((HICHIP == HI3519A_V100) || (HICHIP == HI3516C_V500))
3100 "SRC1_CSC_IDC0 ", /* 0x328 */
3101 "SRC1_CSC_IDC1 ", /* 0x32c */
3102 "SRC1_CSC_ODC0 ", /* 0x330 */
3103 "SRC1_CSC_ODC1 ", /* 0x334 */
3104 #else
3105 "SRC1_CSC_IDC ", /* 0x230 */
3106 "SRC1_CSC_ODC ", /* 0x234 */
3107 #endif
3108 "SRC1_CSC_P0 ", /* 0x338 */
3109 "SRC1_CSC_P1 ", /* 0x33c */
3110 "SRC1_CSC_P2 ", /* 0x340 */
3111 "SRC1_CSC_P3 ", /* 0x344 */
3112 "SRC1_CSC_P4 ", /* 0x348 */
3113 #if ((HICHIP == HI3519A_V100) || (HICHIP == HI3516C_V500))
3114 "SRC1_DITHER_CTRL ", /* 0x34c */
3115 #endif
3116 "SRC2_HSP ", /* 0x350 */
3117 "SRC2_HLOFFSET ", /* 0x354 */
3118 "SRC2_HCOFFSET ", /* 0x358 */
3119 "SRC2_VSP ", /* 0x35c */
3120 "SRC2_VSR ", /* 0x360 */
3121 "SRC2_VOFFSET ", /* 0x364 */
3122 "SRC2_ZMEORESO ", /* 0x368 */
3123 "SRC2_ZMEIRESO ", /* 0x36c */
3124 "SRC2_HPZME ", /* 0x370 */
3125 "SRC2_HPZME_SIZE ", /* 0x374 */
3126 "SRC2_CSC_MUX ", /* 0x378 */
3127 #if ((HICHIP == HI3519A_V100) || (HICHIP == HI3516C_V500))
3128 "DES_CSC_IDC0 ", /* 0x37c */
3129 "DES_CSC_IDC1 ", /* 0x380 */
3130 "DES_CSC_ODC0 ", /* 0x384 */
3131 "DES_CSC_ODC1 ", /* 0x388 */
3132 #else
3133 "DES_CSC_IDC ", /* 0x2c0 */
3134 "DES_CSC_ODC ", /* 0x2c4 */
3135 #endif
3136 "DES_CSC_P0 ", /* 0x38c */
3137 "DES_CSC_P1 ", /* 0x390 */
3138 "DES_CSC_P2 ", /* 0x394 */
3139 "DES_CSC_P3 ", /* 0x398 */
3140 "DES_CSC_P4 ", /* 0x39c */
3141 #if ((HICHIP == HI3519A_V100) || (HICHIP == HI3516C_V500))
3142 "DST_DITHER_CTRL ", /* 0x3a0 */
3143 #endif
3144 "DES_DSWM ", /* 0x3a4 */
3145 "SRC2_RTT_CTRL ", /* 0x3f0 */
3146 "CBMCTRL ", /* 0x400 */
3147 "CBMBKG ", /* 0x404 */
3148 "CBMCOLORIZE ", /* 0x408 */
3149 "CBMALUPARA ", /* 0x40c */
3150 "CBMKEYPARA ", /* 0x410 */
3151 "CBMKEYMIN ", /* 0x414 */
3152 "CBMKEYMAX ", /* 0x418 */
3153 "CBMKEYMASK ", /* 0x41c */
3154 "SRC1_CBMPARA ", /* 0x420 */
3155 "SRC1_CBMSTPOS ", /* 0x424 */
3156 "SRC2_CBMPARA ", /* 0x428 */
3157 "SRC2_CBMSTPOS ", /* 0x32c */
3158 "SRC1_ZME_LHADDR_HIGH", /* 0x0 */
3159 "SRC1_ZME_LHADDR_LOW", /* 0x4 */
3160 "SRC1_ZME_LVADDR_HIGH", /* 0x8 */
3161 "SRC1_ZME_LVADDR_LOW", /* 0xc */
3162 "SRC1_ZME_CHADDR_HIGH", /* 0x10 */
3163 "SRC1_ZME_CHADDR_LOW", /* 0x14 */
3164 "SRC1_ZME_CVADDR_HIGH", /* 0x18 */
3165 "SRC1_ZME_CVADDR_LOW", /* 0x1c */
3166 "SRC2_ZME_LHADDR_HIGH", /* 0x20 */
3167 "SRC2_ZME_LHADDR_LOW", /* 0x24 */
3168 "SRC2_ZME_LVADDR_HIGH", /* 0x28 */
3169 "SRC2_ZME_LVADDR_LOW", /* 0x2c */
3170 "SRC2_ZME_CHADDR_HIGH", /* 0x30 */
3171 "SRC2_ZME_CHADDR_LOW", /* 0x34 */
3172 "SRC2_ZME_CVADDR_HIGH", /* 0x38 */
3173 "SRC2_ZME_CVADDR_LOW", /* 0x3c */
3174 "CLUT_ADDR_HIGH", /* 0x40 */
3175 "CLUT_ADDR_LOW", /* 0x44 */
3176 };
3177
3178 #if (HICHIP == HI3516C_V500)
tde_hal_node_print_cv500(osal_proc_entry_t * p,hi_u32 * cur_node)3179 static hi_void tde_hal_node_print_cv500(osal_proc_entry_t *p, hi_u32 *cur_node)
3180 {
3181 hi_s32 i;
3182 for (i = 0; i < 11; i++) { /* 11 SRC1_CTRL 0x100 */
3183 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i], *(cur_node + i + 64)); /* 64 cur node data */
3184 }
3185
3186 for (i = 0; i < 11; i++) { /* 11 SRC2_CTRL 0x150 */
3187 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 11], *(cur_node + i + 84)); /* 11 84 cur node data */
3188 }
3189
3190 for (i = 0; i < 12; i++) { /* 12 DES_CTRL 0x2a0 */
3191 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 22], *(cur_node + i + 168)); /* 22 168 cur node data */
3192 }
3193
3194 for (i = 0; i < 42; i++) { /* 42 SRC1_HSP 0x300 */
3195 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 34], *(cur_node + i + 192)); /* 34 192 cur node data */
3196 }
3197 for (i = 0; i < 1; i++) { /* 1 SRC2_RTT_CTRL 0x3f0 */
3198 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 76], *(cur_node + i + 252)); /* 76 252 cur node data */
3199 }
3200 for (i = 0; i < 12; i++) { /* 12 CBMCTRL 0x400 */
3201 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 77], *(cur_node + i + 256)); /* 77 256 cur node data */
3202 }
3203 for (i = 0; i < 18; i++) { /* 18 TDE_SRC1_ZME_LHADDR 0x0 */
3204 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 89], *(cur_node + i)); /* 89 cur node data */
3205 }
3206 }
3207 #elif (HICHIP == HI3519A_V100)
tde_hal_node_print_19a(osal_proc_entry_t * p,hi_u32 * cur_node)3208 static hi_void tde_hal_node_print_19a(osal_proc_entry_t *p, hi_u32 *cur_node)
3209 {
3210 hi_s32 i;
3211 for (i = 0; i < 22; i++) { /* 22 SRC1_CTRL 0x0 */
3212 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i], *(cur_node + i));
3213 }
3214
3215 for (i = 0; i < 12; i++) { /* 12 DES_CTRL 0x0f8 */
3216 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 22], *(cur_node + i + 62)); /* 22 62 cur node data */
3217 }
3218
3219 for (i = 0; i < 8; i++) { /* 8 SRC1_HSP 0x200 */
3220 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 34], *(cur_node + i + 128)); /* 34 128 cur node data */
3221 }
3222
3223 for (i = 0; i < 12; i++) { /* 12 SRC1_HPZME 0x228 */
3224 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 42], *(cur_node + i + 138)); /* 42 138 cur node data */
3225 }
3226
3227 for (i = 0; i < 8; i++) { /* 8 SRC2_HSP 0x280 */
3228 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 54], *(cur_node + i + 160)); /* 54 160 cur node data */
3229 }
3230
3231 for (i = 0; i < 14; i++) { /* 14 SRC2_HPZME 0x2a8 */
3232 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 62], *(cur_node + i + 170)); /* 62 170 cur node data */
3233 }
3234
3235 for (i = 0; i < 1; i++) { /* SRC2_RTT_CTRL 0x3f0 */
3236 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 76], *(cur_node + i + 252)); /* 76 252 cur node data */
3237 }
3238
3239 for (i = 0; i < 12; i++) { /* 12 CBMCTRL 0x300 */
3240 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 77], *(cur_node + i + 192)); /* 77 192 cur node data */
3241 }
3242
3243 for (i = 0; i < 18; i++) { /* 18 TDE_SRC1_ZME_LHADDR 0x480 */
3244 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 89], *(cur_node + i + 288)); /* 89 288 cur node data */
3245 }
3246 }
3247 #else
tde_hal_node_print_all(osal_proc_entry_t * p,hi_u32 * cur_node)3248 static hi_void tde_hal_node_print_all(osal_proc_entry_t *p, hi_u32 *cur_node)
3249 {
3250 hi_s32 i;
3251 for (i = 0; i < 22; i++) { /* 22 SRC1_CTRL 0x0 */
3252 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i], *(cur_node + i));
3253 }
3254
3255 for (i = 0; i < 12; i++) { /* 12 DES_CTRL 0x0f8 */
3256 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 22], *(cur_node + i + 62)); /* 62 22 cur node data */
3257 }
3258
3259 for (i = 0; i < 8; i++) { /* 8 SRC1_HSP 0x200 */
3260 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 34], *(cur_node + i + 128)); /* 34 128 cur node data */
3261 }
3262
3263 for (i = 0; i < 9; i++) { /* 9 SRC1_HPZME 0x228 */
3264 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 42], *(cur_node + i + 138)); /* 42 138 cur node data */
3265 }
3266
3267 for (i = 0; i < 8; i++) { /* 8 SRC2_HSP 0x280 */
3268 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 51], *(cur_node + i + 160)); /* 51 160 cur node data */
3269 }
3270
3271 for (i = 0; i < 3; i++) { /* 3 SRC2_HPZME 0x2a8 */
3272 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 59], *(cur_node + i + 170)); /* 59 170 cur node data */
3273 }
3274
3275 for (i = 0; i < 8; i++) { /* 8 DES_CSC_IDC 0x2c0 */
3276 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 62], *(cur_node + i + 176)); /* 62 176 cur node data */
3277 }
3278
3279 for (i = 0; i < 1; i++) { /* SRC2_RTT_CTRL 0x3f0 */
3280 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 70], *(cur_node + i + 252)); /* 70 252 cur node data */
3281 }
3282
3283 for (i = 0; i < 12; i++) { /* 12 CBMCTRL 0x300 */
3284 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 71], *(cur_node + i + 192)); /* 71 192 cur node data */
3285 }
3286
3287 for (i = 0; i < 18; i++) { /* 18 TDE_SRC1_ZME_LHADDR 0x480 */
3288 osal_seq_printf(p, "(%s):\t0x%08x\n", g_update[i + 83], *(cur_node + i + 288)); /* 83 288 cur node data */
3289 }
3290 }
3291 #endif
3292
tde_hal_node_print_info(osal_proc_entry_t * p,hi_u32 * cur_node)3293 osal_proc_entry_t *tde_hal_node_print_info(osal_proc_entry_t *p, hi_u32 *cur_node)
3294 {
3295 if (p == HI_NULL) {
3296 return 0;
3297 }
3298 /* print node information */
3299 osal_seq_printf(p, "\n--------- Hisilicon TDE Node params Info ---------\n");
3300 #if (HICHIP == HI3516C_V500)
3301 tde_hal_node_print_cv500(p, cur_node);
3302 #elif (HICHIP == HI3519A_V100)
3303 tde_hal_node_print_19a(p, cur_node);
3304 #else
3305 tde_hal_node_print_all(p, cur_node);
3306 #endif
3307 return p;
3308 }
3309 #endif
3310 #endif
3311