1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: \n 16 * 17 * History: \n 18 * 2023-03-02, Create file. \n 19 */ 20 #ifndef HAL_RTC_V100_REGS_DEF_H 21 #define HAL_RTC_V100_REGS_DEF_H 22 23 #include <stdint.h> 24 25 #ifdef __cplusplus 26 #if __cplusplus 27 extern "C" { 28 #endif /* __cplusplus */ 29 #endif /* __cplusplus */ 30 31 /** 32 * @defgroup drivers_hal_rtc_v100_regs_def RTC V100 Regs Defination 33 * @ingroup drivers_hal_rtc 34 * @{ 35 */ 36 37 #define RTC_REGS_MAX_NUM 4 38 39 /** 40 * @brief This union represents the bit fields in the Control. \n 41 * Read the register into the <i>d32</i> member then 42 * set/clear the bits using the <i>b</i> elements. 43 */ 44 typedef union rtc_control_reg_data { 45 uint32_t d32; /*!< Raw register data. */ 46 struct { 47 uint32_t enable : 1; /*!< RTC enable bit. */ 48 uint32_t mode : 1; /*!< RTC mode bit. */ 49 uint32_t int_mask : 1; 50 uint32_t reserved3_31 : 29; 51 } b; /*!< Register bits. */ 52 } rtc_control_reg_data_t; 53 54 /** 55 * @brief This union represents the bit fields in the End-of-Interrupt. \n 56 * Read the register into the <i>d32</i> member then 57 * set/clear the bits using the <i>b</i> elements. 58 */ 59 typedef union rtc_eoi_data { 60 uint32_t d32; /*!< Raw register data. */ 61 struct { 62 uint32_t eoi : 1; /*!< Reading from this register returns zeroes(0) 63 and clear the interrupt. */ 64 uint32_t reserved1_31 : 31; 65 } b; /*!< Register bits. */ 66 } rtc_eoi_data_t; 67 68 typedef struct rtc_regs_info { 69 volatile uint32_t load_count; /*!< Value to be loaded into RTC. <i>Offset: 00h</i>. */ 70 volatile uint32_t current_value; /*!< Current Value of RTC. <i>Offset: 04h</i>. */ 71 volatile uint32_t control_reg; /*!< Control Register for RTC. <i>Offset: 08h</i>. */ 72 volatile uint32_t eoi; /*!< Clears the interrupt from RTC. <i>Offset: 0Ch</i>. */ 73 volatile uint32_t int_status; /*!< Contains the interrupt status for RTC. <i>Offset: 10h</i>. */ 74 } rtc_regs_info_t; 75 76 typedef struct rtc_regs { 77 volatile rtc_regs_info_t g_rtc_regs_info[RTC_REGS_MAX_NUM]; /*!< RTC regs. 78 <i>Offset: 000h + i*0x14h</i>. */ 79 } rtc_regs_t; 80 /** 81 * @} 82 */ 83 84 #ifdef __cplusplus 85 #if __cplusplus 86 } 87 #endif /* __cplusplus */ 88 #endif /* __cplusplus */ 89 90 #endif