1 /**
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 *
15 * Description: Provide rtc port \n
16 *
17 * History: \n
18 * 2023-03-02, Create file. \n
19 */
20
21 #include "soc_osal.h"
22 #include "common_def.h"
23 #include "hal_rtc_v100.h"
24 #include "chip_core_irq.h"
25 #include "rtc_porting.h"
26
27 #define RTC_BASE_ADDR 0x57024000
28 #define RTC_0_BASE_ADDR (RTC_BASE_ADDR + 0x00)
29 #define RTC_1_BASE_ADDR (RTC_BASE_ADDR + 0x14)
30 #define RTC_2_BASE_ADDR (RTC_BASE_ADDR + 0x28)
31 #define RTC_3_BASE_ADDR (RTC_BASE_ADDR + 0x3C)
32
33 static uintptr_t g_rtc_base_addr[RTC_MAX_NUM] = {
34 RTC_0_BASE_ADDR,
35 RTC_1_BASE_ADDR,
36 RTC_2_BASE_ADDR,
37 RTC_3_BASE_ADDR,
38 };
39
rtc_porting_comm_addr_get(void)40 uintptr_t rtc_porting_comm_addr_get(void)
41 {
42 return RTC_BASE_ADDR;
43 }
44
rtc_porting_base_addr_get(rtc_index_t index)45 uintptr_t rtc_porting_base_addr_get(rtc_index_t index)
46 {
47 return g_rtc_base_addr[index];
48 }
49
rtc0_irq_handler(int i,void * p)50 static int rtc0_irq_handler(int i, void *p)
51 {
52 unused(i);
53 unused(p);
54 hal_rtc_v100_irq_handler(RTC_0);
55 osal_irq_clear(RTC_0_IRQN);
56 return 0;
57 }
58
rtc1_irq_handler(int i,void * p)59 static int rtc1_irq_handler(int i, void *p)
60 {
61 unused(i);
62 unused(p);
63 hal_rtc_v100_irq_handler(RTC_1);
64 return 0;
65 }
66
rtc2_irq_handler(int i,void * p)67 static int rtc2_irq_handler(int i, void *p)
68 {
69 unused(i);
70 unused(p);
71 hal_rtc_v100_irq_handler(RTC_2);
72 return 0;
73 }
74
75
rtc3_irq_handler(int i,void * p)76 static int rtc3_irq_handler(int i, void *p)
77 {
78 unused(i);
79 unused(p);
80 hal_rtc_v100_irq_handler(RTC_3);
81 return 0;
82 }
83
84 static osal_irq_handler const rtc_irq_handler[RTC_MAX_NUM] = {
85 rtc0_irq_handler,
86 rtc1_irq_handler,
87 rtc2_irq_handler,
88 rtc3_irq_handler,
89 };
90
rtc_port_register_irq(rtc_index_t index,uint32_t id,uint16_t priority)91 void rtc_port_register_irq(rtc_index_t index, uint32_t id, uint16_t priority)
92 {
93 osal_irq_disable(id);
94 osal_irq_request(id, rtc_irq_handler[index], NULL, NULL, NULL);
95 osal_irq_set_priority(id, priority);
96 osal_irq_enable(id);
97 }
98
rtc_port_unregister_irq(rtc_index_t index,uint32_t id)99 void rtc_port_unregister_irq(rtc_index_t index, uint32_t id)
100 {
101 unused(index);
102 osal_irq_disable(id);
103 osal_irq_free(id, NULL);
104 }
105
106 static uint32_t g_rtc_clock_value = CONFIG_RTC_CLOCK_VALUE;
107
rtc_porting_clock_value_update(uint32_t clock)108 void rtc_porting_clock_value_update(uint32_t clock)
109 {
110 g_rtc_clock_value = clock;
111 }
112
rtc_porting_clock_value_get(void)113 uint32_t rtc_porting_clock_value_get(void)
114 {
115 return g_rtc_clock_value;
116 }
117
rtc_porting_ms_2_cycle(uint32_t ms)118 uint64_t rtc_porting_ms_2_cycle(uint32_t ms)
119 {
120 uint32_t clock_value = rtc_porting_clock_value_get();
121 return ((uint64_t)ms * clock_value / MS_PER_S);
122 }
123
rtc_hw_porting_ms_2_cycle(uint64_t ms)124 uint64_t rtc_hw_porting_ms_2_cycle(uint64_t ms)
125 {
126 uint32_t clock_value = rtc_porting_clock_value_get();
127 return (ms * (uint64_t)clock_value / MS_PER_S);
128 }
129
rtc_porting_cycle_2_us(uint64_t cycle)130 uint32_t rtc_porting_cycle_2_us(uint64_t cycle)
131 {
132 uint32_t clock_value = rtc_porting_clock_value_get();
133 return (uint32_t)((cycle * (MS_PER_S * US_PER_MS)) / (clock_value));
134 }
135
rtc_porting_compensat_by_tcxo(uint64_t diff)136 uint64_t rtc_porting_compensat_by_tcxo(uint64_t diff)
137 {
138 if (diff < RTC_COMPENSAT_1_CYCLE_BY_TCXO) {
139 return 0;
140 } else if (diff < RTC_COMPENSAT_2_CYCLE_BY_TCXO) {
141 return RTC_1_CYCLE;
142 } else if (diff < RTC_COMPENSAT_3_CYCLE_BY_TCXO) {
143 return RTC_2_CYCLE;
144 } else {
145 return diff / RTC_COMPENSAT_1_CYCLE_BY_TCXO;
146 }
147 }