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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2016 Chris Zhong <zyw@rock-chips.com>
4  * Copyright (C) 2016 ROCKCHIP, Inc.
5  */
6 
7 #ifndef _CDN_DP_CORE_H
8 #define _CDN_DP_CORE_H
9 
10 #include <drm/drm_dp_helper.h>
11 #include <drm/drm_panel.h>
12 #include <drm/drm_probe_helper.h>
13 
14 #include "rockchip_drm_drv.h"
15 
16 #define MAX_PHY 2
17 
18 enum audio_format {
19     AFMT_I2S = 0,
20     AFMT_SPDIF = 1,
21     AFMT_UNUSED,
22 };
23 
24 struct audio_info {
25     enum audio_format format;
26     int sample_rate;
27     int channels;
28     int sample_width;
29 };
30 
31 enum vic_pxl_encoding_format {
32     PXL_RGB = 0x1,
33     YCBCR_4_4_4 = 0x2,
34     YCBCR_4_2_2 = 0x4,
35     YCBCR_4_2_0 = 0x8,
36     Y_ONLY = 0x10,
37 };
38 
39 struct video_info {
40     bool h_sync_polarity;
41     bool v_sync_polarity;
42     bool interlaced;
43     int color_depth;
44     enum vic_pxl_encoding_format color_fmt;
45 };
46 
47 struct cdn_firmware_header {
48     u32 size_bytes;  /* size of the entire header+image(s) in bytes */
49     u32 header_size; /* size of just the header in bytes */
50     u32 iram_size;   /* size of iram */
51     u32 dram_size;   /* size of dram */
52 };
53 
54 struct cdn_dp_port {
55     struct cdn_dp_device *dp;
56     struct phy *phy;
57     u8 lanes;
58     bool phy_enabled;
59     u8 id;
60 };
61 
62 struct cdn_dp_device {
63     struct device *dev;
64     struct drm_device *drm_dev;
65     struct drm_connector connector;
66     struct drm_encoder encoder;
67     struct drm_display_mode mode;
68     struct platform_device *audio_pdev;
69     struct delayed_work event_work;
70     struct edid *edid;
71     struct rockchip_drm_sub_dev sub_dev;
72 
73     struct mutex lock;
74     bool connected;
75     bool active;
76     bool suspended;
77 
78     const struct firmware *fw; /* cdn dp firmware */
79     unsigned int fw_version;   /* cdn fw version */
80     bool fw_loaded;
81 
82     void __iomem *regs;
83     struct regmap *grf;
84     struct clk *core_clk;
85     struct clk *pclk;
86     struct clk *spdif_clk;
87     struct clk *grf_clk;
88     struct reset_control *spdif_rst;
89     struct reset_control *dptx_rst;
90     struct reset_control *apb_rst;
91     struct reset_control *core_rst;
92     struct audio_info audio_info;
93     struct video_info video_info;
94     struct cdn_dp_port *port[MAX_PHY];
95     u8 ports;
96     u8 max_lanes;
97     unsigned int max_rate;
98     u8 lanes;
99     int active_port;
100 
101     u8 dpcd[DP_RECEIVER_CAP_SIZE];
102     bool sink_has_audio;
103 };
104 #endif /* _CDN_DP_CORE_H */
105