1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: Provides V151 ssi register \n 16 * 17 * History: \n 18 * 2022-08-08, Create file. \n 19 */ 20 #ifndef HAL_SPI_V151_REGS_DEF_H 21 #define HAL_SPI_V151_REGS_DEF_H 22 23 #include <stdint.h> 24 25 #ifdef __cplusplus 26 #if __cplusplus 27 extern "C" { 28 #endif /* __cplusplus */ 29 #endif /* __cplusplus */ 30 31 /** 32 * @defgroup drivers_hal_spi_v151_regs_def SPI V151 Regs Definition 33 * @ingroup drivers_hal_spi 34 * @{ 35 */ 36 37 #define HAL_SPI_DRNM_REG_SIZE 36 38 39 /** 40 * @brief This union represents the bit fields in the Control Register 0. \n 41 * Read the register into the <i>d32</i> member then 42 * set/clear the bits using the <i>b</i> elements. 43 */ 44 typedef union spi_ctra_data { 45 uint32_t d32; /*!< Raw register data. */ 46 struct { 47 uint32_t soe : 1; 48 uint32_t srlt : 1; 49 uint32_t ssn_te : 1; 50 uint32_t scph : 1; 51 uint32_t scpol : 1; 52 uint32_t cfs16 : 4; 53 uint32_t dfs16 : 4; 54 uint32_t dfs32 : 5; 55 uint32_t trsm : 2; 56 uint32_t enhff : 2; 57 uint32_t prs : 2; 58 uint32_t reserved24_31 : 6; 59 } b; /*!< Register bits. */ 60 } spi_ctra_data_t; 61 62 /** 63 * @brief This union represents the bit fields in the Control Register 1. \n 64 * Read the register into the <i>d32</i> member then 65 * set/clear the bits using the <i>b</i> elements. 66 */ 67 typedef union spi_ctrb_data { 68 uint32_t d32; /*!< Raw register data. */ 69 struct { 70 uint32_t nrdf : 16; 71 } b; /*!< Register bits. */ 72 } spi_ctrb_data_t; 73 74 /** 75 * @brief This union represents the bit fields in the SPI Enable Register. \n 76 * Read the register into the <i>d32</i> member then 77 * set/clear the bits using the <i>b</i> elements. 78 */ 79 typedef union spi_er_data { 80 uint32_t d32; /*!< Raw register data. */ 81 struct { 82 uint32_t start_en : 1; 83 } b; /*!< Register bits. */ 84 } spi_er_data_t; 85 86 /** 87 * @brief This union represents the bit fields in the Microwire Control Register. \n 88 * Read the register into the <i>d32</i> member then 89 * set/clear the bits using the <i>b</i> elements. 90 */ 91 typedef union spi_mcr_data { 92 uint32_t d32; /*!< Raw register data. */ 93 struct { 94 uint32_t mh : 1; 95 uint32_t mss : 1; 96 uint32_t mtrc : 1; 97 } b; /*!< Register bits. */ 98 } spi_mcr_data_t; 99 100 /** 101 * @brief This union represents the bit fields in the Slave Enable Register. \n 102 * Read the register into the <i>d32</i> member then 103 * set/clear the bits using the <i>b</i> elements. 104 */ 105 typedef union spi_slenr_data { 106 uint32_t d32; /*!< Raw register data. */ 107 struct { 108 uint32_t ssef : 16; 109 } b; /*!< Register bits. */ 110 } spi_slenr_data_t; 111 112 /** 113 * @brief This union represents the bit fields in the Slave Enable Register. \n 114 * Read the register into the <i>d32</i> member then 115 * set/clear the bits using the <i>b</i> elements. 116 */ 117 typedef union spi_brs_data { 118 uint32_t d32; /*!< Raw register data. */ 119 struct { 120 uint32_t frdv : 16; 121 } b; /*!< Register bits. */ 122 } spi_brs_data_t; 123 124 /** 125 * @brief This union represents the bit fields in the Transmit FIFO Threshold Level. \n 126 * Read the register into the <i>d32</i> member then 127 * set/clear the bits using the <i>b</i> elements. 128 */ 129 typedef union spi_twlr_data { 130 uint32_t d32; /*!< Raw register data. */ 131 struct { 132 uint32_t twl; 133 } b; /*!< Register bits. */ 134 } spi_twlr_data_t; 135 136 /** 137 * @brief This union represents the bit fields in the Receive FIFO Threshold Level. \n 138 * Read the register into the <i>d32</i> member then 139 * set/clear the bits using the <i>b</i> elements. 140 */ 141 typedef union spi_rwlr_data { 142 uint32_t d32; /*!< Raw register data. */ 143 struct { 144 uint32_t rwl; 145 } b; /*!< Register bits. */ 146 } spi_rwlr_data_t; 147 148 /** 149 * @brief This union represents the bit fields in the Transmit FIFO Level Register. \n 150 * Read the register into the <i>d32</i> member then 151 * set/clear the bits using the <i>b</i> elements. 152 */ 153 typedef union spi_tlr_data { 154 uint32_t d32; /*!< Raw register data. */ 155 struct { 156 uint32_t tfl; /*!< <b>Transmit FIFO Level.</b> \n 157 Contains the number of valid data entries in the transmit FIFO. */ 158 } b; /*!< Register bits. */ 159 } spi_tlr_data_t; 160 161 /** 162 * @brief This union represents the bit fields in the Receive FIFO Level Register. \n 163 * Read the register into the <i>d32</i> member then 164 * set/clear the bits using the <i>b</i> elements. 165 */ 166 typedef union spi_rlr_data { 167 uint32_t d32; /*!< Raw register data. */ 168 struct { 169 uint32_t rfl; /*!< <b>Receive FIFO Level.</b> \n 170 Contains the number of valid data entries in the receive FIFO. */ 171 } b; /*!< Register bits. */ 172 } spi_rlr_data_t; 173 174 /** 175 * @brief This union represents the bit fields in the Receive FIFO Level Register. \n 176 * Read the register into the <i>d32</i> member then 177 * set/clear the bits using the <i>b</i> elements. 178 */ 179 typedef union spi_wsr_data { 180 uint32_t d32; /*!< Raw register data. */ 181 struct { 182 uint32_t dcfe_tfee : 1; 183 uint32_t reserved1_3 : 3; 184 uint32_t rfne : 1; 185 uint32_t rffe : 1; 186 uint32_t reserved6_10 : 5; 187 uint32_t tfnf : 1; 188 uint32_t tfe : 1; 189 uint32_t reserved13_14 : 2; 190 uint32_t sbf : 1; 191 uint32_t reserved16_31; 192 } b; /*!< Register bits. */ 193 } spi_wsr_data_t; 194 195 /** 196 * @brief This union represents the bit fields in the Interrupt Registers. \n 197 * Read the register into the <i>d32</i> member then 198 * set/clear the bits using the <i>b</i> elements. 199 */ 200 union spi_v151_interrupt_data { 201 uint32_t d32; /*!< Raw register data. */ 202 struct { 203 uint32_t rffis : 1; 204 uint32_t rfofis : 1; 205 uint32_t rfufis : 1; 206 uint32_t reserved3_6 : 4; 207 uint32_t tfeis : 1; 208 uint32_t tfofis : 1; 209 uint32_t reserved9_14 : 6; 210 uint32_t mmcris : 1; 211 } b; /*!< Register bits. */ 212 }; 213 214 /** 215 * @brief This union represents the bit fields in the Interrupt Mask Register. \n 216 * Read the register into the <i>d32</i> member then 217 * set/clear the bits using the <i>b</i> elements. 218 */ 219 typedef union spi_v151_interrupt_data spi_inmar_data_t; 220 221 /** 222 * @brief This union represents the bit fields in the Interrupt Status Register. \n 223 * Read the register into the <i>d32</i> member then 224 * set/clear the bits using the <i>b</i> elements. 225 */ 226 typedef union spi_v151_interrupt_data spi_insr_data_t; 227 228 /** 229 * @brief This union represents the bit fields in the Raw Interrupt Status Register. \n 230 * Read the register into the <i>d32</i> member then 231 * set/clear the bits using the <i>b</i> elements. 232 */ 233 typedef union spi_v151_interrupt_data spi_rainsr_data_t; 234 235 /** 236 * @brief This union represents the bit fields in the Interrupt Clear Register Register. \n 237 * Read the register into the <i>d32</i> member then 238 * set/clear the bits using the <i>b</i> elements. 239 */ 240 typedef union spi_icr_data { 241 uint32_t d32; /*!< Raw register data. */ 242 struct { 243 uint32_t cis : 1; 244 uint32_t reserved1_31 : 31; 245 } b; /*!< Register bits. */ 246 } spi_icr_data_t; 247 248 /** 249 * @brief This union represents the bit fields in the Transmit FIFO Overflow Interrupt Clear Register Register. \n 250 * Read the register into the <i>d32</i> member then 251 * set/clear the bits using the <i>b</i> elements. 252 */ 253 typedef union spi_icr_data spi_tfoficr_data_t; 254 255 /** 256 * @brief This union represents the bit fields in the Receive FIFO Overflow Interrupt Clear Register Register. \n 257 * Read the register into the <i>d32</i> member then 258 * set/clear the bits using the <i>b</i> elements. 259 */ 260 typedef union spi_icr_data spi_rxoicr_data_t; 261 262 /** 263 * @brief This union represents the bit fields in the Receive FIFO Underflow Interrupt Clear Register Register. \n 264 * Read the register into the <i>d32</i> member then 265 * set/clear the bits using the <i>b</i> elements. 266 */ 267 typedef union spi_icr_data spi_rfficr_data_t; 268 269 /** 270 * @brief This union represents the bit fields in the Multi-Master Interrupt Clear Register Register. \n 271 * Read the register into the <i>d32</i> member then 272 * set/clear the bits using the <i>b</i> elements. 273 */ 274 typedef union spi_icr_data spi_msticr_data_t; 275 276 /** 277 * @brief This union represents the bit fields in the DMA Control Register. \n 278 * Read the register into the <i>d32</i> member then 279 * set/clear the bits using the <i>b</i> elements. 280 */ 281 typedef union spi_dcr_data { 282 uint32_t d32; /*!< Raw register data. */ 283 struct { 284 uint32_t tden : 1; 285 uint32_t rden : 1; 286 uint32_t reserved2_31 : 30; 287 } b; /*!< Register bits. */ 288 } spi_dcr_data_t; 289 290 /** 291 * @brief This union represents the bit fields in the DMA Data Level Register. \n 292 * Read the register into the <i>d32</i> member then 293 * set/clear the bits using the <i>b</i> elements. 294 */ 295 union spi_v151_dmadlr_data { 296 uint32_t d32; /*!< Raw register data. */ 297 struct { 298 uint32_t dl; 299 } b; /*!< Register bits. */ 300 }; 301 302 /** 303 * @brief This union represents the bit fields in the DMA Transmit Data Level Register. \n 304 * Read the register into the <i>d32</i> member then 305 * set/clear the bits using the <i>b</i> elements. 306 */ 307 typedef union spi_v151_dmadlr_data spi_dtdl_data_t; 308 309 /** 310 * @brief This union represents the bit fields in the DMA Receive Data Level Register. \n 311 * Read the register into the <i>d32</i> member then 312 * set/clear the bits using the <i>b</i> elements. 313 */ 314 typedef union spi_v151_dmadlr_data spi_drdl_data_t; 315 316 /** 317 * @brief This union represents the bit fields in the coreKit version ID Register. \n 318 * Read the register into the <i>d32</i> member then 319 * set/clear the bits using the <i>b</i> elements. 320 */ 321 typedef union spi_id_data { 322 uint32_t d32; /*!< Raw register data. */ 323 struct { 324 uint32_t id; 325 } b; /*!< Register bits. */ 326 } spi_id_data_t; 327 328 /** 329 * @brief This union represents the bit fields in the Data Register. \n 330 * Read the register into the <i>d32</i> member then 331 * set/clear the bits using the <i>b</i> elements. 332 */ 333 typedef union spi_drnm_data { 334 uint32_t d32; /*!< Raw register data. */ 335 struct { 336 uint32_t datar; 337 } b; /*!< Register bits. */ 338 } spi_drnm_data_t; 339 340 /** 341 * @brief This union represents the bit fields in the RX Sample Delay Register. \n 342 * Read the register into the <i>d32</i> member then 343 * set/clear the bits using the <i>b</i> elements. 344 */ 345 typedef union spi_rsdr_data { 346 uint32_t d32; /*!< Raw register data. */ 347 struct { 348 uint32_t rxdsd : 8; 349 uint32_t reserved8_31 : 24; 350 } b; /*!< Register bits. */ 351 } spi_rsdr_data_t; 352 353 /** 354 * @brief This union represents the bit fields in the SPI Control 0 Register. \n 355 * Read the register into the <i>d32</i> member then 356 * set/clear the bits using the <i>b</i> elements. 357 */ 358 typedef union spi_enhctl_data { 359 uint32_t d32; /*!< Raw register data. */ 360 struct { 361 uint32_t waitnum : 5; 362 uint32_t aaitf : 2; 363 uint32_t rdsen : 1; 364 uint32_t addrlen : 4; 365 uint32_t ilen : 2; 366 uint32_t iddren : 1; 367 uint32_t ddren : 1; 368 uint32_t reserved16_31 : 18; 369 } b; /*!< Register bits. */ 370 } spi_enhctl_data_t; 371 372 /** 373 * @brief This union represents the bit fields in the Transmit Drive Edge Register. \n 374 * Read the register into the <i>d32</i> member then 375 * set/clear the bits using the <i>b</i> elements. 376 */ 377 typedef union spi_tder_data { 378 uint32_t d32; /*!< Raw register data. */ 379 struct { 380 uint32_t txdde : 8; 381 uint32_t reserved8_31 : 24; 382 } b; /*!< Register bits. */ 383 } spi_tder_data_t; 384 385 /** 386 * @brief Registers associated with spi. 387 */ 388 typedef struct spi_v151_regs { 389 volatile uint32_t spi_er; 390 volatile uint32_t spi_ctra; 391 volatile uint32_t spi_ctrb; 392 volatile uint32_t spi_enhctl; 393 volatile uint32_t spi_mcr; 394 volatile uint32_t spi_brs; 395 volatile uint32_t spi_dcr; 396 volatile uint32_t spi_drdl; 397 volatile uint32_t spi_dtdl; 398 volatile uint32_t spi_rsdr; 399 volatile uint32_t spi_tder; 400 volatile uint32_t spi_drnm[HAL_SPI_DRNM_REG_SIZE]; 401 volatile uint32_t spi_rainsr; 402 volatile uint32_t spi_insr; 403 volatile uint32_t spi_inmar; 404 volatile uint32_t spi_slenr; 405 volatile uint32_t spi_twlr; 406 volatile uint32_t spi_tlr; 407 volatile uint32_t spi_tfoficr; 408 volatile uint32_t spi_rwlr; 409 volatile uint32_t spi_rlr; 410 volatile uint32_t spi_rfficr; 411 volatile uint32_t spi_wsr; 412 volatile uint32_t spi_msticr; 413 volatile uint32_t spi_id; 414 volatile uint32_t spi_rsvd; 415 volatile uint32_t spi_rxoicr; 416 volatile uint32_t spi_icr; 417 } spi_v151_regs_t; 418 419 /** 420 * @} 421 */ 422 423 #ifdef __cplusplus 424 #if __cplusplus 425 } 426 #endif /* __cplusplus */ 427 #endif /* __cplusplus */ 428 429 #endif