1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19 #include "sys_drv.h"
20 #include "hi_osal.h"
21 #include "mkp_sys.h"
22 #include "sysconfig/sys_config.h"
23 #include "sys_hal.h"
24
25 #define PHASE 32
26 #define COEFF_BUTT (PHASE / 2 + 1)
27 #define SYS_MULTI_V 1048576
28 #define SYS_MULTI_H 1048576
29
30 static hi_vi_vpss_mode g_vi_vpss_mode;
31
32 #ifndef arry_size
33 #define arry_size(x) (sizeof(x) / sizeof((x)[0]))
34 #endif
35
sys_drv_set_priority(hi_vi_vpss_mode * vi_vpss_mode)36 hi_void sys_drv_set_priority(hi_vi_vpss_mode *vi_vpss_mode)
37 {
38 #if (defined(CONFIG_AMP) && defined(CONFIG_HUAWEI_LITEOS_OS)) || defined(CONFIG_SMP)
39 hi_u32 i;
40 hi_u32 flag;
41
42 for (i = 0; i < VIPROC_IP_NUM; i++) {
43 if (vi_vpss_mode->mode[i] == VI_ONLINE_VPSS_ONLINE) {
44 flag = 3; /* 3:VI_ONLINE_VPSS_ONLINE */
45 } else if (vi_vpss_mode->mode[i] == VI_ONLINE_VPSS_OFFLINE) {
46 flag = 2; /* 2:VI_ONLINE_VPSS_OFFLINE */
47 } else if (vi_vpss_mode->mode[i] == VI_OFFLINE_VPSS_ONLINE) {
48 flag = 1; /* 1:VI_OFFLINE_VPSS_ONLINE */
49 } else {
50 flag = 0;
51 }
52 set_vi_vpss_mode(flag);
53 }
54 #endif
55 return;
56 }
57
sysconfig_drv_set_vi_vpss_mode(const hi_s32 vi_vpss_mode)58 hi_void sysconfig_drv_set_vi_vpss_mode(const hi_s32 vi_vpss_mode)
59 {
60 set_vi_vpss_mode(vi_vpss_mode);
61 }
62
sys_drv_vi_vpss_mode_init(hi_void)63 hi_void sys_drv_vi_vpss_mode_init(hi_void)
64 {
65 hi_s32 i;
66
67 for (i = 0; i < VI_MAX_PIPE_NUM; i++) {
68 g_vi_vpss_mode.mode[i] = VI_OFFLINE_VPSS_OFFLINE;
69 }
70
71 sys_drv_set_priority(&g_vi_vpss_mode);
72
73 return;
74 }
75
sys_drv_init(hi_void)76 hi_s32 sys_drv_init(hi_void)
77 {
78 hi_s32 ret;
79
80 ret = sys_hal_init();
81 if (ret != HI_SUCCESS) {
82 return ret;
83 }
84
85 sys_drv_vi_vpss_mode_init();
86
87 return ret;
88 }
89
sys_drv_exit(hi_void)90 hi_s32 sys_drv_exit(hi_void)
91 {
92 sys_hal_exit();
93 return HI_SUCCESS;
94 }
95
sys_drv_drv_ioctrl(hi_mpp_chn * mpp_chn,sys_func func_id,hi_void * io_args)96 hi_s32 sys_drv_drv_ioctrl(hi_mpp_chn *mpp_chn, sys_func func_id, hi_void *io_args)
97 {
98 hi_s32 dev;
99
100 if ((mpp_chn == HI_NULL) || (io_args == HI_NULL)) {
101 sys_emerg_trace("null point!\n");
102 return HI_ERR_SYS_NULL_PTR;
103 }
104
105 dev = mpp_chn->dev_id;
106
107 switch (func_id) {
108 case SYS_VOU_BUS_RESET_SEL: {
109 hi_bool *reset = HI_NULL;
110 reset = (hi_bool *)io_args;
111 sys_hal_vou_bus_reset_sel(*reset);
112 break;
113 }
114 case SYS_VOU_APB_CLK_EN: {
115 hi_bool *clk_en = HI_NULL;
116 clk_en = (hi_bool *)io_args;
117 sys_hal_vou_apb_clk_en(dev, *clk_en);
118 break;
119 }
120 case SYS_VOU_BUS_CLK_EN: {
121 hi_bool *clk_en = HI_NULL;
122 clk_en = (hi_bool *)io_args;
123 sys_hal_vou_bus_clk_en(*clk_en);
124 break;
125 }
126 case SYS_VOU_CFG_CLK_EN: {
127 hi_bool *clk_en = HI_NULL;
128 clk_en = (hi_bool *)io_args;
129 sys_hal_vou_cfg_clk_en(dev, *clk_en);
130 break;
131 }
132 case SYS_VOU_CORE_CLK_EN: {
133 hi_bool *clk_en = HI_NULL;
134 clk_en = (hi_bool *)io_args;
135 sys_hal_vou_core_clk_en(dev, *clk_en);
136 break;
137 }
138 case SYS_VOU_DEV_CLK_EN: {
139 hi_bool *clk_en = HI_NULL;
140 clk_en = (hi_bool *)io_args;
141 sys_hal_vou_dev_clk_en(dev, *clk_en);
142 break;
143 }
144 case SYS_VOU_OUT_CLK_EN: {
145 hi_bool *clk_en = HI_NULL;
146 clk_en = (hi_bool *)io_args;
147 sys_hal_vou_out_clk_en(dev, *clk_en);
148 break;
149 }
150 case SYS_VO_BT1120_CLK_EN: {
151 hi_bool *bt1120_clk_en = HI_NULL;
152 bt1120_clk_en = (hi_bool *)io_args;
153 sys_hal_vou_bt_clk_en(dev, *bt1120_clk_en);
154 break;
155 }
156 case SYS_VO_HDMI_CLK_EN: {
157 hi_bool *hdmi_clk_en = HI_NULL;
158 hdmi_clk_en = (hi_bool *)io_args;
159 sys_hal_vou_hdmi_clk_en(dev, *hdmi_clk_en);
160 break;
161 }
162 case SYS_VO_MIPI_CLK_EN: {
163 hi_bool *mipi_clk_en = HI_NULL;
164 mipi_clk_en = (hi_bool *)io_args;
165 sys_hal_vou_mipi_clk_en(dev, *mipi_clk_en);
166 break;
167 }
168 case SYS_VOU_HD0_DIV_MOD: {
169 hi_u32 *clk_sel = HI_NULL;
170 clk_sel = (hi_u32 *)io_args;
171 sys_hal_vou_hd0_div_mode(dev, *clk_sel);
172 break;
173 }
174 case SYS_VOU_HD_CLK_SEL: {
175 hi_u32 *clk_sel = HI_NULL;
176 clk_sel = (hi_u32 *)io_args;
177 sys_hal_vou_hd_clk_sel(dev, *clk_sel);
178 break;
179 }
180 case SYS_VO_HDMI_TX_CLK_EN: {
181 hi_bool *hdmi_tx_clk_en = HI_NULL;
182 hdmi_tx_clk_en = (hi_bool *)io_args;
183 sys_hal_vou_hdmi_tx_clk_en(dev, *hdmi_tx_clk_en);
184 break;
185 }
186 case SYS_VO_MIPI_TX_CLK_EN: {
187 hi_bool *mipi_tx_clk_en = HI_NULL;
188 mipi_tx_clk_en = (hi_bool *)io_args;
189 sys_hal_vou_mipi_tx_clk_en(dev, *mipi_tx_clk_en);
190 break;
191 }
192 case SYS_VO_HDMI_CLK_SEL: {
193 hi_u32 *hdmi_clkdiv = HI_NULL;
194 hdmi_clkdiv = (hi_u32 *)io_args;
195 sys_hal_vou_hd_hdmi_clk_div(dev, *hdmi_clkdiv);
196 break;
197 }
198 case SYS_VOU_DAC_CLK_PHASIC_REVERSE_EN: {
199 break;
200 }
201 case SYS_VOU_HD_CLKOUT_PHASIC_REVERSE_EN: {
202 hi_bool *clk_reverse_en = HI_NULL;
203 clk_reverse_en = (hi_bool *)io_args;
204 sys_hal_vou_hd_out_pctrl(dev, *clk_reverse_en);
205 break;
206 }
207 case SYS_VOU_OUT_CLK_SEL: {
208 hi_u32 *clk_sel = HI_NULL;
209 clk_sel = (hi_u32 *)io_args;
210 sys_hal_vou_out_clk_sel(dev, *clk_sel);
211 break;
212 }
213
214 case SYS_VO_CLK_SEL: {
215 hi_u32 *clk_sel = HI_NULL;
216 clk_sel = (hi_u32 *)io_args;
217 sys_hal_vou_out_clk_sel(dev, *clk_sel);
218 break;
219 }
220 case SYS_VOU_LCD_CLK_EN: {
221 hi_bool *lcd_clk_en = HI_NULL;
222 lcd_clk_en = (hi_bool *)io_args;
223 sys_hal_vou_lcd_clk_en(dev, *lcd_clk_en);
224 break;
225 }
226 case SYS_LCD_MCLK_DIV: {
227 hi_u32 *lcd_mclk_div = HI_NULL;
228 lcd_mclk_div = (hi_u32 *)io_args;
229 sys_hal_lcd_mclk_div(*lcd_mclk_div);
230 break;
231 }
232 case SYS_LCD_DATA_MODE: {
233 hi_u32 *data_mode = HI_NULL;
234 data_mode = (hi_u32 *)io_args;
235 sys_hal_lcd_data_mode(*data_mode);
236 break;
237 }
238
239 case SYS_VO_PLL_FRAC_SET: {
240 hi_s32 pll;
241 hi_u32 bits_set;
242 pll = mpp_chn->dev_id;
243 bits_set = *(hi_u32 *)io_args;
244 sys_hal_set_vo_pll_frac(pll, bits_set);
245 break;
246 }
247 case SYS_VO_PLL_POSTDIV1_SET: {
248 hi_s32 pll;
249 hi_u32 bits_set;
250 pll = mpp_chn->dev_id;
251 bits_set = *(hi_u32 *)io_args;
252 sys_hal_set_vo_pll_postdiv1(pll, bits_set);
253 break;
254 }
255 case SYS_VO_PLL_POSTDIV2_SET: {
256 hi_s32 pll;
257 hi_u32 bits_set;
258 pll = mpp_chn->dev_id;
259 bits_set = *(hi_u32 *)io_args;
260 sys_hal_set_vo_pll_postdiv2(pll, bits_set);
261 break;
262 }
263 case SYS_VO_PLL_REFDIV_SET: {
264 hi_s32 pll;
265 hi_u32 bits_set;
266 pll = mpp_chn->dev_id;
267 bits_set = *(hi_u32 *)io_args;
268 sys_hal_set_vo_pll_refdiv(pll, bits_set);
269 break;
270 }
271 case SYS_VO_PLL_FBDIV_SET: {
272 hi_s32 pll;
273 hi_u32 bits_set;
274 pll = mpp_chn->dev_id;
275 bits_set = *(hi_u32 *)io_args;
276 sys_hal_set_vo_pll_fbdiv(pll, bits_set);
277 break;
278 }
279 case SYS_AIO_RESET_SEL: {
280 hi_bool *reset = HI_NULL;
281 reset = (hi_bool *)io_args;
282 sys_hal_aio_reset_sel(*reset);
283 break;
284 }
285 case SYS_AIO_CLK_EN: {
286 hi_bool *clk_en = HI_NULL;
287 clk_en = (hi_bool *)io_args;
288 sys_hal_aio_clk_en(*clk_en);
289 break;
290 }
291 default:
292 {
293 return HI_FAILURE;
294 }
295 }
296 return HI_SUCCESS;
297 }
298
299