1 /**
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 *
15 * Description: Provides timer port \n
16 *
17 * History: \n
18 * 2022-06-06， Create file. \n
19 */
20 #include "interrupt/osal_interrupt.h"
21 #include "chip_core_irq.h"
22 #include "common_def.h"
23 #include "hal_timer_v150.h"
24 #include "timer.h"
25 #include "platform_core.h"
26 #include "timer_porting.h"
27
28 static uintptr_t const g_timer_base_addr[TIMER_MAX_NUM] = {
29 TIMER_0_BASE_ADDR,
30 TIMER_1_BASE_ADDR,
31 TIMER_2_BASE_ADDR,
32 };
33
timer_porting_comm_addr_get(void)34 uintptr_t timer_porting_comm_addr_get(void)
35 {
36 return TIMER_BASE_ADDR;
37 }
38
timer_porting_base_addr_get(timer_index_t index)39 uintptr_t timer_porting_base_addr_get(timer_index_t index)
40 {
41 return g_timer_base_addr[index];
42 }
43
timer0_irq_handler(int i,void * p)44 STATIC int timer0_irq_handler(int i, void *p)
45 {
46 unused(i);
47 unused(p);
48 hal_timer_v150_interrupt_clear(TIMER_INDEX_0);
49 osal_irq_clear(TIMER_0_IRQN);
50 hal_timer_v150_irq_handler(TIMER_INDEX_0);
51 return 0;
52 }
53
timer1_irq_handler(int i,void * p)54 STATIC int timer1_irq_handler(int i, void *p)
55 {
56 unused(i);
57 unused(p);
58 hal_timer_v150_interrupt_clear(TIMER_INDEX_1);
59 osal_irq_clear(TIMER_1_IRQN);
60 hal_timer_v150_irq_handler(TIMER_INDEX_1);
61 return 0;
62 }
63
timer2_irq_handler(int i,void * p)64 STATIC int timer2_irq_handler(int i, void *p)
65 {
66 unused(i);
67 unused(p);
68 hal_timer_v150_interrupt_clear(TIMER_INDEX_2);
69 osal_irq_clear(TIMER_2_IRQN);
70 hal_timer_v150_irq_handler(TIMER_INDEX_2);
71 return 0;
72 }
73
74 static osal_irq_handler const timer_irq_handler[TIMER_MAX_NUM] = {
75 timer0_irq_handler,
76 timer1_irq_handler,
77 timer2_irq_handler,
78 };
79
timer_port_register_irq(timer_index_t index,uint32_t id,uint16_t priority)80 void timer_port_register_irq(timer_index_t index, uint32_t id, uint16_t priority)
81 {
82 osal_irq_disable(id);
83 osal_irq_request(id, (osal_irq_handler)timer_irq_handler[index], NULL, NULL, NULL);
84 osal_irq_set_priority(id, priority);
85 osal_irq_enable(id);
86 }
87
timer_port_unregister_irq(timer_index_t index,uint32_t id)88 void timer_port_unregister_irq(timer_index_t index, uint32_t id)
89 {
90 unused(index);
91 osal_irq_disable(id);
92 osal_irq_free(id, NULL);
93 }
94
95 static uint32_t g_timer_clock_value = CONFIG_TIMER_CLOCK_VALUE;
timer_porting_clock_value_set(uint32_t clock)96 void timer_porting_clock_value_set(uint32_t clock)
97 {
98 g_timer_clock_value = clock;
99 }
100
timer_porting_clock_value_get(void)101 uint32_t timer_porting_clock_value_get(void)
102 {
103 return g_timer_clock_value;
104 }
105
timer_porting_us_2_cycle(uint32_t us)106 uint64_t timer_porting_us_2_cycle(uint32_t us)
107 {
108 uint32_t clock_value = timer_porting_clock_value_get();
109 return ((uint64_t)(us) * (uint64_t)(clock_value / (MS_PER_S * US_PER_MS)));
110 }
111
timer_porting_cycle_2_us(uint64_t cycle)112 uint32_t timer_porting_cycle_2_us(uint64_t cycle)
113 {
114 uint32_t clock_value = timer_porting_clock_value_get();
115 return (uint32_t)((cycle * (MS_PER_S * US_PER_MS)) / (clock_value));
116 }
117
timer_porting_compensat_by_tcxo(uint64_t diff)118 uint64_t timer_porting_compensat_by_tcxo(uint64_t diff)
119 {
120 if (diff < TIMER_COMPENSAT_1_CYCLE_BY_TCXO) {
121 return 0;
122 } else if (diff < TIMER_COMPENSAT_2_CYCLE_BY_TCXO) {
123 return TIMER_1_CYCLE;
124 } else if (diff < TIMER_COMPENSAT_3_CYCLE_BY_TCXO) {
125 return TIMER_2_CYCLE;
126 } else {
127 return diff / TIMER_COMPENSAT_1_CYCLE_BY_TCXO;
128 }
129 }