1 /**
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 *
15 * Description: Provides uart driver source \n
16 *
17 * History: \n
18 * 2022-07-27, Create file. \n
19 */
20 #include <stdbool.h>
21 #include "soc_osal.h"
22 #include "securec.h"
23 #include "gpio_porting.h"
24 #include "gpio.h"
25
26 #define GPIO_DIRECTION_MAX_PARAM 2
27
28 static bool g_gpio_inited = false;
29
uapi_gpio_init(void)30 void uapi_gpio_init(void)
31 {
32 if (unlikely(g_gpio_inited)) {
33 return;
34 }
35 hal_gpio_init();
36 g_gpio_inited = true;
37 }
38
uapi_gpio_deinit(void)39 void uapi_gpio_deinit(void)
40 {
41 if (unlikely(!g_gpio_inited)) {
42 return;
43 }
44 g_gpio_inited = false;
45 hal_gpio_deinit();
46 }
47
uapi_gpio_set_dir(pin_t pin,gpio_direction_t dir)48 errcode_t uapi_gpio_set_dir(pin_t pin, gpio_direction_t dir)
49 {
50 if (unlikely(!g_gpio_inited)) {
51 return ERRCODE_GPIO_NOT_INIT;
52 }
53
54 if (unlikely(dir >= GPIO_DIRECTION_MAX_PARAM)) {
55 return ERRCODE_GPIO_DIR_SET_FAIL;
56 }
57
58 errcode_t ret = ERRCODE_FAIL;
59
60 uint32_t irq_sts = osal_irq_lock();
61 ret = hal_gpio_setdir(pin, dir);
62 osal_irq_restore(irq_sts);
63
64 return ret;
65 }
66
uapi_gpio_get_dir(pin_t pin)67 gpio_direction_t uapi_gpio_get_dir(pin_t pin)
68 {
69 if (unlikely(!g_gpio_inited)) {
70 return GPIO_DIRECTION_INPUT;
71 }
72
73 gpio_direction_t dir = hal_gpio_getdir(pin);
74
75 return dir;
76 }
77
uapi_gpio_set_val(pin_t pin,gpio_level_t level)78 errcode_t uapi_gpio_set_val(pin_t pin, gpio_level_t level)
79 {
80 if (unlikely(!g_gpio_inited)) {
81 return ERRCODE_GPIO_NOT_INIT;
82 }
83
84 errcode_t ret = ERRCODE_FAIL;
85
86 uint32_t irq_sts = osal_irq_lock();
87 ret = hal_gpio_output(pin, level);
88 osal_irq_restore(irq_sts);
89
90 return ret;
91 }
92
uapi_gpio_get_output_val(pin_t pin)93 gpio_level_t uapi_gpio_get_output_val(pin_t pin)
94 {
95 if (unlikely(!g_gpio_inited)) {
96 return GPIO_LEVEL_LOW;
97 }
98
99 gpio_level_t level = hal_gpio_get_outval(pin);
100
101 return level;
102 }
103
uapi_gpio_toggle(pin_t pin)104 errcode_t uapi_gpio_toggle(pin_t pin)
105 {
106 if (unlikely(!g_gpio_inited)) {
107 return ERRCODE_GPIO_NOT_INIT;
108 }
109
110 errcode_t ret = ERRCODE_FAIL;
111
112 uint32_t irq_sts = osal_irq_lock();
113 ret = hal_gpio_ctrl(pin, GPIO_CTRL_TOGGLE);
114 osal_irq_restore(irq_sts);
115
116 return ret;
117 }
118
uapi_gpio_get_val(pin_t pin)119 gpio_level_t uapi_gpio_get_val(pin_t pin)
120 {
121 if (unlikely(!g_gpio_inited)) {
122 return GPIO_LEVEL_LOW;
123 }
124
125 gpio_level_t level = hal_gpio_get_inval(pin);
126
127 return level;
128 }
129
uapi_gpio_set_isr_mode(pin_t pin,uint32_t trigger)130 errcode_t uapi_gpio_set_isr_mode(pin_t pin, uint32_t trigger)
131 {
132 if (unlikely(!g_gpio_inited)) {
133 return ERRCODE_GPIO_NOT_INIT;
134 }
135
136 errcode_t ret = ERRCODE_FAIL;
137
138 uint32_t irq_sts = osal_irq_lock();
139 ret = hal_gpio_register(pin, trigger, NULL, false);
140 osal_irq_restore(irq_sts);
141
142 return ret;
143 }
144
uapi_gpio_register_isr_func(pin_t pin,uint32_t trigger,gpio_callback_t callback)145 errcode_t uapi_gpio_register_isr_func(pin_t pin, uint32_t trigger, gpio_callback_t callback)
146 {
147 if (unlikely(!g_gpio_inited)) {
148 return ERRCODE_GPIO_NOT_INIT;
149 }
150
151 errcode_t ret = ERRCODE_FAIL;
152
153 uint32_t irq_sts = osal_irq_lock();
154 ret = hal_gpio_register(pin, trigger, callback, true);
155 osal_irq_restore(irq_sts);
156
157 return ret;
158 }
159
uapi_gpio_unregister_isr_func(pin_t pin)160 errcode_t uapi_gpio_unregister_isr_func(pin_t pin)
161 {
162 if (unlikely(!g_gpio_inited)) {
163 return ERRCODE_GPIO_NOT_INIT;
164 }
165
166 errcode_t ret = ERRCODE_FAIL;
167
168 uint32_t irq_sts = osal_irq_lock();
169 ret = hal_gpio_unregister(pin);
170 osal_irq_restore(irq_sts);
171
172 return ret;
173 }
174
uapi_gpio_enable_interrupt(pin_t pin)175 errcode_t uapi_gpio_enable_interrupt(pin_t pin)
176 {
177 if (unlikely(!g_gpio_inited)) {
178 return ERRCODE_GPIO_NOT_INIT;
179 }
180
181 errcode_t ret = ERRCODE_FAIL;
182
183 uint32_t irq_sts = osal_irq_lock();
184 ret = hal_gpio_ctrl(pin, GPIO_CTRL_ENABLE_INTERRUPT);
185 osal_irq_restore(irq_sts);
186
187 return ret;
188 }
189
uapi_gpio_disable_interrupt(pin_t pin)190 errcode_t uapi_gpio_disable_interrupt(pin_t pin)
191 {
192 if (unlikely(!g_gpio_inited)) {
193 return ERRCODE_GPIO_NOT_INIT;
194 }
195
196 errcode_t ret = ERRCODE_FAIL;
197
198 uint32_t irq_sts = osal_irq_lock();
199 ret = hal_gpio_ctrl(pin, GPIO_CTRL_DISABLE_INTERRUPT);
200 osal_irq_restore(irq_sts);
201
202 return ret;
203 }
204
uapi_gpio_clear_interrupt(pin_t pin)205 errcode_t uapi_gpio_clear_interrupt(pin_t pin)
206 {
207 if (unlikely(!g_gpio_inited)) {
208 return ERRCODE_GPIO_NOT_INIT;
209 }
210
211 errcode_t ret = ERRCODE_FAIL;
212
213 uint32_t irq_sts = osal_irq_lock();
214 ret = hal_gpio_ctrl(pin, GPIO_CTRL_CLEAR_INTERRUPT);
215 osal_irq_restore(irq_sts);
216
217 return ret;
218 }
219
220 #if defined(CONFIG_GPIO_SUPPORT_LPM)
uapi_gpio_suspend(uintptr_t arg)221 errcode_t uapi_gpio_suspend(uintptr_t arg)
222 {
223 unused(arg);
224 return hal_gpio_ctrl(0, GPIO_CTRL_SUSPEND);
225 }
226
uapi_gpio_resume(uintptr_t arg)227 errcode_t uapi_gpio_resume(uintptr_t arg)
228 {
229 unused(arg);
230 return hal_gpio_ctrl(0, GPIO_CTRL_RESUME);
231 }
232 #endif
233
234 #if defined(CONFIG_GPIO_SELECT_CORE)
uapi_gpio_select_core(pin_t pin,cores_t core)235 void uapi_gpio_select_core(pin_t pin, cores_t core)
236 {
237 gpio_select_core(pin_t pin, cores_t core);
238 }
239 #endif