1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18 #include "vou_drv.h"
19 #include "vou_dev_exp.h"
20 #include "hi_math_adapt.h"
21 #include "vou.h"
22
23 #ifdef __cplusplus
24 #if __cplusplus
25 extern "C" {
26 #endif
27 #endif /* end of #ifdef __cplusplus */
28
29 #define VO_DEV_MAX_NUM 1
30 #define VO_LAYER_MAX_NUM 1
31
32 #define VO_SD_VTTH_WATERLINE 100
33 #define VO_HD_VTTH_WATERLINE 240
34 #define VO_SD_VTTH_WATERLINE2 2
35 #define VO_HD_VTTH_WATERLINE2 2
36
37 #define VO_BACKGROUD_BLACK 0x8080
38 #define VO_BACKGROUD_GREEN 0x804D3A42
39 #define VO_BACKGROUD_BLUE 0x800404ee
40 #define VO_BACKGROUD_RED 0x00c8c8c8
41 #define VO_BACKGROUD_DEFAULT VO_BACKGROUD_GREEN
42
43 #define VO_RESO_MIN_WDT 32 /* minimal width of display resolution */
44 #define VO_RESO_MIN_HGT 32 /* minimal height of display resolution */
45 #define VO_DISP_MAX_FRMRATE 240 /* max display frame rate */
46
47 /* default number of video layer buffer */
48 #define VO_HD_USE_BLK 4
49 #define VO_SD_USE_BLK 3
50
51 #define MULTI_REGION_NUM_VHD0 1
52 #define MULTI_REGION_NUM_VHD1 0
53
54 #define VO_MIN_DIV_MODE 1
55 #define VO_MAX_DIV_MODE 4
56 #define VO_MIN_HDMI_DIV 1
57 #define VO_MAX_HDMI_DIV 32
58
59 #define VO_LIMIT_USER_DISPWH_59V200 3840
60
61 #define VO_LIMIT_USER_DISPWH_OTHERS 1920
62 #define VO_SYNC_VACT_MIN 100
63
64 /* PLL FREF 24MHz */
65 #define VO_PLL_FREF 24
66
67 /* PLL frac precision */
68 #define VO_PLL_FRAC_PREC (1 << 24)
69 #define VO_PLL_FOUTCVO_MIN 800
70 #define VO_PLL_FOUTCVO_MAX 3200
71 #define VO_PLL_FBDIV_MAX 0xfff
72 #define VO_PLL_FRAC_MAX 0xffffff
73 #define VO_PLL_REFDIV_MAX 0x3f
74 #define VO_PLL_POSTDIV1_MAX 0x7
75 #define VO_PLL_POSTDIV2_MAX 0x7
76
77 /* LCDMCLKDIV max ((75 / 1188) * 2^27 )(max 75Mhz) */
78 #define VO_LCDMCLK_DIV_MAX 8473341
79
80 #define VO_DRV_DCMP_DATA_NUM 2
81 #define VO_DRV_DCMP_IP_NUM 2
82
83 #define VO_DRV_DCMP_EVEN_IP_OFFSET 0
84 #define VO_DRV_DCMP_ODD_IP_OFFSET 1
85 #define VO_DRV_DCMP_CHM_OFFSET_EVEN 2
86 #define VO_DRV_DCMP_CHM_OFFSET_ODD 3
87
88 #ifdef CONFIG_HI_VO_COVER_OSD_SUPPORT
89 #define VO_RGN_OVERLAY_LAYER_MIN 0
90 #define VO_RGN_OVERLAY_LAYER_MAX 0
91 #define VO_RGN_OVERLAY_PIXEL_FMT_NUM 3
92 #define VO_RGN_OVERLAY_FG_ALPHA_MAX 255
93 #define VO_RGN_OVERLAY_FG_ALPHA_MIN 0
94 #define VO_RGN_OVERLAY_BG_ALPHA_MAX 255
95 #define VO_RGN_OVERLAY_BG_ALPHA_MIN 0
96 #define VO_RGN_OVERLAY_GLOBAL_ALPHA_MAX 255
97 #define VO_RGN_OVERLAY_GLOBAL_ALPHA_MIN 0
98
99 #define VO_RGN_OVERLAY_QP_ABS_MAX 51
100 #define VO_RGN_OVERLAY_QP_ABS_MIN 0
101 #define VO_RGN_OVERLAY_QP_REL_MAX 51
102 #define VO_RGN_OVERLAY_QP_REL_MIN (-51)
103 #define VO_RGN_OVERLAY_STRIDE 64
104
105 #define VO_RGN_COVER_LAYER_MIN 0
106 #define VO_RGN_COVER_LAYER_MAX 0
107 #define VO_RGN_COVER_PIXEL_FMT_NUM 3
108 #define VO_RGN_COVER_FG_ALPHA_MAX 255
109 #define VO_RGN_COVER_FG_ALPHA_MIN 0
110 #define VO_RGN_COVER_BG_ALPHA_MAX 255
111 #define VO_RGN_COVER_BG_ALPHA_MIN 0
112 #define VO_RGN_COVER_GLOBAL_ALPHA_MAX 255
113 #define VO_RGN_COVER_GLOBAL_ALPHA_MIN 0
114
115 #define VO_RGN_COVER_QP_ABS_MAX 51
116 #define VO_RGN_COVER_QP_ABS_MIN 0
117 #define VO_RGN_COVER_QP_REL_MAX 51
118 #define VO_RGN_COVER_QP_REL_MIN (-51)
119 #define VO_RGN_COVER_STRIDE 64
120 #endif
121
122 #define VO_ASPECT_RATIO_RECT_XY_MIN 0
123
124 #define VO_ASPECT_RATIO_RECT_XYWH_ALIGN 2
125 #define VO_ASPECT_RATIO_BG_COLOR_MAX 0xffffff
126
127 #define VO_BORDER_WIDTH_MIN 2
128 #define VO_BORDER_WIDTH_MAX 8
129 #define VO_BORDER_WIDTH_ALIGN 2
130 #define VO_BORDER_COLOR_MASK 0xff000000
131
132 #define VO_LAYER_CSC_SCALE2P_DEF_VAL 0xa
133 #define VO_LAYER_CSC_CLIP_MIN 0x0
134 #define VO_LAYER_CSC_CLIP_MAX 0xfff
135
136 #define VO_MPP_CHN_DEV_DEF_VAL 0
137 #define VO_MPP_CHN_CHN_DEF_VAL 0
138
139 /* vou interrupt mask type */
140 typedef enum {
141 VO_INTMSK_NONE = 0,
142 VO_INTMSK_DHD0_VTTHD1 = 0x1,
143 VO_INTMSK_DHD0_VTTHD2 = 0x2,
144 VO_INTMSK_DHD0_VTTHD3 = 0x4,
145 VO_INTMSK_DHD0_UFINT = 0x8,
146
147 VO_INTMSK_DHD1_VTTHD1 = 0x10,
148 VO_INTMSK_DHD1_VTTHD2 = 0x20,
149 VO_INTMSK_DHD1_VTTHD3 = 0x40,
150 VO_INTMSK_DHD1_UFINT = 0x80,
151
152 VO_INTMSK_DSD_VTTHD1 = 0x100,
153 VO_INTMSK_DSD_VTTHD2 = 0x200,
154 VO_INTMSK_DSD_VTTHD3 = 0x400,
155 VO_INTMSK_DSD_UFINT = 0x800,
156
157 VO_INTMSK_B0_ERR = 0x1000,
158 VO_INTMSK_B1_ERR = 0x2000,
159 VO_INTMSK_B2_ERR = 0x4000,
160
161 VO_INTMSK_WBC_DHDOVER = 0x8000,
162
163 VO_INTREPORT_ALL = 0xffffffff
164 } vo_int_mask;
165
166 typedef struct {
167 hi_bool int_ocurred;
168 hi_bool detect_enabled;
169 } vo_drv_load_detect_info;
170
171 typedef struct {
172 vo_dev_capability dev_cap;
173 hi_bool vo_enable;
174 hi_bool config;
175 hi_vo_pub_attr vou_attr;
176
177 hi_u32 layer_num;
178
179 hi_u32 gfx_num;
180 hi_graphic_layer gfx_layer[VO_MAX_GRAPHICS_LAYER_NUM];
181
182 hi_u32 max_width;
183 hi_u32 max_height;
184
185 hi_bool dac_power_up;
186 vo_drv_load_detect_info load_detect_info;
187 hi_u32 low_bandwidth_cnt;
188 hi_u64 bus_err;
189 vo_dither_info dither_info;
190 } vo_drv_dev;
191
192 typedef struct {
193 hi_bool video_enable;
194 hi_bool video_config;
195
196 hi_s32 bind_dev;
197
198 hi_bool enlarge;
199
200 hi_s32 priority;
201
202 hi_u32 layer_size;
203 hi_bool layer_limit;
204
205 hi_u32 chn_num;
206 hi_vo_video_layer_attr vo_video_attr;
207
208 hi_rect zme_in_rect;
209 hi_rect zme_out_rect;
210 hi_vo_csc csc;
211 hi_bool vhdr;
212 hi_vo_csc vhdr_csc;
213 csc_coef_param csc_param;
214 hi_dynamic_range last_dynamic_range;
215 hi_crop_info crop_info;
216 } vo_drv_layer;
217
218 typedef struct {
219 hi_u32 vtth;
220 hi_u32 vtth2;
221 hi_u32 bk_grd;
222 hi_vo_intf_type intf_type;
223 hi_vo_intf_sync out_sync;
224 hal_disp_pixel_format pixel_fmt;
225 } hal_dev_config;
226
227 typedef struct {
228 hi_u32 bk_grd;
229 vo_layer_ddr ddr_id;
230 } hal_layer_config;
231
232 vo_drv_dev g_vo_drv_dev[VO_MAX_DEV_NUM];
233 vo_drv_layer g_vo_drv_layer[VO_MAX_LAYER_NUM];
234
235 #define vo_drv_get_dev_ctx(dev) (&g_vo_drv_dev[(dev)])
236 #define vo_drv_get_layer_ctx(layer) (&g_vo_drv_layer[(layer)])
237
238 static hal_layer_config g_hal_layer_cfg[VO_LAYER_MAX_NUM] = {
239 {
240 .bk_grd = VO_BACKGROUD_DEFAULT,
241 .ddr_id = VO_LAYER_DDR0, /* vhd0 */
242 }
243 };
244
245 hal_disp_syncinfo g_sync_timing[VO_OUTPUT_BUTT] = {
246 /*
247 * |--INTFACE---||-----TOP-----||----HORIZON------||--BOTTOM---||-PULSE-||-INVERSE-|
248 * synm, iop, itf, vact, vbb, vfb, hact, hbb, hfb, hmid,bvact,bvbb, bvfb, hpw, vpw,idv, ihs, ivs
249 */
250 { 0, 0, 0, 288, 22, 2, 720, 132, 12, 1, 288, 23, 2, 126, 3, 0, 0, 0 }, /* 576I(PAL) */
251 { 0, 0, 0, 240, 18, 4, 720, 119, 19, 1, 240, 19, 4, 124, 3, 0, 0, 0 }, /* 480I(NTSC) */
252
253 { 0, 1, 1, 1080, 41, 4, 1920, 192, 638, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@24_hz */
254 { 0, 1, 1, 1080, 41, 4, 1920, 192, 528, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@25_hz */
255 { 0, 1, 1, 1080, 41, 4, 1920, 192, 88, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@30_hz */
256
257 { 0, 1, 1, 720, 25, 5, 1280, 260, 440, 1, 1, 1, 1, 40, 5, 0, 0, 0 }, /* 720P@50_hz */
258 { 0, 1, 1, 720, 25, 5, 1280, 260, 110, 1, 1, 1, 1, 40, 5, 0, 0, 0 }, /* 720P@60_hz */
259 { 0, 0, 1, 540, 20, 2, 1920, 192, 528, 1128, 540, 21, 2, 44, 5, 0, 0, 0 }, /* 1080I@50_hz */
260 { 0, 0, 1, 540, 20, 2, 1920, 192, 88, 908, 540, 21, 2, 44, 5, 0, 0, 0 }, /* 1080I@60_hz */
261 { 0, 1, 1, 1080, 41, 4, 1920, 192, 528, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@50_hz */
262 { 0, 1, 1, 1080, 41, 4, 1920, 192, 88, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@60_hz */
263
264 { 1, 1, 1, 576, 44, 5, 720, 132, 12, 1, 1, 1, 1, 64, 5, 0, 0, 0 }, /* 576P@50_hz */
265 { 1, 1, 1, 480, 36, 9, 720, 122, 16, 1, 1, 1, 1, 62, 6, 0, 0, 0 }, /* 480P@60_hz */
266
267 { 1, 1, 2, 600, 27, 1, 800, 216, 40, 1, 1, 1, 1, 128, 4, 0, 0, 0 }, /* 800*600@60_hz VGA@60_hz */
268 { 1, 1, 2, 768, 35, 3, 1024, 296, 24, 1, 1, 1, 1, 136, 6, 0, 1, 1 }, /* 1024x768@60_hz */
269 { 1, 1, 2, 1024, 41, 1, 1280, 360, 48, 1, 1, 1, 1, 112, 3, 0, 0, 0 }, /* 1280x1024@60_hz */
270 { 1, 1, 2, 768, 27, 3, 1366, 356, 70, 1, 1, 1, 1, 143, 3, 0, 0, 0 }, /* 1366x768@60_hz */
271 { 1, 1, 2, 900, 31, 3, 1440, 384, 80, 1, 1, 1, 1, 152, 6, 0, 1, 0 }, /* 1440x900@60_hz */
272 { 1, 1, 2, 800, 28, 3, 1280, 328, 72, 1, 1, 1, 1, 128, 6, 0, 1, 0 }, /* 1280*800@60_hz VGA@60_hz */
273 { 1, 1, 2, 1200, 49, 1, 1600, 496, 64, 1, 1, 1, 1, 192, 3, 0, 0, 0 }, /* 1600*1200@60_hz */
274 { 1, 1, 2, 1050, 36, 3, 1680, 456, 104, 1, 1, 1, 1, 176, 6, 0, 1, 0 }, /* 1680*1050@60_hz */
275 { 1, 1, 2, 1200, 32, 3, 1920, 112, 48, 1, 1, 1, 1, 32, 6, 0, 0, 1 }, /* 1920*1200@60_hz CVT (reduced blanking) */
276 { 1, 1, 2, 480, 35, 10, 640, 144, 16, 1, 1, 1, 1, 96, 2, 0, 1, 1 }, /* 640*480@60_hz CVT */
277
278 { 0, 0, 0, 288, 22, 2, 960, 176, 16, 1, 288, 23, 2, 168, 3, 0, 0, 0 }, /* 960H(PAL) */
279 { 0, 0, 0, 240, 18, 4, 960, 163, 21, 1, 240, 19, 4, 168, 3, 0, 0, 0 }, /* 960H(NTSC) */
280
281 { 0, 1, 1, 2160, 72, 8, 1920, 192, 88, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1920*2160@30_hz */
282 { 1, 1, 2, 1440, 39, 2, 2560, 112, 48, 1, 1, 1, 1, 32, 5, 0, 0, 0 }, /* 2560*1440@30_hz */
283 { 1, 1, 2, 1440, 39, 2, 2560, 112, 48, 1, 1, 1, 1, 32, 5, 0, 0, 0 }, /* 2560*1440@60_hz */
284 { 0, 1, 2, 1600, 43, 3, 2560, 112, 48, 1, 1, 1, 1, 32, 6, 0, 0, 1 }, /* 2560*1600@60_hz CVT (reduced blanking) */
285 { 0, 1, 1, 2160, 82, 8, 3840, 384, 1276, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@24_hz */
286 { 0, 1, 1, 2160, 82, 8, 3840, 384, 1056, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@25_hz */
287 { 0, 1, 1, 2160, 82, 8, 3840, 384, 176, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@30_hz */
288 { 0, 1, 1, 2160, 82, 8, 3840, 384, 1056, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@50_hz */
289 { 0, 1, 1, 2160, 82, 8, 3840, 384, 176, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@60_hz */
290
291 { 0, 1, 1, 2160, 82, 8, 4096, 384, 1020, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@24 */
292 { 0, 1, 1, 2160, 82, 8, 4096, 216, 968, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@25 */
293 { 0, 1, 1, 2160, 82, 8, 4096, 216, 88, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@30 */
294 { 0, 1, 1, 2160, 82, 8, 4096, 216, 968, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@50 */
295 { 0, 1, 1, 2160, 82, 8, 4096, 216, 88, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@60 */
296 { 0, 1, 1, 240, 15, 9, 320, 65, 7, 1, 240, 14, 9, 1, 1, 0, 0, 0 }, /* 320X240@60 8bit LCD */
297 { 0, 1, 1, 240, 2, 2, 320, 5, 10, 1, 1, 1, 1, 10, 1, 0, 0, 0 }, /* 320X240@50 6bit LCD */
298 { 0, 1, 1, 320, 10, 4, 240, 30, 10, 1, 1, 1, 1, 10, 2, 0, 0, 0 }, /* 240X320@50 6bit LCD */
299 { 0, 1, 1, 320, 2, 2, 240, 20, 10, 1, 1, 1, 1, 2, 1, 0, 0, 0 }, /* 240X320@60 16bit LCD */
300 { 0, 1, 1, 600, 23, 12, 800, 210, 46, 1, 1, 1, 1, 2, 1, 0, 0, 0 }, /* 800X600@50 24bit LCD */
301
302 { 0, 1, 1, 1280, 24, 8, 720, 123, 99, 1, 1, 1, 1, 24, 4, 0, 0, 0 }, /* for MIPI DSI tx 720 x1280 at 60 hz */
303 { 0, 1, 1, 1920, 36, 16, 1080, 28, 130, 1, 1, 1, 1, 8, 10, 0, 0, 0 }, /* for MIPI DSI tx 1080 x1920 at 60 hz */
304 { 0, 1, 1, 4320, 64, 16, 7680, 768, 552, 1, 1, 1, 1, 176, 20, 0, 0, 0 }, /* 7680x4320@30 */
305 {} /* user */
306 };
307
308 static hal_dev_config g_hal_dev_cfg[VO_DEV_MAX_NUM] = {
309 {
310 .vtth = VO_HD_VTTH_WATERLINE,
311 .vtth2 = VO_HD_VTTH_WATERLINE2,
312 .bk_grd = VO_BACKGROUD_DEFAULT,
313 .intf_type = VO_INTF_HDMI | VO_INTF_BT1120 | VO_INTF_BT656 | VO_INTF_MIPI | VO_INTF_MIPI_SLAVE | VO_INTF_LCD,
314 .out_sync = VO_OUTPUT_1080P30,
315 .pixel_fmt = HAL_INPUTFMT_YCBCR_SEMIPLANAR_422, /* VOU_PIXERL_FORMAT_RGB888, VOU_PIXERL_FORMAT_YCBCR422 */
316 }
317 };
318
319 vo_coef_addr g_vo_coef_buf_addr = {0};
320
vo_drv_get_coef_buf_addr(hi_void)321 vo_coef_addr *vo_drv_get_coef_buf_addr(hi_void)
322 {
323 return &g_vo_coef_buf_addr;
324 }
325
vou_drv_convert_layer(hi_vo_layer layer)326 static hal_disp_layer vou_drv_convert_layer(hi_vo_layer layer)
327 {
328 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
329
330 switch (layer) {
331 case VO_HAL_LAYER_VHD0:
332 disp_layer = HAL_DISP_LAYER_VHD0;
333 break;
334
335 default:
336 break;
337 }
338
339 return disp_layer;
340 }
341
vou_drv_convert_data_format(vou_layer_pixerl_format data_fmt)342 static hal_disp_pixel_format vou_drv_convert_data_format(vou_layer_pixerl_format data_fmt)
343 {
344 hal_disp_pixel_format pixel_format = HAL_DISP_PIXELFORMAT_BUTT;
345
346 switch (data_fmt) {
347 case VOU_LAYER_PIXERL_FORMAT_SP_YCBCR_400:
348 pixel_format = HAL_INPUTFMT_YCBCR_SEMIPLANAR_400;
349 break;
350 case VOU_LAYER_PIXERL_FORMAT_SP_YCBCR_420:
351 pixel_format = HAL_INPUTFMT_YCBCR_SEMIPLANAR_420;
352 break;
353 case VOU_LAYER_PIXERL_FORMAT_SP_YCBCR_422:
354 pixel_format = HAL_INPUTFMT_YCBCR_SEMIPLANAR_422;
355 break;
356 default:
357 break;
358 }
359
360 return pixel_format;
361 }
362
vou_drv_set_layer_cvfir_coef(hi_u32 layer,vo_rm_coef_mode coef_mode)363 static hi_void vou_drv_set_layer_cvfir_coef(hi_u32 layer, vo_rm_coef_mode coef_mode)
364 {
365 cvfir_coef coef = {0, 63, 0, 0, -6, 12, 51, 7};
366
367 hi_unused(coef_mode);
368 hal_video_cvfir_set_coef(layer, &coef);
369 }
370
vo_drv_v_set_v0_zme_coef(vo_rm_coef_mode coef_mode)371 hi_void vo_drv_v_set_v0_zme_coef(vo_rm_coef_mode coef_mode)
372 {
373 vou_drv_set_layer_cvfir_coef(HAL_DISP_LAYER_VHD0, coef_mode);
374 }
375
vou_drv_layer_csc_enable(hi_vo_layer layer,hi_bool csc_en)376 hi_void vou_drv_layer_csc_enable(hi_vo_layer layer, hi_bool csc_en)
377 {
378 hal_layer_set_csc_en(layer, csc_en);
379 return;
380 }
381
vou_drv_board_init(hi_void)382 hi_void vou_drv_board_init(hi_void)
383 {
384 hal_vou_init();
385 return;
386 }
387
vou_drv_board_de_init(hi_void)388 hi_void vou_drv_board_de_init(hi_void)
389 {
390 hal_vou_exit();
391 }
392
vo_drv_int_reg_up_mode(hi_vo_layer layer,vo_int_mode int_mode)393 hi_void vo_drv_int_reg_up_mode(hi_vo_layer layer, vo_int_mode int_mode)
394 {
395 hal_video_set_layer_up_mode(layer, int_mode);
396 return;
397 }
398
vou_drv_set_dev_intf_type(hi_vo_dev dev,hi_vo_intf_type intf_type)399 hi_void vou_drv_set_dev_intf_type(hi_vo_dev dev, hi_vo_intf_type intf_type)
400 {
401 g_hal_dev_cfg[dev].intf_type = intf_type;
402
403 return;
404 }
405
vou_drv_set_dev_bk_grd(hi_vo_dev dev,hi_u32 bg_color)406 hi_void vou_drv_set_dev_bk_grd(hi_vo_dev dev, hi_u32 bg_color)
407 {
408 g_hal_dev_cfg[dev].bk_grd = bg_color;
409
410 return;
411 }
412
vou_drv_set_dev_out_sync(hi_vo_dev dev,hi_vo_intf_sync intf_sync)413 hi_void vou_drv_set_dev_out_sync(hi_vo_dev dev, hi_vo_intf_sync intf_sync)
414 {
415 g_hal_dev_cfg[dev].out_sync = intf_sync;
416
417 return;
418 }
419
vou_drv_set_dev_default_vtth(hi_vo_dev dev)420 hi_void vou_drv_set_dev_default_vtth(hi_vo_dev dev)
421 {
422 if (vo_drv_is_phy_dev_hd(dev) == HI_TRUE) {
423 g_hal_dev_cfg[dev].vtth = VO_HD_VTTH_WATERLINE;
424 } else {
425 g_hal_dev_cfg[dev].vtth = VO_SD_VTTH_WATERLINE;
426 }
427
428 return;
429 }
430
vou_drv_set_dev_vtth(hi_vo_dev dev,hi_u32 vtth)431 hi_s32 vou_drv_set_dev_vtth(hi_vo_dev dev, hi_u32 vtth)
432 {
433 hi_u32 dft_vtth;
434
435 dft_vtth = (vo_drv_is_phy_dev_hd(dev)) ? VO_HD_VTTH_WATERLINE : VO_SD_VTTH_WATERLINE;
436 g_hal_dev_cfg[dev].vtth = MAX2(vtth, dft_vtth);
437
438 return HI_SUCCESS;
439 }
440
vou_drv_get_dev_vtth(hi_vo_dev dev,hi_u32 * vtth)441 hi_void vou_drv_get_dev_vtth(hi_vo_dev dev, hi_u32 *vtth)
442 {
443 *vtth = g_hal_dev_cfg[dev].vtth;
444 return;
445 }
446
vou_drv_is_support_save_buf_mode(hi_void)447 hi_bool vou_drv_is_support_save_buf_mode(hi_void)
448 {
449 return HI_TRUE;
450 }
451
vou_drv_set_dev_default_vtth2(hi_vo_dev dev)452 hi_void vou_drv_set_dev_default_vtth2(hi_vo_dev dev)
453 {
454 hi_vo_mod_param *vo_mod_param = vo_get_vo_mod_param();
455
456 if (dev == VO_DEV_DHD0) {
457 if (vo_mod_param->save_buf_mode[dev]) {
458 if (vo_drv_is_phy_dev_hd(dev) == HI_TRUE) {
459 g_hal_dev_cfg[dev].vtth2 = VO_HD_VTTH_WATERLINE2;
460 } else {
461 g_hal_dev_cfg[dev].vtth2 = VO_SD_VTTH_WATERLINE2;
462 }
463 }
464 }
465 return;
466 }
467
vou_drv_set_dev_vtth2(hi_vo_dev dev,hi_u32 vtth)468 hi_s32 vou_drv_set_dev_vtth2(hi_vo_dev dev, hi_u32 vtth)
469 {
470 hi_u32 dft_vtth2;
471 hi_u32 vtth1 = 0;
472 hi_u32 tmp;
473
474 dft_vtth2 = (vo_drv_is_phy_dev_hd(dev)) ? VO_HD_VTTH_WATERLINE2 : VO_SD_VTTH_WATERLINE2;
475 vou_drv_get_dev_vtth(dev, &vtth1);
476 tmp = MAX2(vtth, dft_vtth2);
477
478 g_hal_dev_cfg[dev].vtth2 = MIN2(tmp, vtth1);
479
480 return HI_SUCCESS;
481 }
482
vou_drv_get_dev_vtth2(hi_vo_dev dev,hi_u32 * vtth)483 hi_void vou_drv_get_dev_vtth2(hi_vo_dev dev, hi_u32 *vtth)
484 {
485 if (dev <= VO_DEV_DHD0) {
486 *vtth = g_hal_dev_cfg[dev].vtth2;
487 }
488
489 return;
490 }
491
vou_drv_get_dev_enable(hi_vo_dev dev)492 hi_bool vou_drv_get_dev_enable(hi_vo_dev dev)
493 {
494 hi_bool intf_en = HI_FALSE;
495
496 hal_disp_get_intf_enable(dev, &intf_en);
497 return intf_en;
498 }
499
vou_drv_check_usr_sync_timing(hi_vo_dev dev,hi_vo_sync_info * sync_info)500 hi_s32 vou_drv_check_usr_sync_timing(hi_vo_dev dev, hi_vo_sync_info *sync_info)
501 {
502 if (((sync_info->synm != HI_TRUE) && (sync_info->synm != HI_FALSE)) ||
503 ((sync_info->iop != HI_TRUE) && (sync_info->iop != HI_FALSE)) ||
504 ((sync_info->idv != HI_TRUE) && (sync_info->idv != HI_FALSE)) ||
505 ((sync_info->ihs != HI_TRUE) && (sync_info->ihs != HI_FALSE)) ||
506 ((sync_info->ivs != HI_TRUE) && (sync_info->ivs != HI_FALSE))) {
507 vo_err_trace("DHD%d: sync's synm(%d),iop(%d),idv(%d),ihs(%d),ivs(%d) should be %d or %d\n",
508 dev, sync_info->synm, sync_info->iop, sync_info->idv, sync_info->ihs, sync_info->ivs, HI_TRUE, HI_FALSE);
509 return HI_ERR_VO_ILLEGAL_PARAM;
510 }
511
512 if ((sync_info->hact == 0) || (sync_info->hbb == 0) || (sync_info->hfb == 0)) {
513 vo_err_trace("usr sync_time hact(%u) hbb(%u) hfb(%u) can't be 0!\n", sync_info->hact, sync_info->hbb,
514 sync_info->hfb);
515 return HI_ERR_VO_ILLEGAL_PARAM;
516 }
517
518 if ((sync_info->vact < VO_SYNC_VACT_MIN) || (sync_info->vbb == 0) || (sync_info->vfb == 0)) {
519 vo_err_trace("usr sync_time vact(%u) can't be smaller than %d and vbb(%u) vfb(%u) can't be 0!\n",
520 sync_info->vact, VO_SYNC_VACT_MIN, sync_info->vbb, sync_info->vfb);
521 return HI_ERR_VO_ILLEGAL_PARAM;
522 }
523
524 if ((sync_info->hpw == 0) || (sync_info->vpw == 0)) {
525 vo_err_trace("usr sync_time hpw(%u) vpw(%u) can't be 0!\n", sync_info->hpw, sync_info->vpw);
526 return HI_ERR_VO_ILLEGAL_PARAM;
527 }
528
529 if ((sync_info->iop == 0) && ((sync_info->bvact == 0) || (sync_info->bvbb == 0) || (sync_info->bvfb == 0))) {
530 vo_err_trace("usr sync_time vact(%u) vbb(%u) vfb(%u) can't be 0 when interlaced timing !\n",
531 sync_info->vact, sync_info->vbb, sync_info->vfb);
532 return HI_ERR_VO_ILLEGAL_PARAM;
533 }
534
535 return HI_SUCCESS;
536 }
537
vou_drv_set_usr_sync_timing(hi_vo_sync_info * sync_info)538 hi_void vou_drv_set_usr_sync_timing(hi_vo_sync_info *sync_info)
539 {
540 g_sync_timing[VO_OUTPUT_USER].synm = sync_info->synm;
541 g_sync_timing[VO_OUTPUT_USER].iop = sync_info->iop;
542 g_sync_timing[VO_OUTPUT_USER].intfb = sync_info->intfb;
543 g_sync_timing[VO_OUTPUT_USER].vact = sync_info->vact;
544 g_sync_timing[VO_OUTPUT_USER].vbb = sync_info->vbb;
545 g_sync_timing[VO_OUTPUT_USER].vfb = sync_info->vfb;
546 g_sync_timing[VO_OUTPUT_USER].hact = sync_info->hact;
547 g_sync_timing[VO_OUTPUT_USER].hbb = sync_info->hbb;
548 g_sync_timing[VO_OUTPUT_USER].hfb = sync_info->hfb;
549 g_sync_timing[VO_OUTPUT_USER].hmid = sync_info->hmid;
550 g_sync_timing[VO_OUTPUT_USER].bvact = sync_info->bvact;
551 g_sync_timing[VO_OUTPUT_USER].bvbb = sync_info->bvbb;
552 g_sync_timing[VO_OUTPUT_USER].bvfb = sync_info->bvfb;
553 g_sync_timing[VO_OUTPUT_USER].hpw = sync_info->hpw;
554 g_sync_timing[VO_OUTPUT_USER].vpw = sync_info->vpw;
555 g_sync_timing[VO_OUTPUT_USER].idv = sync_info->idv;
556 g_sync_timing[VO_OUTPUT_USER].ihs = sync_info->ihs;
557 g_sync_timing[VO_OUTPUT_USER].ivs = sync_info->ivs;
558 }
559
vo_drv_check_dev_pll_param(hi_vo_dev dev,hi_vo_user_intfsync_pll * pll)560 hi_s32 vo_drv_check_dev_pll_param(hi_vo_dev dev, hi_vo_user_intfsync_pll *pll)
561 {
562 if ((pll->fbdiv > VO_PLL_FBDIV_MAX) ||
563 (pll->frac > VO_PLL_FRAC_MAX) ||
564 (pll->refdiv > VO_PLL_REFDIV_MAX) ||
565 (pll->refdiv == 0) ||
566 (pll->postdiv1 > VO_PLL_POSTDIV1_MAX) ||
567 (pll->postdiv1 == 0) ||
568 (pll->postdiv2 > VO_PLL_POSTDIV2_MAX) ||
569 (pll->postdiv2 == 0)) {
570 vo_err_trace("dev(%d) pll param (fbdiv,frac,refdiv,postdiv1,postdiv2)="
571 "(0x%x,0x%x,0x%x,0x%x,0x%x) illegal .\n",
572 dev, pll->fbdiv, pll->frac, pll->refdiv, pll->postdiv1, pll->postdiv2);
573 return HI_FAILURE;
574 }
575
576 return HI_SUCCESS;
577 }
578
vo_drv_check_dev_pll_postdiv(hi_vo_dev dev,hi_vo_user_intfsync_pll * pll)579 hi_s32 vo_drv_check_dev_pll_postdiv(hi_vo_dev dev, hi_vo_user_intfsync_pll *pll)
580 {
581 if (pll->postdiv1 < pll->postdiv2) {
582 vo_err_trace("dev(%d) pll postdiv (postdiv1,postdiv2)="
583 "(0x%x,0x%x) illegal.\n",
584 dev, pll->postdiv1, pll->postdiv2);
585 return HI_FAILURE;
586 }
587
588 return HI_SUCCESS;
589 }
590
vo_drv_check_dev_pll_foutvco(hi_vo_dev dev,hi_vo_user_intfsync_pll * pll)591 hi_s32 vo_drv_check_dev_pll_foutvco(hi_vo_dev dev, hi_vo_user_intfsync_pll *pll)
592 {
593 hi_u32 foutcvo;
594
595 /* 0x01000000: 2^24 */
596 foutcvo = VO_PLL_FREF * pll->fbdiv / pll->refdiv + VO_PLL_FREF * pll->frac / VO_PLL_FRAC_PREC / pll->refdiv;
597 if (foutcvo < VO_PLL_FOUTCVO_MIN || foutcvo > VO_PLL_FOUTCVO_MAX) {
598 vo_err_trace("dev(%d) pll foutcvo (fbdiv,frac,refdiv)="
599 "(0x%x,0x%x,0x%x) illegal .\n",
600 dev, pll->fbdiv, pll->frac, pll->refdiv);
601 return HI_FAILURE;
602 }
603
604 return HI_SUCCESS;
605 }
606
vo_drv_check_dev_pll(hi_vo_dev dev,hi_vo_user_intfsync_pll * pll)607 hi_s32 vo_drv_check_dev_pll(hi_vo_dev dev, hi_vo_user_intfsync_pll *pll)
608 {
609 hi_s32 pll_check;
610 pll_check = vo_drv_check_dev_pll_param(dev, pll);
611 if (pll_check != HI_SUCCESS) {
612 return HI_FAILURE;
613 }
614 pll_check = vo_drv_check_dev_pll_postdiv(dev, pll);
615 if (pll_check != HI_SUCCESS) {
616 return HI_FAILURE;
617 }
618 pll_check = vo_drv_check_dev_pll_foutvco(dev, pll);
619 if (pll_check != HI_SUCCESS) {
620 return HI_FAILURE;
621 }
622
623 return HI_SUCCESS;
624 }
625
vo_drv_check_dev_lcdmclkdiv(hi_vo_dev dev,hi_u32 lcd_m_clk_div)626 hi_s32 vo_drv_check_dev_lcdmclkdiv(hi_vo_dev dev, hi_u32 lcd_m_clk_div)
627 {
628 if (lcd_m_clk_div > VO_LCDMCLK_DIV_MAX || lcd_m_clk_div == 0) {
629 vo_err_trace("dev(%d) lcd_mclk value %d illegal, it must be in (0,%d].\n",
630 dev, lcd_m_clk_div, VO_LCDMCLK_DIV_MAX);
631 return HI_FAILURE;
632 }
633
634 return HI_SUCCESS;
635 }
636
vo_drv_check_dev_clksource(hi_vo_dev dev,hi_vo_clk_source cs)637 hi_s32 vo_drv_check_dev_clksource(hi_vo_dev dev, hi_vo_clk_source cs)
638 {
639 if (cs == VO_CLK_SOURCE_PLL) {
640 /* support pll. */
641 } else if (cs == VO_CLK_SOURCE_LCDMCLK) {
642 /* support lcdmclk. */
643 } else {
644 vo_err_trace("dev(%d) clk source %d illegal.\n", dev, cs);
645 return HI_FAILURE;
646 }
647
648 return HI_SUCCESS;
649 }
650
vo_drv_check_dev_clkvalue(hi_vo_dev dev,hi_vo_user_intfsync_info * user_info)651 hi_s32 vo_drv_check_dev_clkvalue(hi_vo_dev dev, hi_vo_user_intfsync_info *user_info)
652 {
653 hi_vo_user_intfsync_attr *user_intf_sync_attr = &user_info->user_intf_sync_attr;
654 hi_vo_user_intfsync_pll *user_intf_sync_pll = &user_info->user_intf_sync_attr.user_sync_pll;
655 hi_s32 value_check;
656
657 if (user_intf_sync_attr->clk_source == VO_CLK_SOURCE_PLL) {
658 value_check = vo_drv_check_dev_pll(dev, user_intf_sync_pll);
659 } else if (user_intf_sync_attr->clk_source == VO_CLK_SOURCE_LCDMCLK) {
660 value_check = vo_drv_check_dev_lcdmclkdiv(dev, user_intf_sync_attr->lcd_m_clk_div);
661 } else {
662 return HI_FAILURE;
663 }
664
665 return value_check;
666 }
667
vo_drv_check_dev_user_sync_info(hi_vo_dev dev,hi_vo_user_intfsync_info * user_info)668 hi_s32 vo_drv_check_dev_user_sync_info(hi_vo_dev dev, hi_vo_user_intfsync_info *user_info)
669 {
670 hi_vo_user_intfsync_attr *user_intf_sync_attr = &user_info->user_intf_sync_attr;
671 hi_s32 info_check;
672
673 if (dev != VO_DEV_DHD0) {
674 vo_err_trace("dev(%d) is illegal.\n", dev);
675 return HI_ERR_VO_ILLEGAL_PARAM;
676 }
677
678 info_check = vo_drv_check_dev_clksource(dev, user_intf_sync_attr->clk_source);
679 if (info_check != HI_SUCCESS) {
680 return HI_ERR_VO_ILLEGAL_PARAM;
681 }
682
683 info_check = vo_drv_check_dev_clkvalue(dev, user_info);
684 if (info_check != HI_SUCCESS) {
685 return HI_ERR_VO_ILLEGAL_PARAM;
686 }
687
688 if ((user_info->dev_div > VO_MAX_DIV_MODE) || (user_info->dev_div < VO_MIN_DIV_MODE)) {
689 vo_err_trace("VO(%d) div mode %d is illegal,it must be in [%d,%d].\n", dev, user_info->dev_div,
690 VO_MIN_DIV_MODE, VO_MAX_DIV_MODE);
691 return HI_ERR_VO_ILLEGAL_PARAM;
692 }
693
694 if ((user_info->pre_div > VO_MAX_HDMI_DIV) || (user_info->pre_div < VO_MIN_HDMI_DIV)) {
695 vo_err_trace("VO(%d) pre div %d is illegal,it must be in [%d,%d].\n", dev, user_info->pre_div,
696 VO_MIN_HDMI_DIV, VO_MAX_HDMI_DIV);
697 return HI_ERR_VO_ILLEGAL_PARAM;
698 }
699
700 if ((user_info->clk_reverse != HI_TRUE) && (user_info->clk_reverse != HI_FALSE)) {
701 vo_err_trace("VO(%d) clk_reverse:%d is illegal, it must be HI_TRUE or HI_FALSE.\n", dev,
702 user_info->clk_reverse);
703 return HI_ERR_VO_ILLEGAL_PARAM;
704 }
705 return HI_SUCCESS;
706 }
707
vo_drv_set_dev_user_intf_sync_attr(hi_vo_dev dev,hi_vo_user_intfsync_attr * user_attr)708 hi_void vo_drv_set_dev_user_intf_sync_attr(hi_vo_dev dev, hi_vo_user_intfsync_attr *user_attr)
709 {
710 hi_mpp_chn mpp_chn = {0};
711 hi_u32 fbdiv;
712 hi_u32 frac;
713 hi_u32 refdiv;
714 hi_u32 postdiv1;
715 hi_u32 postdiv2;
716 hi_vo_user_intfsync_pll *user_sync_pll = HI_NULL;
717 hi_u32 vdp_out_clk_sel = 0x0;
718 hi_u32 lcd_mclk_div = 0x015E4C3;
719
720 hi_bool clk_en = HI_TRUE;
721
722 mpp_chn.mod_id = HI_ID_VO;
723 mpp_chn.dev_id = dev;
724 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
725 user_sync_pll = &user_attr->user_sync_pll;
726 fbdiv = user_sync_pll->fbdiv;
727 frac = user_sync_pll->frac;
728 refdiv = user_sync_pll->refdiv;
729 postdiv1 = user_sync_pll->postdiv1;
730 postdiv2 = user_sync_pll->postdiv2;
731 if (dev == VO_DEV_DHD0) {
732 if (user_attr->clk_source == VO_CLK_SOURCE_PLL) {
733 vdp_out_clk_sel = 0x0;
734 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_OUT_CLK_SEL, &vdp_out_clk_sel);
735
736 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_PLL_FBDIV_SET, &fbdiv);
737 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_PLL_FRAC_SET, &frac);
738 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_PLL_REFDIV_SET, &refdiv);
739 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_PLL_POSTDIV1_SET, &postdiv1);
740 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_PLL_POSTDIV2_SET, &postdiv2);
741 } else if (user_attr->clk_source == VO_CLK_SOURCE_LCDMCLK) {
742 vdp_out_clk_sel = 0x6;
743 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_OUT_CLK_SEL, &vdp_out_clk_sel);
744 lcd_mclk_div = user_attr->lcd_m_clk_div;
745 call_sys_drv_ioctrl(&mpp_chn, SYS_LCD_MCLK_DIV, &lcd_mclk_div);
746 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_LCD_CLK_EN, &clk_en);
747 }
748 } else {
749 vo_err_trace("VO dev %d is illegal.\n", dev);
750 }
751 return;
752 }
753
vo_drv_set_dev_div(hi_vo_dev dev,hi_u32 dev_div)754 hi_void vo_drv_set_dev_div(hi_vo_dev dev, hi_u32 dev_div)
755 {
756 hi_mpp_chn mpp_chn = {0};
757 hi_u32 div_mode = dev_div - 1;
758 hi_vo_intf_type intf_type;
759
760 mpp_chn.mod_id = HI_ID_VO;
761 mpp_chn.dev_id = dev;
762 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
763
764 if (dev == VO_DEV_DHD0) {
765 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_HD0_DIV_MOD, &div_mode);
766 }
767
768 intf_type = g_hal_dev_cfg[dev].intf_type;
769
770 if ((VO_INTF_LCD_6BIT & intf_type) || (VO_INTF_LCD_8BIT & intf_type)) {
771 if (dev_div == 3) {
772 hal_disp_set_lcd_serial_perd(0);
773 } else {
774 hal_disp_set_lcd_serial_perd(1);
775 }
776 }
777 return;
778 }
779
vo_drv_set_hdmi_div(hi_vo_dev dev,hi_u32 pre_div)780 hi_void vo_drv_set_hdmi_div(hi_vo_dev dev, hi_u32 pre_div)
781 {
782 hi_mpp_chn mpp_chn = {0};
783 hi_u32 pre_divmode;
784
785 pre_divmode = pre_div - 1;
786
787 mpp_chn.mod_id = HI_ID_VO;
788 mpp_chn.dev_id = dev;
789 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
790
791 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_HDMI_CLK_SEL, &pre_divmode);
792 }
793
vo_drv_set_clk_reverse(hi_bool reverse)794 hi_void vo_drv_set_clk_reverse(hi_bool reverse)
795 {
796 hi_mpp_chn mpp_chn = {0};
797
798 mpp_chn.mod_id = HI_ID_VO;
799 mpp_chn.dev_id = VO_MPP_CHN_DEV_DEF_VAL;
800 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
801
802 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_HD_CLKOUT_PHASIC_REVERSE_EN, &reverse);
803 return;
804 }
805
806 /* interrupt relative */
vo_drv_dev_int_enable(hi_vo_dev dev,hi_bool enable)807 hi_void vo_drv_dev_int_enable(hi_vo_dev dev, hi_bool enable)
808 {
809 hi_u32 int_type;
810 hi_u32 hifb_int_type;
811
812 if (dev != VO_DEV_DHD0) {
813 return;
814 }
815 int_type = VO_INTMSK_DHD0_VTTHD1;
816 hifb_int_type = VO_INTMSK_DHD0_VTTHD3 | VO_INTMSK_DHD0_VTTHD2;
817
818 if (enable == HI_TRUE) {
819 hal_disp_set_int_mask(int_type);
820 hal_disp_set_int_mask1(hifb_int_type);
821 } else {
822 hal_disp_clr_int_mask(int_type);
823 hal_disp_clr_int_mask1(hifb_int_type);
824 }
825
826 return;
827 }
828
vou_drv_int_clear(hi_u32 int_clear)829 hi_void vou_drv_int_clear(hi_u32 int_clear)
830 {
831 hal_disp_clear_int_status(int_clear);
832 }
833
vou_drv_int_disable_all(hi_void)834 hi_void vou_drv_int_disable_all(hi_void)
835 {
836 hal_disp_clr_int_mask(VO_INTREPORT_ALL);
837 }
838
vo_drv_int_set_mode(hi_vo_dev dev,vo_int_mode int_mode)839 hi_void vo_drv_int_set_mode(hi_vo_dev dev, vo_int_mode int_mode)
840 {
841 hal_disp_set_vt_thd_mode(dev, int_mode);
842
843 return;
844 }
845
vou_drv_check_dev_intf(hi_vo_dev dev,hi_vo_intf_type intf_type)846 static hi_s32 vou_drv_check_dev_intf(hi_vo_dev dev, hi_vo_intf_type intf_type)
847 {
848 HI_ASSERT((dev == VO_DEV_DHD0));
849
850 if ((intf_type & ~(VO_INTF_HDMI | VO_INTF_BT1120 | VO_INTF_BT656 | VO_INTF_MIPI | VO_INTF_LCD_6BIT |
851 VO_INTF_LCD_8BIT | VO_INTF_LCD_16BIT | VO_INTF_LCD_18BIT | VO_INTF_LCD_24BIT)) ||
852 (intf_type == 0)) {
853 vo_err_trace("device HD%d does not support intf(%d) !\n", dev, intf_type);
854 return HI_ERR_VO_NOT_SUPPORT;
855 }
856
857 if ((intf_type & ~VO_INTF_HDMI) && (intf_type & ~VO_INTF_BT1120) && (intf_type & ~VO_INTF_BT656) &&
858 (intf_type & ~VO_INTF_MIPI) && (intf_type & ~VO_INTF_LCD_6BIT) && (intf_type & ~VO_INTF_LCD_8BIT) &&
859 (intf_type & ~VO_INTF_LCD_16BIT) && (intf_type & ~VO_INTF_LCD_18BIT) && (intf_type & ~VO_INTF_LCD_24BIT)) {
860 vo_err_trace("this chip do not support more than one intfcace be used at the same time!\n");
861 return HI_ERR_VO_NOT_SUPPORT;
862 }
863
864 return HI_SUCCESS;
865 }
866
vou_drv_check_hdmi_sync(hi_vo_dev dev,hi_vo_intf_type intf_type,hi_vo_intf_sync intf_sync)867 static hi_s32 vou_drv_check_hdmi_sync(hi_vo_dev dev, hi_vo_intf_type intf_type, hi_vo_intf_sync intf_sync)
868 {
869 if (intf_type & VO_INTF_HDMI) {
870 if (!(((intf_sync >= VO_OUTPUT_1080P24) && (intf_sync <= VO_OUTPUT_640x480_60)) ||
871 ((intf_sync >= VO_OUTPUT_1920x2160_30) && (intf_sync <= VO_OUTPUT_3840x2160_30)))) {
872 vo_err_trace("for HDMI intface, vo%d's intfsync %d illegal!\n", dev, intf_sync);
873 return HI_ERR_VO_NOT_SUPPORT;
874 }
875
876 if ((intf_sync >= VO_OUTPUT_1920x2160_30) && (intf_sync <= VO_OUTPUT_3840x2160_30)) {
877 vo_err_trace("the intf_sync is not support!");
878 return HI_ERR_VO_NOT_SUPPORT;
879 }
880 }
881
882 return HI_SUCCESS;
883 }
884
vou_drv_check_mipi_sync(hi_vo_dev dev,hi_vo_intf_type intf_type,hi_vo_intf_sync intf_sync)885 static hi_s32 vou_drv_check_mipi_sync(hi_vo_dev dev, hi_vo_intf_type intf_type, hi_vo_intf_sync intf_sync)
886 {
887 if ((intf_type & VO_INTF_MIPI)) {
888 if (!((intf_sync >= VO_OUTPUT_720x1280_60) && (intf_sync <= VO_OUTPUT_1080x1920_60))) {
889 vo_err_trace("for MIPI OR MIPI_SLAVE intface, vo%d's intfsync %d illegal!\n",
890 dev, intf_sync);
891 return HI_ERR_VO_NOT_SUPPORT;
892 }
893 }
894
895 return HI_SUCCESS;
896 }
897
vou_drv_check_bt1120_sync(hi_vo_dev dev,hi_vo_intf_type intf_type,hi_vo_intf_sync intf_sync)898 static hi_s32 vou_drv_check_bt1120_sync(hi_vo_dev dev, hi_vo_intf_type intf_type, hi_vo_intf_sync intf_sync)
899 {
900 if (intf_type & VO_INTF_BT1120) {
901 if ((intf_sync < VO_OUTPUT_1080P24) || (intf_sync > VO_OUTPUT_640x480_60)) {
902 vo_err_trace("for BT1120 intface, vo%d's intfsync %d illegal!\n", dev, intf_sync);
903 return HI_ERR_VO_NOT_SUPPORT;
904 }
905 }
906
907 return HI_SUCCESS;
908 }
909
vou_drv_check_bt656_sync(hi_vo_dev dev,hi_vo_intf_type intf_type,hi_vo_intf_sync intf_sync)910 static hi_s32 vou_drv_check_bt656_sync(hi_vo_dev dev, hi_vo_intf_type intf_type, hi_vo_intf_sync intf_sync)
911 {
912 if ((intf_type & VO_INTF_BT656)) {
913 if ((intf_sync != VO_OUTPUT_PAL) && (intf_sync != VO_OUTPUT_NTSC)) {
914 vo_err_trace("for BT656 intface,vo%d's intfsync %d illegal!\n", dev, intf_sync);
915 return HI_ERR_VO_NOT_SUPPORT;
916 }
917 }
918
919 return HI_SUCCESS;
920 }
921
vou_drv_check_lcd_sync(hi_vo_dev dev,hi_vo_intf_type intf_type,hi_vo_intf_sync intf_sync)922 static hi_s32 vou_drv_check_lcd_sync(hi_vo_dev dev, hi_vo_intf_type intf_type, hi_vo_intf_sync intf_sync)
923 {
924 if (intf_type & VO_INTF_LCD_8BIT) {
925 if (intf_sync != VO_OUTPUT_320x240_60) {
926 vo_err_trace("for LCD 8bit intface,vo%d's intfsync %d illegal!\n", dev, intf_sync);
927 return HI_ERR_VO_NOT_SUPPORT;
928 }
929 }
930
931 if (intf_type & VO_INTF_LCD_6BIT) {
932 if ((intf_sync < VO_OUTPUT_320x240_50) || (intf_sync > VO_OUTPUT_240x320_50)) {
933 vo_err_trace("for LCD 6bit intface,vo%d's intfsync %d illegal!\n", dev, intf_sync);
934 return HI_ERR_VO_NOT_SUPPORT;
935 }
936 }
937
938 if (intf_type & VO_INTF_LCD_16BIT) {
939 if (intf_sync != VO_OUTPUT_240x320_60) {
940 vo_err_trace("for LCD 16bit intface,vo%d's intfsync %d illegal!\n", dev, intf_sync);
941 return HI_ERR_VO_NOT_SUPPORT;
942 }
943 }
944
945 if (intf_type & VO_INTF_LCD_18BIT) {
946 if (intf_sync != VO_OUTPUT_USER) {
947 vo_err_trace("for LCD 18bit intface,vo%d's intfsync %d illegal!\n", dev, intf_sync);
948 return HI_ERR_VO_NOT_SUPPORT;
949 }
950 }
951
952 if (intf_type & VO_INTF_LCD_24BIT) {
953 if (intf_sync != VO_OUTPUT_800x600_50) {
954 vo_err_trace("for LCD 24bit intface,vo%d's intfsync %d illegal!\n", dev, intf_sync);
955 return HI_ERR_VO_NOT_SUPPORT;
956 }
957 }
958 return HI_SUCCESS;
959 }
960
vou_drv_check_dev_sync(hi_vo_dev dev,hi_vo_intf_type intf_type,hi_vo_intf_sync intf_sync)961 static hi_s32 vou_drv_check_dev_sync(hi_vo_dev dev, hi_vo_intf_type intf_type, hi_vo_intf_sync intf_sync)
962 {
963 hi_s32 ret;
964 if (intf_sync == VO_OUTPUT_USER) {
965 /*
966 * user defined sync will be welcome for all interface type
967 * WARNING: user must make sure to config right sync, otherwise, screen doesn't't work!
968 */
969 return HI_SUCCESS;
970 }
971
972 if ((intf_sync == VO_OUTPUT_960H_PAL) || (intf_sync == VO_OUTPUT_960H_NTSC)) {
973 vo_err_trace("vo%d's intfsync %d illegal, vo doesn't support interlace sync %d!\n", dev,
974 intf_sync, intf_sync);
975 return HI_ERR_VO_NOT_SUPPORT;
976 }
977
978 ret = vou_drv_check_hdmi_sync(dev, intf_type, intf_sync);
979 if (ret != HI_SUCCESS) {
980 return ret;
981 }
982
983 ret = vou_drv_check_mipi_sync(dev, intf_type, intf_sync);
984 if (ret != HI_SUCCESS) {
985 return ret;
986 }
987
988 ret = vou_drv_check_bt1120_sync(dev, intf_type, intf_sync);
989 if (ret != HI_SUCCESS) {
990 return ret;
991 }
992
993 ret = vou_drv_check_bt656_sync(dev, intf_type, intf_sync);
994 if (ret != HI_SUCCESS) {
995 return ret;
996 }
997
998 ret = vou_drv_check_lcd_sync(dev, intf_type, intf_sync);
999 if (ret != HI_SUCCESS) {
1000 return ret;
1001 }
1002
1003 return HI_SUCCESS;
1004 }
1005
vou_drv_check_dev_pub_attr(hi_vo_dev dev,hi_vo_pub_attr * pub_attr)1006 hi_s32 vou_drv_check_dev_pub_attr(hi_vo_dev dev, hi_vo_pub_attr *pub_attr)
1007 {
1008 hi_s32 ret;
1009
1010 ret = vou_drv_check_dev_intf(dev, pub_attr->intf_type);
1011 if (ret != HI_SUCCESS) {
1012 vo_err_trace("vo%d check device's interface %d illegal!\n", dev, pub_attr->intf_type);
1013 return ret;
1014 }
1015
1016 ret = vou_drv_check_dev_sync(dev, pub_attr->intf_type, pub_attr->intf_sync);
1017 if (ret != HI_SUCCESS) {
1018 return ret;
1019 }
1020
1021 return HI_SUCCESS;
1022 }
1023
vou_drv_set_dev_full_frame_rate(hi_vo_dev dev,hi_u32 frame_rate)1024 hi_s32 vou_drv_set_dev_full_frame_rate(hi_vo_dev dev, hi_u32 frame_rate)
1025 {
1026 hi_unused(dev);
1027 hi_unused(frame_rate);
1028 return HI_SUCCESS;
1029 }
1030
vou_drv_set_pub_attr(hi_vo_dev dev,hi_vo_pub_attr * pub_attr)1031 hi_s32 vou_drv_set_pub_attr(hi_vo_dev dev, hi_vo_pub_attr *pub_attr)
1032 {
1033 vo_drv_dev *drv_dev_ctx = HI_NULL;
1034 drv_dev_ctx = vo_drv_get_dev_ctx(dev);
1035 (hi_void)memcpy_s(&drv_dev_ctx->vou_attr, sizeof(hi_vo_pub_attr), pub_attr, sizeof(hi_vo_pub_attr));
1036 drv_dev_ctx->config = HI_TRUE;
1037
1038 return HI_SUCCESS;
1039 }
1040
vou_drv_set_user_sync_info(hi_vo_dev dev,hi_vo_user_intfsync_info * info)1041 hi_s32 vou_drv_set_user_sync_info(hi_vo_dev dev, hi_vo_user_intfsync_info *info)
1042 {
1043 hi_unused(dev);
1044 hi_unused(info);
1045 return HI_SUCCESS;
1046 }
1047
vou_drv_layer_enable(hi_vo_layer layer,hi_bool enable)1048 hi_void vou_drv_layer_enable(hi_vo_layer layer, hi_bool enable)
1049 {
1050 hal_video_hfir_set_ck_gt_en(layer, enable);
1051 hal_layer_enable_layer(layer, enable);
1052 return;
1053 }
1054
vou_drv_set_layer_bk_grd(hi_vo_layer layer,hi_u32 bk_grd)1055 hi_void vou_drv_set_layer_bk_grd(hi_vo_layer layer, hi_u32 bk_grd)
1056 {
1057 g_hal_layer_cfg[layer].bk_grd = bk_grd;
1058 return;
1059 }
1060
vou_drv_set_layer_data_fmt(hi_vo_layer layer,vou_layer_pixerl_format data_fmt)1061 hi_void vou_drv_set_layer_data_fmt(hi_vo_layer layer, vou_layer_pixerl_format data_fmt)
1062 {
1063 hal_disp_layer hal_layer;
1064 hal_disp_pixel_format disp_data_fmt;
1065
1066 hal_layer = vou_drv_convert_layer(layer);
1067 disp_data_fmt = vou_drv_convert_data_format(data_fmt);
1068 hal_layer_set_layer_data_fmt(hal_layer, disp_data_fmt);
1069 return;
1070 }
1071
vou_drv_get_layer_data_fmt(hi_vo_layer layer,vou_layer_pixerl_format * data_fmt)1072 hi_void vou_drv_get_layer_data_fmt(hi_vo_layer layer, vou_layer_pixerl_format *data_fmt)
1073 {
1074 hal_disp_layer hal_layer;
1075 hal_disp_pixel_format disp_data_fmt;
1076
1077 hal_layer = vou_drv_convert_layer(layer);
1078
1079 hal_layer_get_layer_data_fmt(hal_layer, &disp_data_fmt);
1080
1081 switch (disp_data_fmt) {
1082 case HAL_INPUTFMT_YCBCR_SEMIPLANAR_400:
1083 *data_fmt = VOU_LAYER_PIXERL_FORMAT_SP_YCBCR_400;
1084 break;
1085 case HAL_INPUTFMT_YCBCR_SEMIPLANAR_420:
1086 *data_fmt = VOU_LAYER_PIXERL_FORMAT_SP_YCBCR_420;
1087 break;
1088 case HAL_INPUTFMT_YCBCR_SEMIPLANAR_422:
1089 *data_fmt = VOU_LAYER_PIXERL_FORMAT_SP_YCBCR_422;
1090 break;
1091 default:
1092 vo_warn_trace("layer(%d) get hal data format %d\n", layer, disp_data_fmt);
1093 break;
1094 }
1095 }
1096
vou_drv_is_virt_dev(hi_vo_dev dev)1097 hi_bool vou_drv_is_virt_dev(hi_vo_dev dev)
1098 {
1099 hi_unused(dev);
1100 return HI_FALSE;
1101 }
1102
vo_drv_get_dev_hal_id(hi_vo_dev dev,vo_hal_dev * hal_dev)1103 hi_void vo_drv_get_dev_hal_id(hi_vo_dev dev, vo_hal_dev *hal_dev)
1104 {
1105 switch (dev) {
1106 case VO_DEV_INDEX0:
1107 *hal_dev = VO_DEV_DHD0;
1108 break;
1109 default:
1110 vo_err_trace("dev %d is illegal.\n", dev);
1111 break;
1112 }
1113 }
1114
vo_drv_get_channel_hal_id(hi_vo_dev dev,hal_disp_outputchannel * vo_channel)1115 hi_void vo_drv_get_channel_hal_id(hi_vo_dev dev, hal_disp_outputchannel *vo_channel)
1116 {
1117 switch (dev) {
1118 case VO_CHANNEL_INDEX0:
1119 *vo_channel = HAL_DISP_CHANNEL_DHD0;
1120 break;
1121 default:
1122 vo_err_trace("dev %d is illegal.\n", dev);
1123 break;
1124 }
1125 }
1126
vou_drv_def_layer_bind_dev(hi_void)1127 hi_void vou_drv_def_layer_bind_dev(hi_void)
1128 {
1129 hal_cbm_set_cbm_mixer_prio(HAL_DISP_LAYER_VHD0, VOU_MIX_PRIO0, HAL_CBMMIX1);
1130 hal_cbm_set_cbm_mixer_prio(HAL_DISP_LAYER_GFX0, VOU_MIX_PRIO1, HAL_CBMMIX1);
1131
1132 return;
1133 }
1134
vo_drv_set_dev_bg_color(hi_vo_dev dev,hi_u32 bg_color,hi_bool rgb)1135 hi_void vo_drv_set_dev_bg_color(hi_vo_dev dev, hi_u32 bg_color, hi_bool rgb)
1136 {
1137 hal_disp_bkcolor bkg = {0};
1138 hi_u32 yuv_bk_grd = 0;
1139 if (rgb) {
1140 /* for 24bit value. */
1141 bkg.bkg_y = RGB_R(bg_color);
1142 bkg.bkg_cb = RGB_G(bg_color);
1143 bkg.bkg_cr = RGB_B(bg_color);
1144 bkg.bkg_y = bkg.bkg_y << 2;
1145 bkg.bkg_cb = bkg.bkg_cb << 2;
1146 bkg.bkg_cr = bkg.bkg_cr << 2;
1147 } else {
1148 yuv_bk_grd = rgb2_yuv_full(bg_color);
1149 bkg.bkg_y = YUV_Y(yuv_bk_grd);
1150 bkg.bkg_cb = YUV_U(yuv_bk_grd);
1151 bkg.bkg_cr = YUV_V(yuv_bk_grd);
1152 }
1153
1154 if (dev == VO_DEV_DHD0) {
1155 hal_cbm_set_cbm_bkg(HAL_CBMMIX1, &bkg);
1156 } else if (dev == VO_DEV_DHD1) {
1157 hal_cbm_set_cbm_bkg(HAL_CBMMIX2, &bkg);
1158 }
1159 }
1160
vo_drv_set_cbm_bkg(hi_vo_dev dev)1161 static hi_void vo_drv_set_cbm_bkg(hi_vo_dev dev)
1162 {
1163 hal_disp_bkcolor bkg;
1164 hi_u32 yuv_bk_grd = 0;
1165 hi_vo_intf_type intf_type;
1166 hal_dev_config *hal_dev_cfg = HI_NULL;
1167
1168 hal_dev_cfg = &g_hal_dev_cfg[dev];
1169 intf_type = hal_dev_cfg->intf_type;
1170
1171 if ((VO_INTF_LCD & intf_type) || (VO_INTF_LCD_6BIT & intf_type) || (VO_INTF_LCD_8BIT & intf_type) ||
1172 (VO_INTF_LCD_16BIT & intf_type) || (VO_INTF_LCD_18BIT & intf_type) || (VO_INTF_LCD_24BIT & intf_type) ||
1173 (VO_INTF_MIPI & intf_type) || (VO_INTF_MIPI_SLAVE & intf_type)) {
1174 /* for 24bit value. */
1175 bkg.bkg_y = RGB_R(hal_dev_cfg->bk_grd);
1176 bkg.bkg_cb = RGB_G(hal_dev_cfg->bk_grd);
1177 bkg.bkg_cr = RGB_B(hal_dev_cfg->bk_grd);
1178 bkg.bkg_y = bkg.bkg_y << 2;
1179 bkg.bkg_cb = bkg.bkg_cb << 2;
1180 bkg.bkg_cr = bkg.bkg_cr << 2;
1181 } else {
1182 yuv_bk_grd = rgb2_yuv_full(hal_dev_cfg->bk_grd);
1183 bkg.bkg_y = YUV_Y(yuv_bk_grd);
1184 bkg.bkg_cb = YUV_U(yuv_bk_grd);
1185 bkg.bkg_cr = YUV_V(yuv_bk_grd);
1186 }
1187
1188 hal_cbm_set_cbm_bkg(HAL_CBMMIX1, &bkg);
1189 }
1190
vo_drv_get_intf_property(hi_vo_dev dev,hal_disp_syncinfo * sync_info,hal_disp_syncinv * inv)1191 static hi_void vo_drv_get_intf_property(hi_vo_dev dev, hal_disp_syncinfo *sync_info, hal_disp_syncinv *inv)
1192 {
1193 hal_dev_config *hal_dev_cfg = HI_NULL;
1194
1195 hal_dev_cfg = &g_hal_dev_cfg[dev];
1196
1197 (hi_void)memcpy_s(sync_info, sizeof(hal_disp_syncinfo),
1198 &g_sync_timing[hal_dev_cfg->out_sync], sizeof(hal_disp_syncinfo));
1199 inv->hs_inv = sync_info->ihs ? 1 : 0;
1200 inv->vs_inv = sync_info->ivs ? 1 : 0;
1201 inv->dv_inv = sync_info->idv ? 1 : 0;
1202 }
1203
vo_drv_set_intf_hdmi_cfg(hi_vo_dev dev,hal_disp_syncinv * inv)1204 static hi_void vo_drv_set_intf_hdmi_cfg(hi_vo_dev dev, hal_disp_syncinv *inv)
1205 {
1206 hi_mpp_chn mpp_chn;
1207 hi_bool hdmi_clk_en = HI_TRUE;
1208 hi_bool hdmi_tx_clk_en = HI_TRUE;
1209
1210 mpp_chn.mod_id = HI_ID_VO;
1211 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
1212 mpp_chn.dev_id = dev;
1213
1214 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_HDMI_CLK_EN, &hdmi_clk_en); /* [10] VDP hdmi_cken */
1215 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_HDMI_TX_CLK_EN, &hdmi_tx_clk_en); /* [18] VDP hdmi_tx_cken */
1216 if ((g_hal_dev_cfg[dev].out_sync == VO_OUTPUT_576P50) ||
1217 (g_hal_dev_cfg[dev].out_sync == VO_OUTPUT_480P60)) {
1218 inv->hs_inv = 1 - inv->hs_inv;
1219 inv->vs_inv = 1 - inv->vs_inv;
1220 }
1221 }
1222
vo_drv_set_intf_mipi_cfg(hi_vo_dev dev,hal_disp_syncinv * inv)1223 static hi_void vo_drv_set_intf_mipi_cfg(hi_vo_dev dev, hal_disp_syncinv *inv)
1224 {
1225 hi_mpp_chn mpp_chn;
1226 U_INTF_LCD_CTRL lcd_ctrl;
1227 hal_disp_outputchannel vo_channel = HAL_DISP_CHANNEL_BUTT;
1228 hi_bool mipi_clk_en = HI_TRUE;
1229 hi_bool mipi_tx_clk_en = HI_TRUE;
1230 hi_vo_intf_type intf_type;
1231 hal_dev_config *hal_dev_cfg = HI_NULL;
1232
1233 hal_dev_cfg = &g_hal_dev_cfg[dev];
1234 intf_type = hal_dev_cfg->intf_type;
1235
1236 mpp_chn.mod_id = HI_ID_VO;
1237 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
1238 mpp_chn.dev_id = dev;
1239
1240 vo_drv_get_channel_hal_id(dev, &vo_channel);
1241
1242 if (VO_INTF_MIPI & intf_type) {
1243 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_MIPI_CLK_EN, &mipi_clk_en); /* [11] VDP mipi_cken */
1244 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_MIPI_TX_CLK_EN, &mipi_tx_clk_en); /* [19] VDP mipi_tx_cken */
1245
1246 hal_disp_set_intf_mux_sel(vo_channel, VO_INTF_MIPI);
1247
1248 lcd_ctrl.bits.hdmi_mode = 1;
1249 hal_disp_set_intf_ctrl(intf_type, &(lcd_ctrl.u32));
1250
1251 hal_intf_bt_set_dfir_en(0x1);
1252
1253 g_vo_drv_layer[dev].csc.csc_matrix = VO_CSC_MATRIX_BT709_TO_RGB_PC;
1254
1255 inv->hs_inv = 0;
1256 inv->vs_inv = 0;
1257 inv->dv_inv = 0;
1258 }
1259 }
1260
vo_drv_set_intf_bt1120_cfg(hi_vo_dev dev)1261 static hi_void vo_drv_set_intf_bt1120_cfg(hi_vo_dev dev)
1262 {
1263 hi_mpp_chn mpp_chn;
1264 hal_disp_outputchannel vo_channel = HAL_DISP_CHANNEL_BUTT;
1265 hi_bool bt_clk_en = HI_TRUE;
1266 hi_u32 data_mode;
1267
1268 mpp_chn.mod_id = HI_ID_VO;
1269 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
1270 mpp_chn.dev_id = dev;
1271
1272 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_BT1120_CLK_EN, &bt_clk_en); /* [8][9] bt clk en ,bt bp en. */
1273
1274 hal_disp_set_intf_mux_sel(vo_channel, VO_INTF_BT1120);
1275
1276 /* for bt1120 interface image effect. */
1277 if (vo_get_transparent_transmit() == HI_TRUE) {
1278 hal_intf_bt_set_dfir_en(0x0);
1279 } else {
1280 hal_intf_bt_set_dfir_en(0x1);
1281 }
1282 data_mode = 5; /* 5, bt1120 mode */
1283 call_sys_drv_ioctrl(&mpp_chn, SYS_LCD_DATA_MODE, &data_mode);
1284 }
1285
vo_drv_set_intf_bt656_cfg(hi_vo_dev dev,hi_u32 * div_mode)1286 static hi_void vo_drv_set_intf_bt656_cfg(hi_vo_dev dev, hi_u32 *div_mode)
1287 {
1288 hi_mpp_chn mpp_chn;
1289 hal_disp_outputchannel vo_channel = HAL_DISP_CHANNEL_BUTT;
1290 hi_bool bt_clk_en = HI_TRUE;
1291 hi_u32 data_mode;
1292
1293 mpp_chn.mod_id = HI_ID_VO;
1294 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
1295 mpp_chn.dev_id = dev;
1296
1297 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_BT1120_CLK_EN, &bt_clk_en);
1298
1299 hal_disp_set_intf_mux_sel(vo_channel, VO_INTF_BT656);
1300 hal_intf_bt_set_dfir_en(0x1);
1301 *div_mode = 1;
1302 data_mode = 6; /* 6, bt656 mode */
1303 call_sys_drv_ioctrl(&mpp_chn, SYS_LCD_DATA_MODE, &data_mode);
1304 }
1305
vo_drv_set_intf_lcd_ctrl(hi_vo_intf_type intf_type,hi_u32 * div_mode,hi_bool * clk_reverse,hi_u32 * data_mode,U_INTF_LCD_CTRL * lcd_ctrl)1306 static hi_void vo_drv_set_intf_lcd_ctrl(hi_vo_intf_type intf_type, hi_u32 *div_mode,
1307 hi_bool *clk_reverse, hi_u32 *data_mode, U_INTF_LCD_CTRL *lcd_ctrl)
1308 {
1309 if (VO_INTF_LCD_8BIT & intf_type) {
1310 *div_mode = 3;
1311 *data_mode = 3;
1312 lcd_ctrl->bits.hdmi_mode = 1;
1313 lcd_ctrl->bits.lcd_serial_mode = 1;
1314 lcd_ctrl->bits.lcd_serial_perd = 1;
1315 lcd_ctrl->bits.lcd_parallel_order = 0;
1316 lcd_ctrl->bits.lcd_data_inv = 0;
1317 lcd_ctrl->bits.lcd_parallel_mode = 1; /* 0:RGB565, 1:RGB888 */
1318 } else if (VO_INTF_LCD_6BIT & intf_type) {
1319 *div_mode = 2;
1320 *data_mode = 4;
1321
1322 lcd_ctrl->bits.lcd_serial_mode = 1;
1323 lcd_ctrl->bits.lcd_serial_perd = 0;
1324 lcd_ctrl->bits.lcd_parallel_order = 0;
1325 lcd_ctrl->bits.lcd_data_inv = 0;
1326 lcd_ctrl->bits.lcd_parallel_mode = 0;
1327 } else if (VO_INTF_LCD_16BIT & intf_type) {
1328 *div_mode = 0;
1329 *data_mode = 2;
1330
1331 lcd_ctrl->bits.lcd_serial_mode = 0;
1332 lcd_ctrl->bits.lcd_serial_perd = 0;
1333 lcd_ctrl->bits.lcd_parallel_order = 0;
1334 lcd_ctrl->bits.lcd_data_inv = 0;
1335 lcd_ctrl->bits.lcd_parallel_mode = 1;
1336 } else if (VO_INTF_LCD_18BIT & intf_type) {
1337 *div_mode = 0;
1338 *data_mode = 1;
1339
1340 lcd_ctrl->bits.lcd_serial_mode = 0;
1341 lcd_ctrl->bits.lcd_serial_perd = 0;
1342 lcd_ctrl->bits.lcd_parallel_order = 0;
1343 lcd_ctrl->bits.lcd_data_inv = 0;
1344 lcd_ctrl->bits.lcd_parallel_mode = 1;
1345 } else if (VO_INTF_LCD_24BIT & intf_type) {
1346 *clk_reverse = HI_FALSE;
1347 *div_mode = 0;
1348 *data_mode = 0;
1349
1350 lcd_ctrl->bits.lcd_serial_mode = 0;
1351 lcd_ctrl->bits.lcd_serial_perd = 0;
1352 lcd_ctrl->bits.lcd_parallel_order = 0;
1353 lcd_ctrl->bits.lcd_data_inv = 0;
1354 lcd_ctrl->bits.lcd_parallel_mode = 1;
1355 }
1356 }
1357
vo_drv_set_intf_lcd_cfg(hi_vo_dev dev,hi_bool * clk_reverse,hi_u32 * div_mode)1358 static hi_void vo_drv_set_intf_lcd_cfg(hi_vo_dev dev, hi_bool *clk_reverse, hi_u32 *div_mode)
1359 {
1360 hi_u32 data_mode;
1361 hi_mpp_chn mpp_chn;
1362 U_INTF_LCD_CTRL lcd_ctrl;
1363 hal_disp_outputchannel vo_channel = HAL_DISP_CHANNEL_BUTT;
1364 hi_bool bt_clk_en = HI_TRUE;
1365 hi_bool clk_en = HI_TRUE;
1366
1367 hi_vo_intf_type intf_type;
1368 hi_vo_intf_sync out_sync;
1369 hal_dev_config *hal_dev_cfg = HI_NULL;
1370
1371 hal_dev_cfg = &g_hal_dev_cfg[dev];
1372 intf_type = hal_dev_cfg->intf_type;
1373 out_sync = hal_dev_cfg->out_sync;
1374
1375 mpp_chn.mod_id = HI_ID_VO;
1376 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
1377 mpp_chn.dev_id = dev;
1378
1379 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_BT1120_CLK_EN, &bt_clk_en);
1380 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_LCD_CLK_EN, &clk_en);
1381
1382 hal_disp_set_intf_mux_sel(vo_channel, intf_type);
1383
1384 vo_drv_set_intf_lcd_ctrl(intf_type, div_mode, clk_reverse, &data_mode, &lcd_ctrl);
1385
1386 call_sys_drv_ioctrl(&mpp_chn, SYS_LCD_DATA_MODE, &data_mode);
1387
1388 hal_disp_set_intf_ctrl(intf_type, &(lcd_ctrl.u32));
1389
1390 if (out_sync != VO_OUTPUT_USER) {
1391 hal_disp_set_lcd_serial_perd(lcd_ctrl.bits.lcd_serial_perd);
1392 }
1393
1394 g_vo_drv_layer[dev].csc.csc_matrix = VO_CSC_MATRIX_BT709_TO_RGB_PC;
1395 }
1396
vo_drv_set_intf_cfg(hi_vo_dev dev,hal_disp_syncinv * inv,hi_bool * clk_reverse,hi_u32 * div_mode)1397 static hi_void vo_drv_set_intf_cfg(hi_vo_dev dev, hal_disp_syncinv *inv, hi_bool *clk_reverse, hi_u32 *div_mode)
1398 {
1399 hi_vo_intf_type intf_type;
1400 hal_dev_config *hal_dev_cfg = HI_NULL;
1401
1402 hal_dev_cfg = &g_hal_dev_cfg[dev];
1403 intf_type = hal_dev_cfg->intf_type;
1404
1405 if (VO_INTF_HDMI & intf_type) {
1406 vo_drv_set_intf_hdmi_cfg(dev, inv);
1407 }
1408
1409 if ((VO_INTF_MIPI & intf_type) || (VO_INTF_MIPI_SLAVE & intf_type)) {
1410 vo_drv_set_intf_mipi_cfg(dev, inv);
1411 }
1412
1413 if (VO_INTF_BT1120 & intf_type) {
1414 vo_drv_set_intf_bt1120_cfg(dev);
1415 }
1416
1417 if (VO_INTF_BT656 & intf_type) {
1418 vo_drv_set_intf_bt656_cfg(dev, div_mode);
1419 }
1420
1421 if ((VO_INTF_LCD & intf_type) || (VO_INTF_LCD_6BIT & intf_type) || (VO_INTF_LCD_8BIT & intf_type) ||
1422 (VO_INTF_LCD_16BIT & intf_type) || (VO_INTF_LCD_18BIT & intf_type) || (VO_INTF_LCD_24BIT & intf_type)) {
1423 vo_drv_set_intf_lcd_cfg(dev, clk_reverse, div_mode);
1424 }
1425 }
1426
vo_drv_set_dev_out_reverse(hi_vo_dev dev,hi_bool clk_reverse)1427 static hi_void vo_drv_set_dev_out_reverse(hi_vo_dev dev, hi_bool clk_reverse)
1428 {
1429 hi_mpp_chn mpp_chn;
1430 hi_vo_intf_sync out_sync;
1431 hal_dev_config *hal_dev_cfg = HI_NULL;
1432
1433 hal_dev_cfg = &g_hal_dev_cfg[dev];
1434 out_sync = hal_dev_cfg->out_sync;
1435
1436 mpp_chn.mod_id = HI_ID_VO;
1437 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
1438 mpp_chn.dev_id = dev;
1439
1440 if (out_sync != VO_OUTPUT_USER) {
1441 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_HD_CLKOUT_PHASIC_REVERSE_EN, &clk_reverse);
1442 }
1443 }
1444
vo_drv_set_div_mod(hi_vo_dev dev,hi_u32 * div_mode)1445 static hi_void vo_drv_set_div_mod(hi_vo_dev dev, hi_u32 *div_mode)
1446 {
1447 hi_mpp_chn mpp_chn;
1448 hi_vo_intf_sync out_sync;
1449 vo_hal_dev hal_dev = VO_DEV_BUTT;
1450 hal_dev_config *hal_dev_cfg = HI_NULL;
1451
1452 hal_dev_cfg = &g_hal_dev_cfg[dev];
1453 out_sync = hal_dev_cfg->out_sync;
1454
1455 mpp_chn.mod_id = HI_ID_VO;
1456 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
1457 mpp_chn.dev_id = dev;
1458
1459 /* get the id of vo device in hal level */
1460 vo_drv_get_dev_hal_id(dev, &hal_dev);
1461
1462 if (out_sync != VO_OUTPUT_USER) {
1463 if (hal_dev == VO_DEV_DHD0) {
1464 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_HD0_DIV_MOD, div_mode);
1465 }
1466 }
1467 }
1468
vo_drv_set_intf_clip(hi_vo_dev dev)1469 static hi_void vo_drv_set_intf_clip(hi_vo_dev dev)
1470 {
1471 hi_vo_intf_type intf_type;
1472 hal_dev_config *hal_dev_cfg = HI_NULL;
1473
1474 hal_dev_cfg = &g_hal_dev_cfg[dev];
1475 intf_type = hal_dev_cfg->intf_type;
1476
1477 if (VO_INTF_HDMI & intf_type) {
1478 hal_disp_clip clip_data = { 0x10, 0x10, 0x10, 0x3ff, 0x3ff, 0x3ff };
1479 hal_disp_set_intf_clip(VO_INTF_HDMI, HI_TRUE, &clip_data);
1480 }
1481
1482 if (VO_INTF_BT1120 & intf_type) {
1483 hal_disp_clip clip_data = {0x40, 0x40, 0x40, 0x3ac, 0x3c0, 0x3c0};
1484 hal_disp_set_intf_clip(VO_INTF_BT1120, HI_TRUE, &clip_data);
1485 }
1486
1487 if (VO_INTF_BT656 & intf_type) {
1488 hal_disp_clip clip_data = {0x40, 0x40, 0x40, 0x3ac, 0x3c0, 0x3c0};
1489 hal_disp_set_intf_clip(VO_INTF_BT656, HI_TRUE, &clip_data);
1490 }
1491 }
1492
vo_drv_set_vtth(hi_vo_dev dev,hal_disp_syncinfo * sync_info)1493 static hi_void vo_drv_set_vtth(hi_vo_dev dev, hal_disp_syncinfo *sync_info)
1494 {
1495 hi_u32 vtth_temp = 0;
1496 hi_u32 vtth_temp2 = 0;
1497 hi_u16 vert_all = 0;
1498 hi_u16 vtth_line2 = 0;
1499 hi_u16 vtth_line = 0;
1500 hi_u16 vtth_min = VO_HD_MIN_VTTH_WATERLINE;
1501 hal_dev_config *hal_dev_cfg = HI_NULL;
1502 hal_disp_outputchannel vo_channel = HAL_DISP_CHANNEL_BUTT;
1503
1504 hal_dev_cfg = &g_hal_dev_cfg[dev];
1505
1506 vo_drv_get_channel_hal_id(dev, &vo_channel);
1507
1508 if (vo_drv_is_phy_dev_hd(dev) || vo_drv_is_phy_dev_sd(dev)) {
1509 if (vo_drv_is_phy_dev_hd(dev)) {
1510 vtth_min = VO_HD_MIN_VTTH_WATERLINE;
1511 } else if (vo_drv_is_phy_dev_sd(dev)) {
1512 vtth_min = VO_SD_MIN_VTTH_WATERLINE;
1513 }
1514
1515 if (sync_info->iop == 0) {
1516 vo_drv_int_set_mode(dev, VO_INT_MODE_FIELD);
1517 vo_drv_int_reg_up_mode(dev, VO_INT_MODE_FIELD);
1518 } else {
1519 vo_drv_int_set_mode(dev, VO_INT_MODE_FRAME);
1520 vo_drv_int_reg_up_mode(dev, VO_INT_MODE_FRAME);
1521 }
1522
1523 vtth_temp = hal_dev_cfg->vtth;
1524 vtth_temp2 = hal_dev_cfg->vtth;
1525 vert_all = sync_info->vact + sync_info->vfb + sync_info->vbb;
1526
1527 if (vtth_temp >= vert_all) {
1528 /* argu 0 means : set to default value. */
1529 vou_drv_set_dev_vtth(dev, 0);
1530 vo_err_trace("VO device %d vtthd : %d is not in logic [%d,%d], set to default minimum: %d\n",
1531 dev, vtth_temp, vtth_min, vert_all - 1, hal_dev_cfg->vtth);
1532 }
1533
1534 if (vtth_temp2 >= vert_all) {
1535 /* argu 0 means : set to default value. */
1536 vou_drv_set_dev_vtth2(dev, 0);
1537 vo_err_trace("VO device %d vtthd2 : %d is not in logic [%d,%d], set to default minimum: %d\n",
1538 dev, vtth_temp2, vtth_min, vert_all - 1, hal_dev_cfg->vtth);
1539 }
1540
1541 vtth_line = vert_all - 1 - (hi_u16)vtth_temp;
1542 vtth_line2 = vert_all - 1 - (hi_u16)vtth_temp2;
1543 }
1544
1545 hal_disp_set_vt_thd(vo_channel, vtth_line, vtth_line2);
1546 }
1547
vo_drv_open(hi_vo_dev dev)1548 hi_void vo_drv_open(hi_vo_dev dev)
1549 {
1550 hal_disp_syncinfo sync_info;
1551 hal_disp_syncinv inv = {0};
1552 hi_mpp_chn mpp_chn;
1553 hi_bool clk_en = HI_TRUE;
1554 hi_bool clk_reverse = HI_TRUE;
1555 hal_disp_outputchannel vo_channel = HAL_DISP_CHANNEL_BUTT;
1556 hal_dev_config *hal_dev_cfg = HI_NULL;
1557 hi_vo_intf_type intf_type;
1558 hi_u32 div_mode = 0;
1559
1560 hal_dev_cfg = &g_hal_dev_cfg[dev];
1561 intf_type = hal_dev_cfg->intf_type;
1562
1563 mpp_chn.mod_id = HI_ID_VO;
1564 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
1565 mpp_chn.dev_id = dev;
1566
1567 vo_drv_get_channel_hal_id(dev, &vo_channel);
1568
1569 vo_drv_set_all_crg_clk(HI_TRUE);
1570
1571 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_OUT_CLK_EN, &clk_en);
1572
1573 vo_drv_set_cbm_bkg(dev);
1574
1575 vou_drv_init_default_csc(dev);
1576
1577 vo_drv_get_intf_property(dev, &sync_info, &inv);
1578
1579 vo_drv_set_intf_cfg(dev, &inv, &clk_reverse, &div_mode);
1580
1581 vo_drv_set_dev_out_reverse(dev, clk_reverse);
1582 vo_drv_set_div_mod(dev, &div_mode);
1583
1584 hal_disp_set_intf_sync(vo_channel, &sync_info, &inv);
1585
1586 hal_disp_set_dev_multi_chn_en(vo_channel, HAL_MULTICHN_EN_1P1C);
1587
1588 vo_drv_set_intf_clip(dev);
1589
1590 vo_drv_set_vtth(dev, &sync_info);
1591
1592 if ((VO_INTF_LCD_6BIT & intf_type) || (VO_INTF_LCD_16BIT & intf_type) || (VO_INTF_LCD_18BIT & intf_type)) {
1593 vou_drv_set_dev_dither_out(dev, 6); /* 6, 6bit */
1594 }
1595 vou_drv_set_dev_dither(dev, 10); /* 10, 10bit */
1596
1597 hal_disp_set_intf_enable(vo_channel, HI_TRUE);
1598
1599 vo_drv_dev_int_enable(dev, HI_TRUE);
1600
1601 hal_disp_set_reg_up(vo_channel);
1602
1603 return;
1604 }
1605
vo_drv_close(hi_vo_dev dev)1606 hi_void vo_drv_close(hi_vo_dev dev)
1607 {
1608 hi_mpp_chn mpp_chn;
1609 hi_bool clk_en = HI_FALSE;
1610 hi_u64 timeval = 0;
1611 hi_u64 time_begin;
1612
1613 hi_u32 vdp_out_clk_sel = 0x0;
1614 hi_u32 vdp_hd_clk_sel = 0x0;
1615 hal_disp_outputchannel vo_channel = HAL_DISP_CHANNEL_BUTT;
1616 hi_vo_intf_type intf_type = g_hal_dev_cfg[dev].intf_type;
1617
1618 hal_disp_set_intf_enable(dev, HI_FALSE);
1619 vo_drv_dev_int_enable(dev, HI_FALSE);
1620 hal_disp_set_reg_up(dev);
1621 vo_drv_get_channel_hal_id(dev, &vo_channel);
1622
1623 mpp_chn.mod_id = HI_ID_VO;
1624 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
1625 mpp_chn.dev_id = dev;
1626
1627 time_begin = get_sys_time_by_usec();
1628
1629 do {
1630 timeval = get_sys_time_by_usec() - time_begin;
1631 if (timeval >= 50000) { /* 50000us */
1632 break;
1633 }
1634 } while (hal_disp_get_reg_up(dev) != 0);
1635
1636 if (VO_INTF_HDMI & intf_type) {
1637 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_HDMI_CLK_EN, &clk_en);
1638 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_HDMI_TX_CLK_EN, &clk_en);
1639 }
1640
1641 if ((VO_INTF_BT656 & g_hal_dev_cfg[dev].intf_type) || (VO_INTF_BT1120 & g_hal_dev_cfg[dev].intf_type)) {
1642 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_OUT_CLK_EN, &clk_en);
1643 hal_disp_set_intf_mux_sel(vo_channel, HAL_DISP_INTF_BUTT);
1644 }
1645
1646 if (VO_INTF_MIPI & intf_type) {
1647 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_MIPI_CLK_EN, &clk_en);
1648 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_MIPI_TX_CLK_EN, &clk_en); /* [19] VDP mipi_tx_cken */
1649
1650 hal_disp_set_intf_mux_sel(vo_channel, HAL_DISP_INTF_BUTT);
1651 }
1652
1653 if ((VO_INTF_LCD & intf_type) || (VO_INTF_LCD_6BIT & intf_type) || (VO_INTF_LCD_8BIT & intf_type) ||
1654 (VO_INTF_LCD_16BIT & intf_type) || (VO_INTF_LCD_18BIT & intf_type) || (VO_INTF_LCD_24BIT & intf_type)) {
1655 call_sys_drv_ioctrl(&mpp_chn, SYS_VO_BT1120_CLK_EN, &clk_en);
1656
1657 hal_disp_set_intf_mux_sel(vo_channel, HAL_DISP_INTF_BUTT);
1658 }
1659 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_LCD_CLK_EN, &clk_en);
1660
1661 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_OUT_CLK_SEL, &vdp_out_clk_sel);
1662
1663 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_HD_CLK_SEL, &vdp_hd_clk_sel);
1664
1665 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_DEV_CLK_EN, &clk_en);
1666
1667 return;
1668 }
1669
vo_drv_enable(hi_vo_dev dev)1670 hi_void vo_drv_enable(hi_vo_dev dev)
1671 {
1672 g_vo_drv_dev[dev].vo_enable = HI_TRUE;
1673 }
1674
vo_drv_disable(hi_vo_dev dev)1675 hi_void vo_drv_disable(hi_vo_dev dev)
1676 {
1677 vo_drv_dev *drv_dev_ctx = &g_vo_drv_dev[dev];
1678
1679 drv_dev_ctx->config = HI_FALSE;
1680 drv_dev_ctx->vo_enable = HI_FALSE;
1681 (hi_void)memset_s(&drv_dev_ctx->vou_attr, sizeof(hi_vo_pub_attr), 0, sizeof(hi_vo_pub_attr));
1682 }
1683
vou_drv_default_setting(hi_void)1684 hi_void vou_drv_default_setting(hi_void)
1685 {
1686 hi_u32 i;
1687 hfir_coef h_coef = { 42, -10, -20, 28, -40, 61, -107, 330 };
1688
1689 for (i = LAYER_VHD_START; i <= LAYER_VHD_END; i++) {
1690 /* set each graphic layer global alpha */
1691 hal_layer_set_layer_g_alpha(i, 255); /* global alpha max 255 */
1692 hal_video_set_layer_alpha(i, 255); /* alpha max 255 */
1693
1694 /* set video layer hfir enable */
1695 hal_video_hfir_set_hfir_mode(i, HAL_HFIRMODE_COPY);
1696
1697 hal_video_hfir_set_coef(i, &h_coef);
1698 hal_video_hfir_set_mid_en(i, HI_TRUE);
1699 }
1700
1701 /* set each cross bar default PRI */
1702 vou_drv_def_layer_bind_dev();
1703
1704 hal_sys_set_outstanding();
1705
1706 hal_disp_clear_int_status(VO_INTREPORT_ALL);
1707
1708 /* only set video layer */
1709 for (i = 0; i <= LAYER_VHD_END; i++) {
1710 vou_drv_layer_enable(i, HI_FALSE);
1711 vou_drv_set_layer_data_fmt(i, VOU_LAYER_PIXERL_FORMAT_SP_YCBCR_422);
1712 vou_drv_set_layer_bk_grd(i, VO_BACKGROUD_DEFAULT);
1713 }
1714
1715 return;
1716 }
1717
vo_drv_transparent_transmit_setting(hi_bool transparent_transmit)1718 hi_void vo_drv_transparent_transmit_setting(hi_bool transparent_transmit)
1719 {
1720 hi_unused(transparent_transmit);
1721 }
1722
vou_drv_check_dev_id(hi_vo_dev dev)1723 hi_s32 vou_drv_check_dev_id(hi_vo_dev dev)
1724 {
1725 if ((dev < 0) || (dev >= VO_MAX_DEV_NUM)) {
1726 return HI_ERR_VO_INVALID_DEVID;
1727 }
1728
1729 return HI_SUCCESS;
1730 }
1731
vo_drv_dev_capability_init(hi_vo_dev dev)1732 static hi_void vo_drv_dev_capability_init(hi_vo_dev dev)
1733 {
1734 vo_dev_capability *dev_cap = NULL;
1735 dev_cap = &g_vo_drv_dev[dev].dev_cap;
1736
1737 switch (dev) {
1738 case VO_DEV_DHD0: {
1739 dev_cap->dev_type = VO_UHD_HW_DEV;
1740 dev_cap->hd_vpss_rciv = HI_FALSE;
1741 dev_cap->sd_tde_disp = HI_TRUE;
1742 dev_cap->support_wbc = HI_TRUE;
1743 dev_cap->spt_get_screen_frm = HI_TRUE;
1744 break;
1745 }
1746
1747 default:
1748 vo_err_trace("unknown dev %d!!\n", dev);
1749 break;
1750 }
1751
1752 return;
1753 }
1754
vo_drv_dev_info_init(hi_void)1755 hi_void vo_drv_dev_info_init(hi_void)
1756 {
1757 hi_s32 i;
1758 (hi_void)memset_s(g_vo_drv_dev, sizeof(vo_drv_dev) * VO_MAX_DEV_NUM,
1759 0, sizeof(vo_drv_dev) * VO_MAX_DEV_NUM);
1760
1761 for (i = 0; i < VO_MAX_DEV_NUM; i++) {
1762 vo_drv_dev_capability_init(i);
1763 if (i == VO_DEV_DHD0) {
1764 /* 2 video layer and 1 graphic layer in DHD0 */
1765 g_vo_drv_dev[i].layer_num = 1;
1766 g_vo_drv_dev[i].gfx_num = 1;
1767 g_vo_drv_dev[i].dither_info.dither_out_bit_width = 8; /* 8, 8bit */
1768 }
1769 }
1770
1771 return;
1772 }
1773
vo_drv_dev_info_part_init(hi_void)1774 hi_void vo_drv_dev_info_part_init(hi_void)
1775 {
1776 hi_s32 i;
1777
1778 for (i = 0; i < VO_MAX_DEV_NUM; i++) {
1779 vo_drv_dev_capability_init(i);
1780 if (i == VO_DEV_DHD0) {
1781 /* 2 video layer and 1 graphic layer in DHD0 */
1782 g_vo_drv_dev[i].layer_num = 1; /* 1 video layer */
1783 g_vo_drv_dev[i].gfx_num = 1; /* 1 gfx layer */
1784 g_vo_drv_dev[i].dither_info.dither_out_bit_width = 8; /* 8 bit */
1785 }
1786 }
1787
1788 return;
1789 }
1790
vo_drv_dev_info_de_init(hi_void)1791 hi_void vo_drv_dev_info_de_init(hi_void)
1792 {
1793 return;
1794 }
1795
vou_drv_special_work_flow(hi_vo_dev dev)1796 hi_bool vou_drv_special_work_flow(hi_vo_dev dev)
1797 {
1798 hi_unused(dev);
1799 return HI_FALSE;
1800 }
1801
vo_drv_is_phy_dev_hd(hi_vo_dev dev)1802 hi_bool vo_drv_is_phy_dev_hd(hi_vo_dev dev)
1803 {
1804 vo_dev_capability *dev_cap = &g_vo_drv_dev[dev].dev_cap;
1805 if ((dev_cap->dev_type == VO_UHD_HW_DEV) ||
1806 (dev_cap->dev_type == VO_HD_HW_DEV)) {
1807 return HI_TRUE;
1808 }
1809
1810 return HI_FALSE;
1811 }
1812
vo_drv_is_phy_dev_sd(hi_vo_dev dev)1813 hi_bool vo_drv_is_phy_dev_sd(hi_vo_dev dev)
1814 {
1815 if (g_vo_drv_dev[dev].dev_cap.dev_type == VO_SD_HW_DEV) {
1816 return HI_TRUE;
1817 }
1818
1819 return HI_FALSE;
1820 }
1821
vou_drv_set_disp_max_size(hi_vo_dev dev,hi_u32 max_width,hi_u32 max_height)1822 hi_void vou_drv_set_disp_max_size(hi_vo_dev dev, hi_u32 max_width, hi_u32 max_height)
1823 {
1824 g_vo_drv_dev[dev].max_width = max_width;
1825 g_vo_drv_dev[dev].max_height = max_height;
1826 }
1827
vou_drv_get_25_175_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1828 static hi_void vou_drv_get_25_175_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1829 {
1830 *vdp_hd_clk_sel = 1;
1831
1832 sync_pll->fbdiv = 67;
1833 sync_pll->frac = 5035000;
1834 sync_pll->refdiv = 2;
1835 sync_pll->postdiv1 = 2;
1836 sync_pll->postdiv2 = 1;
1837 sync_pll->hdmiclk_div = 0xf;
1838 }
1839
vou_drv_get_27_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1840 static hi_void vou_drv_get_27_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1841 {
1842 *vdp_hd_clk_sel = 1;
1843
1844 sync_pll->fbdiv = 72;
1845 sync_pll->frac = 0;
1846 sync_pll->refdiv = 2;
1847 sync_pll->postdiv1 = 2;
1848 sync_pll->postdiv2 = 1;
1849 sync_pll->hdmiclk_div = 0xf;
1850 }
1851
vou_drv_get_40_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1852 static hi_void vou_drv_get_40_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1853 {
1854 *vdp_hd_clk_sel = 1;
1855
1856 sync_pll->fbdiv = 160;
1857 sync_pll->frac = 0;
1858 sync_pll->refdiv = 3;
1859 sync_pll->postdiv1 = 2;
1860 sync_pll->postdiv2 = 1;
1861 sync_pll->hdmiclk_div = 0xf;
1862 }
1863
vou_drv_get_65_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1864 static hi_void vou_drv_get_65_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1865 {
1866 *vdp_hd_clk_sel = 1;
1867
1868 sync_pll->fbdiv = 130;
1869 sync_pll->frac = 0;
1870 sync_pll->refdiv = 3;
1871 sync_pll->postdiv1 = 2;
1872 sync_pll->postdiv2 = 1;
1873 sync_pll->hdmiclk_div = 0x7;
1874 }
1875
vou_drv_get_74_25_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1876 static hi_void vou_drv_get_74_25_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1877 {
1878 *vdp_hd_clk_sel = 1;
1879
1880 sync_pll->fbdiv = 99;
1881 sync_pll->frac = 0;
1882 sync_pll->refdiv = 2;
1883 sync_pll->postdiv1 = 2;
1884 sync_pll->postdiv2 = 1;
1885 sync_pll->hdmiclk_div = 0x7;
1886 }
1887
vou_drv_get_83_5_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1888 static hi_void vou_drv_get_83_5_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1889 {
1890 *vdp_hd_clk_sel = 1;
1891
1892 sync_pll->fbdiv = 114;
1893 sync_pll->frac = 0;
1894 sync_pll->refdiv = 2;
1895 sync_pll->postdiv1 = 2;
1896 sync_pll->postdiv2 = 1;
1897 sync_pll->hdmiclk_div = 0x7;
1898 }
1899
vou_drv_get_85_5_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1900 static hi_void vou_drv_get_85_5_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1901 {
1902 *vdp_hd_clk_sel = 1;
1903
1904 sync_pll->fbdiv = 167;
1905 sync_pll->frac = 0;
1906 sync_pll->refdiv = 3;
1907 sync_pll->postdiv1 = 2;
1908 sync_pll->postdiv2 = 1;
1909 sync_pll->hdmiclk_div = 0x7;
1910 }
1911
vou_drv_get_106_5_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1912 static hi_void vou_drv_get_106_5_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1913 {
1914 *vdp_hd_clk_sel = 1;
1915
1916 sync_pll->fbdiv = 71;
1917 sync_pll->frac = 0;
1918 sync_pll->refdiv = 2;
1919 sync_pll->postdiv1 = 2;
1920 sync_pll->postdiv2 = 1;
1921 sync_pll->hdmiclk_div = 0x3;
1922 }
1923
vou_drv_get_108_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1924 static hi_void vou_drv_get_108_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1925 {
1926 *vdp_hd_clk_sel = 1;
1927
1928 sync_pll->fbdiv = 72;
1929 sync_pll->frac = 0;
1930 sync_pll->refdiv = 2;
1931 sync_pll->postdiv1 = 2;
1932 sync_pll->postdiv2 = 1;
1933 sync_pll->hdmiclk_div = 0x3;
1934 }
1935
vou_drv_get_120_8496_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1936 static hi_void vou_drv_get_120_8496_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1937 {
1938 *vdp_hd_clk_sel = 1;
1939
1940 sync_pll->fbdiv = 119;
1941 sync_pll->frac = 6295000;
1942 sync_pll->refdiv = 3;
1943 sync_pll->postdiv1 = 2;
1944 sync_pll->postdiv2 = 1;
1945 sync_pll->hdmiclk_div = 0x3;
1946 }
1947
vou_drv_get_146_25_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1948 static hi_void vou_drv_get_146_25_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1949 {
1950 *vdp_hd_clk_sel = 0;
1951
1952 sync_pll->fbdiv = 146;
1953 sync_pll->frac = 4195000;
1954 sync_pll->refdiv = 3;
1955 sync_pll->postdiv1 = 2;
1956 sync_pll->postdiv2 = 1;
1957
1958 sync_pll->hdmiclk_div = 0x3;
1959 }
1960
vou_drv_get_148_5_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1961 static hi_void vou_drv_get_148_5_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1962 {
1963 *vdp_hd_clk_sel = 0;
1964
1965 sync_pll->fbdiv = 99;
1966 sync_pll->frac = 0;
1967 sync_pll->refdiv = 2;
1968 sync_pll->postdiv1 = 2;
1969 sync_pll->postdiv2 = 1;
1970 sync_pll->hdmiclk_div = 0x3;
1971 }
1972
vou_drv_get_154_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1973 static hi_void vou_drv_get_154_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1974 {
1975 *vdp_hd_clk_sel = 0;
1976
1977 sync_pll->fbdiv = 154;
1978 sync_pll->frac = 0;
1979 sync_pll->refdiv = 3;
1980 sync_pll->postdiv1 = 2;
1981 sync_pll->postdiv2 = 1;
1982 sync_pll->hdmiclk_div = 0x3;
1983 }
1984
vou_drv_get_162_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1985 static hi_void vou_drv_get_162_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1986 {
1987 *vdp_hd_clk_sel = 0;
1988
1989 sync_pll->fbdiv = 162;
1990 sync_pll->frac = 0;
1991 sync_pll->refdiv = 3;
1992 sync_pll->postdiv1 = 2;
1993 sync_pll->postdiv2 = 1;
1994 sync_pll->hdmiclk_div = 0x3;
1995 }
1996
vou_drv_get_241_6992_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)1997 static hi_void vou_drv_get_241_6992_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
1998 {
1999 *vdp_hd_clk_sel = 0;
2000
2001 sync_pll->fbdiv = 119;
2002 sync_pll->frac = 6295000;
2003 sync_pll->refdiv = 3;
2004 sync_pll->postdiv1 = 2;
2005 sync_pll->postdiv2 = 1;
2006 sync_pll->hdmiclk_div = 0x1;
2007 }
2008
vou_drv_get_268_5_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)2009 static hi_void vou_drv_get_268_5_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
2010 {
2011 *vdp_hd_clk_sel = 0;
2012
2013 sync_pll->fbdiv = 537;
2014 sync_pll->frac = 0;
2015 sync_pll->refdiv = 12;
2016 sync_pll->postdiv1 = 2;
2017 sync_pll->postdiv2 = 1;
2018 sync_pll->hdmiclk_div = 0x1;
2019 }
2020
vou_drv_get_297_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)2021 static hi_void vou_drv_get_297_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
2022 {
2023 *vdp_hd_clk_sel = 0;
2024
2025 sync_pll->fbdiv = 99;
2026 sync_pll->frac = 0;
2027 sync_pll->refdiv = 2;
2028 sync_pll->postdiv1 = 2;
2029 sync_pll->postdiv2 = 1;
2030 sync_pll->hdmiclk_div = 0x1;
2031 }
2032
vou_drv_get_594_config(hi_u32 * vdp_hd_clk_sel,vo_intfsync_pll * sync_pll)2033 static hi_void vou_drv_get_594_config(hi_u32 *vdp_hd_clk_sel, vo_intfsync_pll *sync_pll)
2034 {
2035 *vdp_hd_clk_sel = 0;
2036
2037 sync_pll->fbdiv = 99;
2038 sync_pll->frac = 0;
2039 sync_pll->refdiv = 2;
2040 sync_pll->postdiv1 = 2;
2041 sync_pll->postdiv2 = 1;
2042 sync_pll->hdmiclk_div = 0x0;
2043 }
2044
vou_drv_set_pll_timing(hi_u32 vdp_hd_clk_sel,hi_mpp_chn * mpp_chn,vo_intfsync_pll * sync_pll)2045 static hi_void vou_drv_set_pll_timing(hi_u32 vdp_hd_clk_sel, hi_mpp_chn *mpp_chn, vo_intfsync_pll *sync_pll)
2046 {
2047 hi_u32 vdp_out_clk_sel = 0x0;
2048
2049 call_sys_drv_ioctrl(mpp_chn, SYS_VOU_HD_CLK_SEL, &vdp_hd_clk_sel);
2050 call_sys_drv_ioctrl(mpp_chn, SYS_VOU_OUT_CLK_SEL, &vdp_out_clk_sel);
2051
2052 call_sys_drv_ioctrl(mpp_chn, SYS_VO_HDMI_CLK_SEL, &sync_pll->hdmiclk_div);
2053 call_sys_drv_ioctrl(mpp_chn, SYS_VO_PLL_FBDIV_SET, &sync_pll->fbdiv);
2054 call_sys_drv_ioctrl(mpp_chn, SYS_VO_PLL_FRAC_SET, &sync_pll->frac);
2055 call_sys_drv_ioctrl(mpp_chn, SYS_VO_PLL_REFDIV_SET, &sync_pll->refdiv);
2056 call_sys_drv_ioctrl(mpp_chn, SYS_VO_PLL_POSTDIV1_SET, &sync_pll->postdiv1);
2057 call_sys_drv_ioctrl(mpp_chn, SYS_VO_PLL_POSTDIV2_SET, &sync_pll->postdiv2);
2058 }
2059
vou_drv_set_dev_clk(hi_vo_dev dev)2060 hi_s32 vou_drv_set_dev_clk(hi_vo_dev dev)
2061 {
2062 hi_bool clk_en = HI_TRUE;
2063 hi_mpp_chn mpp_chn = {0};
2064 vo_drv_dev *dev_ctx = HI_NULL;
2065 hi_u32 vdp_hd_clk_sel = 0x0;
2066 hi_u32 vdp_out_clk_sel = 0x0;
2067 hi_u32 lcd_mclk_div = 0x015E4C3;
2068 vo_intfsync_pll sync_pll;
2069 dev_ctx = vo_drv_get_dev_ctx(dev);
2070
2071 mpp_chn.mod_id = HI_ID_VO;
2072 mpp_chn.dev_id = dev;
2073 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
2074
2075 if (dev_ctx->vou_attr.intf_sync == VO_OUTPUT_USER) {
2076 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_HD_CLK_SEL, &vdp_hd_clk_sel);
2077
2078 return HI_SUCCESS;
2079 }
2080
2081 switch (dev_ctx->vou_attr.intf_sync) {
2082 case VO_OUTPUT_PAL:
2083 case VO_OUTPUT_NTSC:
2084 case VO_OUTPUT_576P50:
2085 case VO_OUTPUT_480P60: {
2086 vou_drv_get_27_config(&vdp_hd_clk_sel, &sync_pll);
2087 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2088 break;
2089 }
2090 case VO_OUTPUT_1080P24:
2091 case VO_OUTPUT_1080P25:
2092 case VO_OUTPUT_1080P30:
2093 case VO_OUTPUT_720P50:
2094 case VO_OUTPUT_720P60:
2095 case VO_OUTPUT_1080I50:
2096 case VO_OUTPUT_1080I60:
2097 case VO_OUTPUT_720x1280_60: { /* for MIPI tx interface. */
2098 vou_drv_get_74_25_config(&vdp_hd_clk_sel, &sync_pll);
2099 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2100 break;
2101 }
2102 case VO_OUTPUT_1080P50:
2103 case VO_OUTPUT_1080P60:
2104 case VO_OUTPUT_1920x2160_30:
2105 case VO_OUTPUT_1080x1920_60: { /* for MIPI tx interface. */
2106 vou_drv_get_148_5_config(&vdp_hd_clk_sel, &sync_pll);
2107 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2108 break;
2109 }
2110 case VO_OUTPUT_640x480_60: {
2111 vou_drv_get_25_175_config(&vdp_hd_clk_sel, &sync_pll);
2112 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2113 break;
2114 }
2115 case VO_OUTPUT_800x600_60: {
2116 vou_drv_get_40_config(&vdp_hd_clk_sel, &sync_pll);
2117 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2118 break;
2119 }
2120 case VO_OUTPUT_1024x768_60: {
2121 vou_drv_get_65_config(&vdp_hd_clk_sel, &sync_pll);
2122 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2123 break;
2124 }
2125 case VO_OUTPUT_1280x1024_60: {
2126 vou_drv_get_108_config(&vdp_hd_clk_sel, &sync_pll);
2127 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2128 break;
2129 }
2130 case VO_OUTPUT_1366x768_60: {
2131 vou_drv_get_85_5_config(&vdp_hd_clk_sel, &sync_pll);
2132 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2133 break;
2134 }
2135 case VO_OUTPUT_1440x900_60: {
2136 vou_drv_get_106_5_config(&vdp_hd_clk_sel, &sync_pll);
2137 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2138 break;
2139 }
2140 case VO_OUTPUT_1280x800_60: {
2141 vou_drv_get_83_5_config(&vdp_hd_clk_sel, &sync_pll);
2142 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2143 break;
2144 }
2145 case VO_OUTPUT_1600x1200_60: {
2146 vou_drv_get_162_config(&vdp_hd_clk_sel, &sync_pll);
2147 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2148 break;
2149 }
2150 case VO_OUTPUT_1680x1050_60: {
2151 vou_drv_get_146_25_config(&vdp_hd_clk_sel, &sync_pll);
2152 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2153 break;
2154 }
2155 case VO_OUTPUT_1920x1200_60: {
2156 vou_drv_get_154_config(&vdp_hd_clk_sel, &sync_pll);
2157 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2158 break;
2159 }
2160 case VO_OUTPUT_320x240_60: {
2161 vdp_out_clk_sel = 0x6;
2162 lcd_mclk_div = 0x2aE4C3;
2163 call_sys_drv_ioctrl(&mpp_chn, SYS_LCD_MCLK_DIV, &lcd_mclk_div);
2164 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_OUT_CLK_SEL, &vdp_out_clk_sel);
2165 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_LCD_CLK_EN, &clk_en);
2166 break;
2167 }
2168 case VO_OUTPUT_320x240_50: {
2169 vdp_out_clk_sel = 0x6;
2170 lcd_mclk_div = 0x152306;
2171 call_sys_drv_ioctrl(&mpp_chn, SYS_LCD_MCLK_DIV, &lcd_mclk_div);
2172 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_OUT_CLK_SEL, &vdp_out_clk_sel);
2173 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_LCD_CLK_EN, &clk_en);
2174 break;
2175 }
2176 case VO_OUTPUT_240x320_50: {
2177 vdp_out_clk_sel = 0x6;
2178 lcd_mclk_div = 0x182ed6;
2179 call_sys_drv_ioctrl(&mpp_chn, SYS_LCD_MCLK_DIV, &lcd_mclk_div);
2180 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_OUT_CLK_SEL, &vdp_out_clk_sel);
2181 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_LCD_CLK_EN, &clk_en);
2182 break;
2183 }
2184 case VO_OUTPUT_240x320_60: {
2185 vdp_out_clk_sel = 0x6;
2186 lcd_mclk_div = 0x90c54;
2187 call_sys_drv_ioctrl(&mpp_chn, SYS_LCD_MCLK_DIV, &lcd_mclk_div);
2188 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_OUT_CLK_SEL, &vdp_out_clk_sel);
2189 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_LCD_CLK_EN, &clk_en);
2190 break;
2191 }
2192 case VO_OUTPUT_800x600_50: {
2193 vdp_out_clk_sel = 0x6;
2194 lcd_mclk_div = 0x3a9cc2;
2195 call_sys_drv_ioctrl(&mpp_chn, SYS_LCD_MCLK_DIV, &lcd_mclk_div);
2196 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_OUT_CLK_SEL, &vdp_out_clk_sel);
2197 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_LCD_CLK_EN, &clk_en);
2198 break;
2199 }
2200 case VO_OUTPUT_2560x1440_30: {
2201 vou_drv_get_120_8496_config(&vdp_hd_clk_sel, &sync_pll);
2202 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2203 break;
2204 }
2205 case VO_OUTPUT_2560x1440_60: {
2206 vou_drv_get_241_6992_config(&vdp_hd_clk_sel, &sync_pll);
2207 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2208 break;
2209 }
2210 case VO_OUTPUT_2560x1600_60: {
2211 vou_drv_get_268_5_config(&vdp_hd_clk_sel, &sync_pll);
2212 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2213 break;
2214 }
2215 case VO_OUTPUT_3840x2160_24:
2216 case VO_OUTPUT_3840x2160_25:
2217 case VO_OUTPUT_3840x2160_30: {
2218 vou_drv_get_297_config(&vdp_hd_clk_sel, &sync_pll);
2219 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2220 break;
2221 }
2222 case VO_OUTPUT_7680x4320_30:
2223 case VO_OUTPUT_3840x2160_60: {
2224 vou_drv_get_594_config(&vdp_hd_clk_sel, &sync_pll);
2225 vou_drv_set_pll_timing(vdp_hd_clk_sel, &mpp_chn, &sync_pll);
2226 break;
2227 }
2228 default: {
2229 return HI_SUCCESS;
2230 }
2231 }
2232
2233 return HI_SUCCESS;
2234 }
2235
vo_drv_set_all_crg_clk(hi_bool clk_en)2236 hi_void vo_drv_set_all_crg_clk(hi_bool clk_en)
2237 {
2238 hi_mpp_chn mpp_chn;
2239 hi_bool vo_clk_en = clk_en;
2240
2241 mpp_chn.mod_id = HI_ID_VO;
2242 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
2243 mpp_chn.dev_id = VO_MPP_CHN_DEV_DEF_VAL;
2244
2245 /* dev 0 :[4][5][6] sd ppc,hd ppc,hd0 clk; dev 1 :[4][5][7] sd ppc, hd ppc, hd1 clk */
2246 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_DEV_CLK_EN, &vo_clk_en);
2247 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_CORE_CLK_EN, &vo_clk_en); /* [5] hd ppc clk */
2248 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_CFG_CLK_EN, &vo_clk_en); /* [3] CFG clk */
2249 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_BUS_CLK_EN, &vo_clk_en); /* [2] AXI bus */
2250 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_APB_CLK_EN, &vo_clk_en); /* [1] APB clk */
2251
2252 return;
2253 }
2254
vo_drv_set_hd_clk_sel(hi_u32 hd_clk_sel)2255 hi_void vo_drv_set_hd_clk_sel(hi_u32 hd_clk_sel)
2256 {
2257 hi_unused(hd_clk_sel);
2258 }
2259
vo_lpw_bus_reset(hi_bool reset)2260 hi_void vo_lpw_bus_reset(hi_bool reset)
2261 {
2262 hi_mpp_chn mpp_chn;
2263 hi_bool vo_reset = reset;
2264
2265 mpp_chn.mod_id = HI_ID_VO;
2266 mpp_chn.dev_id = VO_MPP_CHN_DEV_DEF_VAL;
2267 mpp_chn.chn_id = VO_MPP_CHN_CHN_DEF_VAL;
2268 /* see sys_hal_vou_bus_reset_sel */
2269 call_sys_drv_ioctrl(&mpp_chn, SYS_VOU_BUS_RESET_SEL, &vo_reset);
2270
2271 return;
2272 }
2273
vo_set_low_power_ctrl_clk_en(hi_bool clk_en)2274 hi_void vo_set_low_power_ctrl_clk_en(hi_bool clk_en)
2275 {
2276 hi_unused(clk_en);
2277 }
2278
vou_drv_init_default_csc(hi_vo_layer layer)2279 hi_void vou_drv_init_default_csc(hi_vo_layer layer)
2280 {
2281 hi_s32 i;
2282 hi_vo_csc *csc = HI_NULL;
2283
2284 hi_unused(layer);
2285
2286 for (i = 0; i < VO_MAX_LAYER_NUM; i++) {
2287 csc = &g_vo_drv_layer[i].csc;
2288 csc->csc_matrix = VO_CSC_MATRIX_IDENTITY;
2289 csc->luma = VO_CSC_DEF_VAL;
2290 csc->contrast = VO_CSC_DEF_VAL;
2291 csc->hue = VO_CSC_DEF_VAL;
2292 csc->satuature = VO_CSC_DEF_VAL;
2293
2294 csc = &g_vo_drv_layer[i].vhdr_csc;
2295 csc->csc_matrix = VO_CSC_MATRIX_BT709_TO_RGB_PC;
2296 csc->luma = VO_CSC_DEF_VAL;
2297 csc->contrast = VO_CSC_DEF_VAL;
2298 csc->hue = VO_CSC_DEF_VAL;
2299 csc->satuature = VO_CSC_DEF_VAL;
2300 }
2301
2302 return;
2303 }
2304
vo_drv_set_dither_sed(hi_vo_dev dev,vdp_dither_mode dither_mode_set)2305 static hi_void vo_drv_set_dither_sed(hi_vo_dev dev, vdp_dither_mode dither_mode_set)
2306 {
2307 hal_disp_dihter_sed dither_sed = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
2308 hal_disp_outputchannel vo_channel = HAL_DISP_CHANNEL_BUTT;
2309 hi_u32 dither_thr_max = 0;
2310 hi_u32 dither_thr_min = 0;
2311
2312 vo_drv_get_channel_hal_id(dev, &vo_channel);
2313
2314 if (dither_mode_set == VDP_DITHER_MODE_TYP) {
2315 dither_sed.dither_sed_y0 = 2147483647;
2316 dither_sed.dither_sed_u0 = 2147482647;
2317 dither_sed.dither_sed_v0 = 2147481647;
2318 dither_sed.dither_sed_w0 = 2147480647;
2319 dither_sed.dither_sed_y1 = 2147483647;
2320 dither_sed.dither_sed_u1 = 2147482647;
2321 dither_sed.dither_sed_v1 = 2147481647;
2322 dither_sed.dither_sed_w1 = 2147480647;
2323 dither_sed.dither_sed_y2 = 2147483647;
2324 dither_sed.dither_sed_u2 = 2147482647;
2325 dither_sed.dither_sed_v2 = 2147481647;
2326 dither_sed.dither_sed_w2 = 2147480647;
2327 dither_sed.dither_sed_y3 = 2147483647;
2328 dither_sed.dither_sed_u3 = 2147482647;
2329 dither_sed.dither_sed_v3 = 2147481647;
2330 dither_sed.dither_sed_w3 = 2147480647;
2331 dither_thr_max = 60000;
2332 dither_thr_min = 120;
2333 } else if (dither_mode_set == VDP_DITHER_MODE_MAX) {
2334 dither_sed.dither_sed_y0 = 2147483647;
2335 dither_sed.dither_sed_u0 = 2147483647;
2336 dither_sed.dither_sed_v0 = 2147483647;
2337 dither_sed.dither_sed_w0 = 2147483647;
2338 dither_sed.dither_sed_y1 = 2147483647;
2339 dither_sed.dither_sed_u1 = 2147483647;
2340 dither_sed.dither_sed_v1 = 2147483647;
2341 dither_sed.dither_sed_w1 = 2147483647;
2342 dither_sed.dither_sed_y2 = 2147483647;
2343 dither_sed.dither_sed_u2 = 2147483647;
2344 dither_sed.dither_sed_v2 = 2147483647;
2345 dither_sed.dither_sed_w2 = 2147483647;
2346 dither_sed.dither_sed_y3 = 2147483647;
2347 dither_sed.dither_sed_u3 = 2147483647;
2348 dither_sed.dither_sed_v3 = 2147483647;
2349 dither_sed.dither_sed_w3 = 2147483647;
2350 dither_thr_max = 0;
2351 dither_thr_min = 0;
2352 }
2353
2354 hal_disp_set_dither_sed(vo_channel, &dither_sed);
2355 hal_disp_set_dither_thr_min_max(vo_channel, dither_thr_min, dither_thr_max);
2356 }
2357
vou_drv_set_dev_dither_mode(hi_vo_dev dev,vdp_dither_mode dither_mode_set,vdp_dither_cfg * cfg)2358 hi_void vou_drv_set_dev_dither_mode(hi_vo_dev dev, vdp_dither_mode dither_mode_set, vdp_dither_cfg *cfg)
2359 {
2360 hal_disp_outputchannel vo_channel = HAL_DISP_CHANNEL_BUTT;
2361 hi_u32 i_data_width_dither = 0;
2362 hi_u32 o_data_width_dither = 0;
2363 hi_u32 dither_io_md;
2364 hi_u32 dither_md = 0;
2365
2366 dither_io_md = cfg->io_mode;
2367
2368 if (dither_io_md == DITHER_IO_MODE_12_10) {
2369 dither_md = DITHER_MODE_10BIT;
2370 i_data_width_dither = DITHER_IWIDTH_MODE_12BIT;
2371 o_data_width_dither = DITHER_OWIDTH_MODE_10BIT;
2372 } else if (dither_io_md == DITHER_IO_MODE_12_8) {
2373 dither_md = DITHER_MODE_8BIT;
2374 i_data_width_dither = DITHER_IWIDTH_MODE_12BIT;
2375 o_data_width_dither = DITHER_OWIDTH_MODE_8BIT;
2376 } else if (dither_io_md == DITHER_IO_MODE_10_8) {
2377 dither_md = DITHER_MODE_8BIT;
2378 i_data_width_dither = DITHER_IWIDTH_MODE_10BIT;
2379 o_data_width_dither = DITHER_OWIDTH_MODE_8BIT;
2380 } else if (dither_io_md == DITHER_IO_MODE_10_6) {
2381 dither_md = DITHER_MODE_8BIT;
2382 i_data_width_dither = DITHER_IWIDTH_MODE_10BIT;
2383 o_data_width_dither = DITHER_OWIDTH_MODE_6BIT;
2384 } else if (dither_io_md == DITHER_IO_MODE_9_6) {
2385 dither_md = DITHER_MODE_8BIT;
2386 i_data_width_dither = DITHER_IWIDTH_MODE_9BIT;
2387 o_data_width_dither = DITHER_OWIDTH_MODE_6BIT;
2388 } else if (dither_io_md == DITHER_IO_MODE_8_6) {
2389 dither_md = DITHER_MODE_8BIT;
2390 i_data_width_dither = DITHER_IWIDTH_MODE_8BIT;
2391 o_data_width_dither = DITHER_OWIDTH_MODE_6BIT;
2392 } else if (dither_io_md == 0) {
2393 dither_md = DITHER_MODE_8BIT;
2394 i_data_width_dither = DITHER_IWIDTH_MODE_8BIT;
2395 o_data_width_dither = DITHER_OWIDTH_MODE_6BIT;
2396 } else {
2397 HI_ASSERT(0);
2398 }
2399
2400 vo_drv_get_channel_hal_id(dev, &vo_channel);
2401 /* drv transfer */
2402 hal_disp_set_dither_round_unlim(vo_channel, cfg->dither_round_unlim);
2403 hal_disp_set_dither_data_in_out(vo_channel, i_data_width_dither, o_data_width_dither);
2404 hal_disp_set_dither_en(vo_channel, cfg->dither_en);
2405 hal_disp_set_dither_mode(vo_channel, dither_md);
2406 hal_disp_set_dither_round(vo_channel, cfg->dither_round);
2407 hal_disp_set_dither_domain_mode(vo_channel, cfg->dither_domain_mode);
2408 hal_disp_set_dither_tap_mode(vo_channel, cfg->dither_tap_mode);
2409
2410 vo_drv_set_dither_sed(dev, dither_mode_set);
2411 }
2412
vou_drv_set_dev_dither_out(hi_vo_dev dev,hi_u32 out_bit_width)2413 hi_void vou_drv_set_dev_dither_out(hi_vo_dev dev, hi_u32 out_bit_width)
2414 {
2415 g_vo_drv_dev[dev].dither_info.dither_out_bit_width = out_bit_width;
2416 return;
2417 }
2418
vou_drv_set_dev_dither(hi_vo_dev dev,hi_u32 in_bit_widht)2419 hi_void vou_drv_set_dev_dither(hi_vo_dev dev, hi_u32 in_bit_widht)
2420 {
2421 vo_drv_dev *drv_dev_ctx = HI_NULL;
2422 vdp_dither_cfg dither_cfg;
2423
2424 drv_dev_ctx = vo_drv_get_dev_ctx(dev);
2425 drv_dev_ctx->dither_info.dither_in_bit_width = in_bit_widht;
2426
2427 if ((drv_dev_ctx->dither_info.dither_in_bit_width == 10) &&
2428 (drv_dev_ctx->dither_info.dither_out_bit_width == 8)) {
2429 dither_cfg.dither_en = 1;
2430 dither_cfg.dither_round = 1;
2431 dither_cfg.dither_round_unlim = 1;
2432 dither_cfg.dither_domain_mode = 1;
2433 dither_cfg.dither_tap_mode = 1;
2434 dither_cfg.io_mode = DITHER_IO_MODE_12_8;
2435
2436 vou_drv_set_dev_dither_mode(dev, VDP_DITHER_MODE_TYP, &dither_cfg);
2437 hal_disp_set_dither_en(dev, HI_TRUE);
2438 /* 4:12bit 5:10bit; 3:8bit */
2439 hal_disp_set_dither_data_in_out(dev, DITHER_IWIDTH_MODE_12BIT, DITHER_OWIDTH_MODE_10BIT);
2440 } else if ((drv_dev_ctx->dither_info.dither_in_bit_width == 10) &&
2441 (drv_dev_ctx->dither_info.dither_out_bit_width == 6)) {
2442 dither_cfg.dither_en = 1;
2443 dither_cfg.dither_round = 0;
2444 dither_cfg.dither_round_unlim = 1;
2445 dither_cfg.dither_domain_mode = 1;
2446 dither_cfg.dither_tap_mode = 1;
2447 dither_cfg.io_mode = DITHER_IO_MODE_10_6;
2448 vou_drv_set_dev_dither_mode(dev, VDP_DITHER_MODE_TYP, &dither_cfg);
2449 hal_disp_set_dither_en(dev, HI_TRUE);
2450 /* 4:12bit 5:10bit; 3:8bit */
2451 hal_disp_set_dither_data_in_out(dev, DITHER_IWIDTH_MODE_10BIT, DITHER_OWIDTH_MODE_6BIT);
2452 } else if (((drv_dev_ctx->dither_info.dither_in_bit_width == 10) &&
2453 (drv_dev_ctx->dither_info.dither_out_bit_width == 10)) ||
2454 ((drv_dev_ctx->dither_info.dither_in_bit_width == 8) &&
2455 (drv_dev_ctx->dither_info.dither_out_bit_width == 8))) {
2456 hal_disp_set_dither_en(dev, HI_FALSE);
2457 }
2458 }
2459
2460 #ifdef HI_DEBUG
vou_drv_lbw_show_proc(osal_proc_entry_t * s)2461 hi_void vou_drv_lbw_show_proc(osal_proc_entry_t *s)
2462 {
2463 hi_s32 i;
2464 vo_drv_dev *drv_dev_ctx = HI_NULL;
2465
2466 osal_seq_printf(s,
2467 "\n-----DEV LowBandwidth Info----------------------------------------------------------------\n");
2468
2469 osal_seq_printf(s, "%8s" "%15s" "\n", "DevId", "LowBandwidth");
2470
2471 for (i = 0; i < VO_MAX_DEV_NUM; i++) {
2472 drv_dev_ctx = vo_drv_get_dev_ctx(i);
2473
2474 if (drv_dev_ctx->vo_enable == HI_TRUE) {
2475 osal_seq_printf(s, "%8d" "%15d" "\n", i, drv_dev_ctx->low_bandwidth_cnt);
2476 }
2477 }
2478
2479 osal_seq_printf(s, "\r\n");
2480
2481 return;
2482 }
2483 #endif
2484
2485 #ifdef __cplusplus
2486 #if __cplusplus
2487 }
2488 #endif
2489 #endif /* end of #ifdef __cplusplus */
2490