1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18 #include "hdmi_reg_tx.h"
19 #include "hdmi_product_define.h"
20
21 volatile tx_hdmi_reg_regs_type *g_tx_hdmi_regs = NULL;
22
hdmi_reg_tx_hdmi_regs_init(hi_char * addr)23 int hdmi_reg_tx_hdmi_regs_init(hi_char *addr)
24 {
25 g_tx_hdmi_regs = (volatile tx_hdmi_reg_regs_type *)(addr + HDMI_TX_BASE_ADDR_HDMITX);
26 return HI_SUCCESS;
27 }
28
hdmi_reg_tx_hdmi_regs_deinit(void)29 int hdmi_reg_tx_hdmi_regs_deinit(void)
30 {
31 if (g_tx_hdmi_regs != HI_NULL) {
32 g_tx_hdmi_regs = HI_NULL;
33 }
34 return HI_SUCCESS;
35 }
36
hdmi_reg_tmds_pack_mode_set(unsigned int tmds_pack_mode)37 int hdmi_reg_tmds_pack_mode_set(unsigned int tmds_pack_mode)
38 {
39 hi_u32 *reg_addr = NULL;
40 tx_pack_fifo_ctrl tmp;
41
42 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->pack_fifo_ctrl.u32);
43 tmp.u32 = hdmi_tx_reg_read(reg_addr);
44 tmp.bits.tmds_pack_mode = tmds_pack_mode;
45 hdmi_tx_reg_write(reg_addr, tmp.u32);
46
47 return HI_SUCCESS;
48 }
49
hdmi_reg_avi_pkt_header_hb_set(unsigned int hb0,unsigned int hb1,unsigned int hb2)50 int hdmi_reg_avi_pkt_header_hb_set(unsigned int hb0, unsigned int hb1, unsigned int hb2)
51 {
52 hi_u32 *reg_addr = NULL;
53 avi_pkt_header tmp;
54
55 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_head.u32);
56 tmp.u32 = hdmi_tx_reg_read(reg_addr);
57 tmp.bits.avi_pkt_hb2 = hb2;
58 tmp.bits.avi_pkt_hb1 = hb1;
59 tmp.bits.avi_pkt_hb0 = hb0;
60 hdmi_tx_reg_write(reg_addr, tmp.u32);
61
62 return HI_SUCCESS;
63 }
64
hdmi_reg_avi_pkt0_low_set(unsigned int avi_pkt0_pb0,unsigned int avi_pkt0_pb1,unsigned int avi_pkt0_pb2,unsigned int avi_pkt0_pb3)65 int hdmi_reg_avi_pkt0_low_set(unsigned int avi_pkt0_pb0,
66 unsigned int avi_pkt0_pb1, unsigned int avi_pkt0_pb2, unsigned int avi_pkt0_pb3)
67 {
68 hi_u32 *reg_addr = NULL;
69 avi_sub_pkt0_low tmp;
70
71 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt0l.u32);
72 tmp.u32 = hdmi_tx_reg_read(reg_addr);
73 tmp.bits.avi_sub_pkt0_pb3 = avi_pkt0_pb3;
74 tmp.bits.avi_sub_pkt0_pb2 = avi_pkt0_pb2;
75 tmp.bits.avi_sub_pkt0_pb1 = avi_pkt0_pb1;
76 tmp.bits.avi_sub_pkt0_pb0 = avi_pkt0_pb0;
77 hdmi_tx_reg_write(reg_addr, tmp.u32);
78
79 return HI_SUCCESS;
80 }
81
hdmi_reg_avi_pkt0_high_set(unsigned int avi_pkt0_pb4,unsigned int avi_pkt0_pb5,unsigned int avi_pkt0_pb6)82 int hdmi_reg_avi_pkt0_high_set(unsigned int avi_pkt0_pb4, unsigned int avi_pkt0_pb5, unsigned int avi_pkt0_pb6)
83 {
84 hi_u32 *reg_addr = NULL;
85 avi_sub_pkt0_high tmp;
86
87 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt0h.u32);
88 tmp.u32 = hdmi_tx_reg_read(reg_addr);
89 tmp.bits.avi_sub_pkt0_pb6 = avi_pkt0_pb6;
90 tmp.bits.avi_sub_pkt0_pb5 = avi_pkt0_pb5;
91 tmp.bits.avi_sub_pkt0_pb4 = avi_pkt0_pb4;
92 hdmi_tx_reg_write(reg_addr, tmp.u32);
93
94 return HI_SUCCESS;
95 }
96
hdmi_reg_avi_pkt1_low_set(unsigned int avi_pkt1_pb0,unsigned int avi_pkt1_pb1,unsigned int avi_pkt1_pb2,unsigned int avi_pkt1_pb3)97 int hdmi_reg_avi_pkt1_low_set(unsigned int avi_pkt1_pb0,
98 unsigned int avi_pkt1_pb1, unsigned int avi_pkt1_pb2, unsigned int avi_pkt1_pb3)
99 {
100 hi_u32 *reg_addr = NULL;
101 avi_sub_pkt1_low tmp;
102
103 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt1l.u32);
104 tmp.u32 = hdmi_tx_reg_read(reg_addr);
105 tmp.bits.avi_sub_pkt1_pb3 = avi_pkt1_pb3;
106 tmp.bits.avi_sub_pkt1_pb2 = avi_pkt1_pb2;
107 tmp.bits.avi_sub_pkt1_pb1 = avi_pkt1_pb1;
108 tmp.bits.avi_sub_pkt1_pb0 = avi_pkt1_pb0;
109 hdmi_tx_reg_write(reg_addr, tmp.u32);
110
111 return HI_SUCCESS;
112 }
113
hdmi_reg_avi_pkt1_high_set(unsigned int avi_pkt1_pb4,unsigned int avi_pkt1_pb5,unsigned int avi_pkt1_pb6)114 int hdmi_reg_avi_pkt1_high_set(unsigned int avi_pkt1_pb4, unsigned int avi_pkt1_pb5, unsigned int avi_pkt1_pb6)
115 {
116 hi_u32 *reg_addr = NULL;
117 avi_sub_pkt1_high tmp;
118
119 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt1h.u32);
120 tmp.u32 = hdmi_tx_reg_read(reg_addr);
121 tmp.bits.avi_sub_pkt1_pb6 = avi_pkt1_pb6;
122 tmp.bits.avi_sub_pkt1_pb5 = avi_pkt1_pb5;
123 tmp.bits.avi_sub_pkt1_pb4 = avi_pkt1_pb4;
124 hdmi_tx_reg_write(reg_addr, tmp.u32);
125
126 return HI_SUCCESS;
127 }
128
hdmi_reg_avi_pkt2_low_set(unsigned int avi_pkt2_pb0,unsigned int avi_pkt2_pb1,unsigned int avi_pkt2_pb2,unsigned int avi_pkt2_pb3)129 int hdmi_reg_avi_pkt2_low_set(unsigned int avi_pkt2_pb0,
130 unsigned int avi_pkt2_pb1, unsigned int avi_pkt2_pb2, unsigned int avi_pkt2_pb3)
131 {
132 hi_u32 *reg_addr = NULL;
133 avi_sub_pkt2_low tmp;
134
135 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt2l.u32);
136 tmp.u32 = hdmi_tx_reg_read(reg_addr);
137 tmp.bits.avi_sub_pkt2_pb3 = avi_pkt2_pb3;
138 tmp.bits.avi_sub_pkt2_pb2 = avi_pkt2_pb2;
139 tmp.bits.avi_sub_pkt2_pb1 = avi_pkt2_pb1;
140 tmp.bits.avi_sub_pkt2_pb0 = avi_pkt2_pb0;
141 hdmi_tx_reg_write(reg_addr, tmp.u32);
142
143 return HI_SUCCESS;
144 }
145
hdmi_reg_avi_pkt2_high_set(unsigned int avi_pkt2_pb4,unsigned int avi_pkt2_pb5,unsigned int avi_pkt2_pb6)146 int hdmi_reg_avi_pkt2_high_set(unsigned int avi_pkt2_pb4, unsigned int avi_pkt2_pb5, unsigned int avi_pkt2_pb6)
147 {
148 hi_u32 *reg_addr = NULL;
149 avi_sub_pkt2_high tmp;
150
151 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt2h.u32);
152 tmp.u32 = hdmi_tx_reg_read(reg_addr);
153 tmp.bits.avi_sub_pkt2_pb6 = avi_pkt2_pb6;
154 tmp.bits.avi_sub_pkt2_pb5 = avi_pkt2_pb5;
155 tmp.bits.avi_sub_pkt2_pb4 = avi_pkt2_pb4;
156 hdmi_tx_reg_write(reg_addr, tmp.u32);
157
158 return HI_SUCCESS;
159 }
160
hdmi_reg_avi_pkt3_low_set(unsigned int avi_pkt3_pb0,unsigned int avi_pkt3_pb1,unsigned int avi_pkt3_pb2,unsigned int avi_pkt3_pb3)161 int hdmi_reg_avi_pkt3_low_set(unsigned int avi_pkt3_pb0,
162 unsigned int avi_pkt3_pb1, unsigned int avi_pkt3_pb2, unsigned int avi_pkt3_pb3)
163 {
164 hi_u32 *reg_addr = NULL;
165 avi_sub_pkt3_low tmp;
166
167 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt3l.u32);
168 tmp.u32 = hdmi_tx_reg_read(reg_addr);
169 tmp.bits.avi_sub_pkt3_pb3 = avi_pkt3_pb3;
170 tmp.bits.avi_sub_pkt3_pb2 = avi_pkt3_pb2;
171 tmp.bits.avi_sub_pkt3_pb1 = avi_pkt3_pb1;
172 tmp.bits.avi_sub_pkt3_pb0 = avi_pkt3_pb0;
173 hdmi_tx_reg_write(reg_addr, tmp.u32);
174
175 return HI_SUCCESS;
176 }
177
hdmi_reg_avi_pkt3_high_set(unsigned int avi_pkt3_pb4,unsigned int avi_pkt3_pb5,unsigned int avi_pkt3_pb6)178 int hdmi_reg_avi_pkt3_high_set(unsigned int avi_pkt3_pb4, unsigned int avi_pkt3_pb5, unsigned int avi_pkt3_pb6)
179 {
180 hi_u32 *reg_addr = NULL;
181 avi_sub_pkt3_high tmp;
182
183 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt3h.u32);
184 tmp.u32 = hdmi_tx_reg_read(reg_addr);
185 tmp.bits.avi_sub_pkt3_pb6 = avi_pkt3_pb6;
186 tmp.bits.avi_sub_pkt3_pb5 = avi_pkt3_pb5;
187 tmp.bits.avi_sub_pkt3_pb4 = avi_pkt3_pb4;
188 hdmi_tx_reg_write(reg_addr, tmp.u32);
189
190 return HI_SUCCESS;
191 }
192
hdmi_reg_avi_pkt_header_hb_get(avi_pkt_header * avi_header)193 int hdmi_reg_avi_pkt_header_hb_get(avi_pkt_header *avi_header)
194 {
195 hi_u32 *reg_addr = NULL;
196 avi_pkt_header tmp;
197
198 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_head.u32);
199 tmp.u32 = hdmi_tx_reg_read(reg_addr);
200 avi_header->bits.avi_pkt_hb2 = tmp.bits.avi_pkt_hb2;
201 avi_header->bits.avi_pkt_hb1 = tmp.bits.avi_pkt_hb1;
202 avi_header->bits.avi_pkt_hb0 = tmp.bits.avi_pkt_hb0;
203
204 return HI_SUCCESS;
205 }
206
hdmi_reg_avi_pkt0_low_get(avi_sub_pkt0_low * avi_pkt0_low)207 int hdmi_reg_avi_pkt0_low_get(avi_sub_pkt0_low *avi_pkt0_low)
208 {
209 hi_u32 *reg_addr = NULL;
210 avi_sub_pkt0_low tmp;
211
212 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt0l.u32);
213 tmp.u32 = hdmi_tx_reg_read(reg_addr);
214 avi_pkt0_low->bits.avi_sub_pkt0_pb3 = tmp.bits.avi_sub_pkt0_pb3;
215 avi_pkt0_low->bits.avi_sub_pkt0_pb2 = tmp.bits.avi_sub_pkt0_pb2;
216 avi_pkt0_low->bits.avi_sub_pkt0_pb1 = tmp.bits.avi_sub_pkt0_pb1;
217 avi_pkt0_low->bits.avi_sub_pkt0_pb0 = tmp.bits.avi_sub_pkt0_pb0;
218
219 return HI_SUCCESS;
220 }
221
hdmi_reg_avi_pkt0_high_get(avi_sub_pkt0_high * avi_pkt0_high)222 int hdmi_reg_avi_pkt0_high_get(avi_sub_pkt0_high *avi_pkt0_high)
223 {
224 hi_u32 *reg_addr = NULL;
225 avi_sub_pkt0_high tmp;
226
227 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt0h.u32);
228 tmp.u32 = hdmi_tx_reg_read(reg_addr);
229 avi_pkt0_high->bits.avi_sub_pkt0_pb6 = tmp.bits.avi_sub_pkt0_pb6;
230 avi_pkt0_high->bits.avi_sub_pkt0_pb5 = tmp.bits.avi_sub_pkt0_pb5;
231 avi_pkt0_high->bits.avi_sub_pkt0_pb4 = tmp.bits.avi_sub_pkt0_pb4;
232
233 return HI_SUCCESS;
234 }
235
hdmi_reg_avi_pkt1_low_get(avi_sub_pkt1_low * avi_pkt1_low)236 int hdmi_reg_avi_pkt1_low_get(avi_sub_pkt1_low *avi_pkt1_low)
237 {
238 hi_u32 *reg_addr = NULL;
239 avi_sub_pkt1_low tmp;
240
241 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt1l.u32);
242 tmp.u32 = hdmi_tx_reg_read(reg_addr);
243 avi_pkt1_low->bits.avi_sub_pkt1_pb3 = tmp.bits.avi_sub_pkt1_pb3;
244 avi_pkt1_low->bits.avi_sub_pkt1_pb2 = tmp.bits.avi_sub_pkt1_pb2;
245 avi_pkt1_low->bits.avi_sub_pkt1_pb1 = tmp.bits.avi_sub_pkt1_pb1;
246 avi_pkt1_low->bits.avi_sub_pkt1_pb0 = tmp.bits.avi_sub_pkt1_pb0;
247
248 return HI_SUCCESS;
249 }
250
hdmi_reg_avi_pkt1_high_get(avi_sub_pkt1_high * avi_pkt1_h)251 int hdmi_reg_avi_pkt1_high_get(avi_sub_pkt1_high *avi_pkt1_h)
252 {
253 hi_u32 *reg_addr = NULL;
254 avi_sub_pkt1_high tmp;
255
256 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt1h.u32);
257 tmp.u32 = hdmi_tx_reg_read(reg_addr);
258 avi_pkt1_h->bits.avi_sub_pkt1_pb6 = tmp.bits.avi_sub_pkt1_pb6;
259 avi_pkt1_h->bits.avi_sub_pkt1_pb5 = tmp.bits.avi_sub_pkt1_pb5;
260 avi_pkt1_h->bits.avi_sub_pkt1_pb4 = tmp.bits.avi_sub_pkt1_pb4;
261
262 return HI_SUCCESS;
263 }
264
hdmi_reg_avi_pkt2_low_get(avi_sub_pkt2_low * avi_pkt2_l)265 int hdmi_reg_avi_pkt2_low_get(avi_sub_pkt2_low *avi_pkt2_l)
266 {
267 hi_u32 *reg_addr = NULL;
268 avi_sub_pkt2_low tmp;
269
270 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt2l.u32);
271 tmp.u32 = hdmi_tx_reg_read(reg_addr);
272 avi_pkt2_l->bits.avi_sub_pkt2_pb3 = tmp.bits.avi_sub_pkt2_pb3;
273 avi_pkt2_l->bits.avi_sub_pkt2_pb2 = tmp.bits.avi_sub_pkt2_pb2;
274 avi_pkt2_l->bits.avi_sub_pkt2_pb1 = tmp.bits.avi_sub_pkt2_pb1;
275 avi_pkt2_l->bits.avi_sub_pkt2_pb0 = tmp.bits.avi_sub_pkt2_pb0;
276
277 return HI_SUCCESS;
278 }
279
hdmi_reg_avi_pkt2_high_get(avi_sub_pkt2_high * avi_pkt2_h)280 void hdmi_reg_avi_pkt2_high_get(avi_sub_pkt2_high *avi_pkt2_h)
281 {
282 hi_u32 *reg_addr = NULL;
283 avi_sub_pkt2_high tmp;
284
285 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt2h.u32);
286 tmp.u32 = hdmi_tx_reg_read(reg_addr);
287 avi_pkt2_h->bits.avi_sub_pkt2_pb6 = tmp.bits.avi_sub_pkt2_pb6;
288 avi_pkt2_h->bits.avi_sub_pkt2_pb5 = tmp.bits.avi_sub_pkt2_pb5;
289 avi_pkt2_h->bits.avi_sub_pkt2_pb4 = tmp.bits.avi_sub_pkt2_pb4;
290
291 return;
292 }
293
hdmi_reg_avi_pkt3_low_get(avi_sub_pkt3_low * avi_pkt3_low)294 void hdmi_reg_avi_pkt3_low_get(avi_sub_pkt3_low *avi_pkt3_low)
295 {
296 hi_u32 *reg_addr = NULL;
297 avi_sub_pkt3_low tmp;
298
299 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt3l.u32);
300 tmp.u32 = hdmi_tx_reg_read(reg_addr);
301 avi_pkt3_low->bits.avi_sub_pkt3_pb3 = tmp.bits.avi_sub_pkt3_pb3;
302 avi_pkt3_low->bits.avi_sub_pkt3_pb2 = tmp.bits.avi_sub_pkt3_pb2;
303 avi_pkt3_low->bits.avi_sub_pkt3_pb1 = tmp.bits.avi_sub_pkt3_pb1;
304 avi_pkt3_low->bits.avi_sub_pkt3_pb0 = tmp.bits.avi_sub_pkt3_pb0;
305
306 return;
307 }
308
hdmi_reg_avi_pkt3_high_get(avi_sub_pkt3_high * avi_pkt3_high)309 void hdmi_reg_avi_pkt3_high_get(avi_sub_pkt3_high *avi_pkt3_high)
310 {
311 hi_u32 *reg_addr = NULL;
312 avi_sub_pkt3_high tmp;
313
314 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_pkt3h.u32);
315 tmp.u32 = hdmi_tx_reg_read(reg_addr);
316 avi_pkt3_high->bits.avi_sub_pkt3_pb6 = tmp.bits.avi_sub_pkt3_pb6;
317 avi_pkt3_high->bits.avi_sub_pkt3_pb5 = tmp.bits.avi_sub_pkt3_pb5;
318 avi_pkt3_high->bits.avi_sub_pkt3_pb4 = tmp.bits.avi_sub_pkt3_pb4;
319
320 return;
321 }
322
hdmi_reg_audio_pkt_header_set(unsigned int hb0,unsigned int hb1,unsigned int hb2)323 int hdmi_reg_audio_pkt_header_set(unsigned int hb0, unsigned int hb1, unsigned int hb2)
324 {
325 hi_u32 *reg_addr = NULL;
326 aif_pkt_header tmp;
327
328 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt_head.u32);
329 tmp.u32 = hdmi_tx_reg_read(reg_addr);
330 tmp.bits.aif_pkt_hb2 = hb2;
331 tmp.bits.aif_pkt_hb1 = hb1;
332 tmp.bits.aif_pkt_hb0 = hb0;
333 hdmi_tx_reg_write(reg_addr, tmp.u32);
334
335 return HI_SUCCESS;
336 }
337
hdmi_reg_audio_pkt0_low_set(unsigned int audio_pkt0_pb0,unsigned int audio_pkt0_pb1,unsigned int audio_pkt0_pb2,unsigned int audio_pkt0_pb3)338 int hdmi_reg_audio_pkt0_low_set(unsigned int audio_pkt0_pb0,
339 unsigned int audio_pkt0_pb1, unsigned int audio_pkt0_pb2, unsigned int audio_pkt0_pb3)
340 {
341 hi_u32 *reg_addr = NULL;
342 aif_sub_pkt0_low tmp;
343
344 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt0l.u32);
345 tmp.u32 = hdmi_tx_reg_read(reg_addr);
346 tmp.bits.aif_sub_pkt0_pb3 = audio_pkt0_pb3;
347 tmp.bits.aif_sub_pkt0_pb2 = audio_pkt0_pb2;
348 tmp.bits.aif_sub_pkt0_pb1 = audio_pkt0_pb1;
349 tmp.bits.aif_sub_pkt0_pb0 = audio_pkt0_pb0;
350 hdmi_tx_reg_write(reg_addr, tmp.u32);
351
352 return HI_SUCCESS;
353 }
354
hdmi_reg_audio_pkt0_high_set(unsigned int audio_pkt0_pb4,unsigned int audio_pkt0_pb5,unsigned int audio_pkt0_pb6)355 int hdmi_reg_audio_pkt0_high_set(unsigned int audio_pkt0_pb4,
356 unsigned int audio_pkt0_pb5, unsigned int audio_pkt0_pb6)
357 {
358 hi_u32 *reg_addr = NULL;
359 aif_sub_pkt0_high tmp;
360
361 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt0h.u32);
362 tmp.u32 = hdmi_tx_reg_read(reg_addr);
363 tmp.bits.aif_sub_pkt0_pb6 = audio_pkt0_pb6;
364 tmp.bits.aif_sub_pkt0_pb5 = audio_pkt0_pb5;
365 tmp.bits.aif_sub_pkt0_pb4 = audio_pkt0_pb4;
366 hdmi_tx_reg_write(reg_addr, tmp.u32);
367
368 return HI_SUCCESS;
369 }
370
hdmi_reg_audio_pkt1_low_set(unsigned int audio_pkt1_pb0,unsigned int audio_pkt1_pb1,unsigned int audio_pkt1_pb2,unsigned int audio_pkt1_pb3)371 int hdmi_reg_audio_pkt1_low_set(unsigned int audio_pkt1_pb0,
372 unsigned int audio_pkt1_pb1, unsigned int audio_pkt1_pb2, unsigned int audio_pkt1_pb3)
373 {
374 hi_u32 *reg_addr = NULL;
375 aif_sub_pkt1_low tmp;
376
377 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt1l.u32);
378 tmp.u32 = hdmi_tx_reg_read(reg_addr);
379 tmp.bits.aif_sub_pkt1_pb3 = audio_pkt1_pb3;
380 tmp.bits.aif_sub_pkt1_pb2 = audio_pkt1_pb2;
381 tmp.bits.aif_sub_pkt1_pb1 = audio_pkt1_pb1;
382 tmp.bits.aif_sub_pkt1_pb0 = audio_pkt1_pb0;
383 hdmi_tx_reg_write(reg_addr, tmp.u32);
384
385 return HI_SUCCESS;
386 }
387
hdmi_reg_audio_pkt1_high_set(unsigned int audio_pkt1_pb4,unsigned int audio_pkt1_pb5,unsigned int audio_pkt1_pb6)388 int hdmi_reg_audio_pkt1_high_set(unsigned int audio_pkt1_pb4,
389 unsigned int audio_pkt1_pb5, unsigned int audio_pkt1_pb6)
390 {
391 hi_u32 *reg_addr = NULL;
392 aif_sub_pkt1_high tmp;
393
394 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt1h.u32);
395 tmp.u32 = hdmi_tx_reg_read(reg_addr);
396 tmp.bits.aif_sub_pkt1_pb6 = audio_pkt1_pb6;
397 tmp.bits.aif_sub_pkt1_pb5 = audio_pkt1_pb5;
398 tmp.bits.aif_sub_pkt1_pb4 = audio_pkt1_pb4;
399 hdmi_tx_reg_write(reg_addr, tmp.u32);
400
401 return HI_SUCCESS;
402 }
403
hdmi_reg_audio_pkt2_low_set(unsigned int audio_pkt2_pb0,unsigned int audio_pkt2_pb1,unsigned int audio_pkt2_pb2,unsigned int audio_pkt2_pb3)404 int hdmi_reg_audio_pkt2_low_set(unsigned int audio_pkt2_pb0,
405 unsigned int audio_pkt2_pb1, unsigned int audio_pkt2_pb2, unsigned int audio_pkt2_pb3)
406 {
407 hi_u32 *reg_addr = NULL;
408 aif_sub_pkt2_low tmp;
409
410 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt2l.u32);
411 tmp.u32 = hdmi_tx_reg_read(reg_addr);
412 tmp.bits.aif_sub_pkt2_pb3 = audio_pkt2_pb3;
413 tmp.bits.aif_sub_pkt2_pb2 = audio_pkt2_pb2;
414 tmp.bits.aif_sub_pkt2_pb1 = audio_pkt2_pb1;
415 tmp.bits.aif_sub_pkt2_pb0 = audio_pkt2_pb0;
416 hdmi_tx_reg_write(reg_addr, tmp.u32);
417
418 return HI_SUCCESS;
419 }
420
hdmi_reg_audio_pkt2_high_set(unsigned int audio_pkt2_pb4,unsigned int audio_pkt2_pb5,unsigned int audio_pkt2_pb6)421 int hdmi_reg_audio_pkt2_high_set(unsigned int audio_pkt2_pb4,
422 unsigned int audio_pkt2_pb5, unsigned int audio_pkt2_pb6)
423 {
424 hi_u32 *reg_addr = NULL;
425 aif_sub_pkt2_high tmp;
426
427 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt2h.u32);
428 tmp.u32 = hdmi_tx_reg_read(reg_addr);
429 tmp.bits.aif_sub_pkt2_pb6 = audio_pkt2_pb6;
430 tmp.bits.aif_sub_pkt2_pb5 = audio_pkt2_pb5;
431 tmp.bits.aif_sub_pkt2_pb4 = audio_pkt2_pb4;
432 hdmi_tx_reg_write(reg_addr, tmp.u32);
433
434 return HI_SUCCESS;
435 }
436
hdmi_reg_audio_pkt3_low_set(unsigned int audio_pkt3_pb0,unsigned int audio_pkt3_pb1,unsigned int audio_pkt3_pb2,unsigned int audio_pkt3_pb3)437 int hdmi_reg_audio_pkt3_low_set(unsigned int audio_pkt3_pb0,
438 unsigned int audio_pkt3_pb1, unsigned int audio_pkt3_pb2, unsigned int audio_pkt3_pb3)
439 {
440 hi_u32 *reg_addr = NULL;
441 aif_sub_pkt3_low tmp;
442
443 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt3l.u32);
444 tmp.u32 = hdmi_tx_reg_read(reg_addr);
445 tmp.bits.aif_sub_pkt3_pb3 = audio_pkt3_pb3;
446 tmp.bits.aif_sub_pkt3_pb2 = audio_pkt3_pb2;
447 tmp.bits.aif_sub_pkt3_pb1 = audio_pkt3_pb1;
448 tmp.bits.aif_sub_pkt3_pb0 = audio_pkt3_pb0;
449 hdmi_tx_reg_write(reg_addr, tmp.u32);
450
451 return HI_SUCCESS;
452 }
453
hdmi_reg_audio_pkt3_high_set(unsigned int audio_pkt3_pb4,unsigned int audio_pkt3_pb5,unsigned int audio_pkt3_pb6)454 int hdmi_reg_audio_pkt3_high_set(unsigned int audio_pkt3_pb4,
455 unsigned int audio_pkt3_pb5, unsigned int audio_pkt3_pb6)
456 {
457 hi_u32 *reg_addr = NULL;
458 aif_sub_pkt3_high tmp;
459
460 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt3h.u32);
461 tmp.u32 = hdmi_tx_reg_read(reg_addr);
462 tmp.bits.aif_sub_pkt3_pb6 = audio_pkt3_pb6;
463 tmp.bits.aif_sub_pkt3_pb5 = audio_pkt3_pb5;
464 tmp.bits.aif_sub_pkt3_pb4 = audio_pkt3_pb4;
465 hdmi_tx_reg_write(reg_addr, tmp.u32);
466
467 return HI_SUCCESS;
468 }
469
hdmi_reg_aif_pkt_header_get(aif_pkt_header * aif_header)470 int hdmi_reg_aif_pkt_header_get(aif_pkt_header *aif_header)
471 {
472 hi_u32 *reg_addr = NULL;
473 aif_pkt_header tmp;
474
475 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt_head.u32);
476 tmp.u32 = hdmi_tx_reg_read(reg_addr);
477 aif_header->bits.aif_pkt_hb2 = tmp.bits.aif_pkt_hb2;
478 aif_header->bits.aif_pkt_hb1 = tmp.bits.aif_pkt_hb1;
479 aif_header->bits.aif_pkt_hb0 = tmp.bits.aif_pkt_hb0;
480
481 return HI_SUCCESS;
482 }
483
hdmi_reg_aif_pkt0_low_get(aif_sub_pkt0_low * aif_pkt0_low)484 int hdmi_reg_aif_pkt0_low_get(aif_sub_pkt0_low *aif_pkt0_low)
485 {
486 hi_u32 *reg_addr = NULL;
487 aif_sub_pkt0_low tmp;
488
489 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt0l.u32);
490 tmp.u32 = hdmi_tx_reg_read(reg_addr);
491 aif_pkt0_low->bits.aif_sub_pkt0_pb3 = tmp.bits.aif_sub_pkt0_pb3;
492 aif_pkt0_low->bits.aif_sub_pkt0_pb2 = tmp.bits.aif_sub_pkt0_pb2;
493 aif_pkt0_low->bits.aif_sub_pkt0_pb1 = tmp.bits.aif_sub_pkt0_pb1;
494 aif_pkt0_low->bits.aif_sub_pkt0_pb0 = tmp.bits.aif_sub_pkt0_pb0;
495
496 return HI_SUCCESS;
497 }
498
hdmi_reg_aif_pkt0_high_get(aif_sub_pkt0_high * aif_pkt0_high)499 int hdmi_reg_aif_pkt0_high_get(aif_sub_pkt0_high *aif_pkt0_high)
500 {
501 hi_u32 *reg_addr = NULL;
502 aif_sub_pkt0_high tmp;
503
504 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt0h.u32);
505 tmp.u32 = hdmi_tx_reg_read(reg_addr);
506 aif_pkt0_high->bits.aif_sub_pkt0_pb6 = tmp.bits.aif_sub_pkt0_pb6;
507 aif_pkt0_high->bits.aif_sub_pkt0_pb5 = tmp.bits.aif_sub_pkt0_pb5;
508 aif_pkt0_high->bits.aif_sub_pkt0_pb4 = tmp.bits.aif_sub_pkt0_pb4;
509
510 return HI_SUCCESS;
511 }
512
hdmi_reg_aif_pkt1_low_get(aif_sub_pkt1_low * aif_pkt1_low)513 int hdmi_reg_aif_pkt1_low_get(aif_sub_pkt1_low *aif_pkt1_low)
514 {
515 hi_u32 *reg_addr = NULL;
516 aif_sub_pkt1_low tmp;
517
518 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt1l.u32);
519 tmp.u32 = hdmi_tx_reg_read(reg_addr);
520 aif_pkt1_low->bits.aif_sub_pkt1_pb3 = tmp.bits.aif_sub_pkt1_pb3;
521 aif_pkt1_low->bits.aif_sub_pkt1_pb2 = tmp.bits.aif_sub_pkt1_pb2;
522 aif_pkt1_low->bits.aif_sub_pkt1_pb1 = tmp.bits.aif_sub_pkt1_pb1;
523 aif_pkt1_low->bits.aif_sub_pkt1_pb0 = tmp.bits.aif_sub_pkt1_pb0;
524
525 return HI_SUCCESS;
526 }
527
hdmi_reg_aif_pkt1_high_get(aif_sub_pkt1_high * aif_pkt1_high)528 int hdmi_reg_aif_pkt1_high_get(aif_sub_pkt1_high *aif_pkt1_high)
529 {
530 hi_u32 *reg_addr = NULL;
531 aif_sub_pkt1_high tmp;
532
533 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt1h.u32);
534 tmp.u32 = hdmi_tx_reg_read(reg_addr);
535 aif_pkt1_high->bits.aif_sub_pkt1_pb6 = tmp.bits.aif_sub_pkt1_pb6;
536 aif_pkt1_high->bits.aif_sub_pkt1_pb5 = tmp.bits.aif_sub_pkt1_pb5;
537 aif_pkt1_high->bits.aif_sub_pkt1_pb4 = tmp.bits.aif_sub_pkt1_pb4;
538
539 return HI_SUCCESS;
540 }
541
hdmi_reg_aif_pkt2_low_get(aif_sub_pkt2_low * aif_pkt2_low)542 int hdmi_reg_aif_pkt2_low_get(aif_sub_pkt2_low *aif_pkt2_low)
543 {
544 hi_u32 *reg_addr = NULL;
545 aif_sub_pkt2_low tmp;
546
547 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt2l.u32);
548 tmp.u32 = hdmi_tx_reg_read(reg_addr);
549 aif_pkt2_low->bits.aif_sub_pkt2_pb3 = tmp.bits.aif_sub_pkt2_pb3;
550 aif_pkt2_low->bits.aif_sub_pkt2_pb2 = tmp.bits.aif_sub_pkt2_pb2;
551 aif_pkt2_low->bits.aif_sub_pkt2_pb1 = tmp.bits.aif_sub_pkt2_pb1;
552 aif_pkt2_low->bits.aif_sub_pkt2_pb0 = tmp.bits.aif_sub_pkt2_pb0;
553
554 return HI_SUCCESS;
555 }
556
hdmi_reg_aif_pkt2_high_get(aif_sub_pkt2_high * aif_pkt2_high)557 int hdmi_reg_aif_pkt2_high_get(aif_sub_pkt2_high *aif_pkt2_high)
558 {
559 hi_u32 *reg_addr = NULL;
560 aif_sub_pkt2_high tmp;
561
562 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt2h.u32);
563 tmp.u32 = hdmi_tx_reg_read(reg_addr);
564 aif_pkt2_high->bits.aif_sub_pkt2_pb6 = tmp.bits.aif_sub_pkt2_pb6;
565 aif_pkt2_high->bits.aif_sub_pkt2_pb5 = tmp.bits.aif_sub_pkt2_pb5;
566 aif_pkt2_high->bits.aif_sub_pkt2_pb4 = tmp.bits.aif_sub_pkt2_pb4;
567
568 return HI_SUCCESS;
569 }
570
hdmi_reg_aif_pkt3_low_get(aif_sub_pkt3_low * aif_pkt3_low)571 int hdmi_reg_aif_pkt3_low_get(aif_sub_pkt3_low *aif_pkt3_low)
572 {
573 hi_u32 *reg_addr = NULL;
574 aif_sub_pkt3_low tmp;
575
576 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt3l.u32);
577 tmp.u32 = hdmi_tx_reg_read(reg_addr);
578 aif_pkt3_low->bits.aif_sub_pkt3_pb3 = tmp.bits.aif_sub_pkt3_pb3;
579 aif_pkt3_low->bits.aif_sub_pkt3_pb2 = tmp.bits.aif_sub_pkt3_pb2;
580 aif_pkt3_low->bits.aif_sub_pkt3_pb1 = tmp.bits.aif_sub_pkt3_pb1;
581 aif_pkt3_low->bits.aif_sub_pkt3_pb0 = tmp.bits.aif_sub_pkt3_pb0;
582
583 return HI_SUCCESS;
584 }
585
hdmi_reg_aif_pkt3_high_get(aif_sub_pkt3_high * aif_pkt3_high)586 int hdmi_reg_aif_pkt3_high_get(aif_sub_pkt3_high *aif_pkt3_high)
587 {
588 hi_u32 *reg_addr = NULL;
589 aif_sub_pkt3_high tmp;
590
591 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aif_pkt3h.u32);
592 tmp.u32 = hdmi_tx_reg_read(reg_addr);
593 aif_pkt3_high->bits.aif_sub_pkt3_pb6 = tmp.bits.aif_sub_pkt3_pb6;
594 aif_pkt3_high->bits.aif_sub_pkt3_pb5 = tmp.bits.aif_sub_pkt3_pb5;
595 aif_pkt3_high->bits.aif_sub_pkt3_pb4 = tmp.bits.aif_sub_pkt3_pb4;
596
597 return HI_SUCCESS;
598 }
599
hdmi_reg_gen_pkt_header_set(unsigned int hb0,unsigned int hb1,unsigned int hb2)600 int hdmi_reg_gen_pkt_header_set(unsigned int hb0, unsigned int hb1, unsigned int hb2)
601 {
602 hi_u32 *reg_addr = NULL;
603 gen_pkt_header tmp;
604
605 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt_head.u32);
606 tmp.u32 = hdmi_tx_reg_read(reg_addr);
607 tmp.bits.gen_pkt_hb2 = hb2;
608 tmp.bits.gen_pkt_hb1 = hb1;
609 tmp.bits.gen_pkt_hb0 = hb0;
610 hdmi_tx_reg_write(reg_addr, tmp.u32);
611
612 return HI_SUCCESS;
613 }
614
hdmi_reg_gen_pkt0_low_set(unsigned int gen_pkt0_pb0,unsigned int gen_pkt0_pb1,unsigned int gen_pkt0_pb2,unsigned int gen_pkt0_pb3)615 int hdmi_reg_gen_pkt0_low_set(unsigned int gen_pkt0_pb0,
616 unsigned int gen_pkt0_pb1, unsigned int gen_pkt0_pb2, unsigned int gen_pkt0_pb3)
617 {
618 hi_u32 *reg_addr = NULL;
619 gen_sub_pkt0_low tmp;
620
621 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt0l.u32);
622 tmp.u32 = hdmi_tx_reg_read(reg_addr);
623 tmp.bits.gen_sub_pkt0_pb3 = gen_pkt0_pb3;
624 tmp.bits.gen_sub_pkt0_pb2 = gen_pkt0_pb2;
625 tmp.bits.gen_sub_pkt0_pb1 = gen_pkt0_pb1;
626 tmp.bits.gen_sub_pkt0_pb0 = gen_pkt0_pb0;
627 hdmi_tx_reg_write(reg_addr, tmp.u32);
628
629 return HI_SUCCESS;
630 }
631
hdmi_reg_gen_pkt0_high_set(unsigned int gen_pkt0_pb4,unsigned int gen_pkt0_pb5,unsigned int gen_pkt0_pb6)632 int hdmi_reg_gen_pkt0_high_set(unsigned int gen_pkt0_pb4, unsigned int gen_pkt0_pb5, unsigned int gen_pkt0_pb6)
633 {
634 hi_u32 *reg_addr = NULL;
635 gen_sub_pkt0_high tmp;
636
637 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt0h.u32);
638 tmp.u32 = hdmi_tx_reg_read(reg_addr);
639 tmp.bits.gen_sub_pkt0_pb6 = gen_pkt0_pb6;
640 tmp.bits.gen_sub_pkt0_pb5 = gen_pkt0_pb5;
641 tmp.bits.gen_sub_pkt0_pb4 = gen_pkt0_pb4;
642 hdmi_tx_reg_write(reg_addr, tmp.u32);
643
644 return HI_SUCCESS;
645 }
646
hdmi_reg_gen_pkt1_low_set(unsigned int gen_pkt1_pb0,unsigned int gen_pkt1_pb1,unsigned int gen_pkt1_pb2,unsigned int gen_pkt1_pb3)647 int hdmi_reg_gen_pkt1_low_set(unsigned int gen_pkt1_pb0,
648 unsigned int gen_pkt1_pb1, unsigned int gen_pkt1_pb2, unsigned int gen_pkt1_pb3)
649 {
650 hi_u32 *reg_addr = NULL;
651 gen_sub_pkt1_low tmp;
652
653 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt1l.u32);
654 tmp.u32 = hdmi_tx_reg_read(reg_addr);
655 tmp.bits.gen_sub_pkt1_pb3 = gen_pkt1_pb3;
656 tmp.bits.gen_sub_pkt1_pb2 = gen_pkt1_pb2;
657 tmp.bits.gen_sub_pkt1_pb1 = gen_pkt1_pb1;
658 tmp.bits.gen_sub_pkt1_pb0 = gen_pkt1_pb0;
659 hdmi_tx_reg_write(reg_addr, tmp.u32);
660
661 return HI_SUCCESS;
662 }
663
hdmi_reg_gen_pkt1_high_set(unsigned int gen_pkt1_pb4,unsigned int gen_pkt1_pb5,unsigned int gen_pkt1_pb6)664 int hdmi_reg_gen_pkt1_high_set(unsigned int gen_pkt1_pb4, unsigned int gen_pkt1_pb5, unsigned int gen_pkt1_pb6)
665 {
666 hi_u32 *reg_addr = NULL;
667 gen_sub_pkt1_high tmp;
668
669 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt1h.u32);
670 tmp.u32 = hdmi_tx_reg_read(reg_addr);
671 tmp.bits.gen_sub_pkt1_pb6 = gen_pkt1_pb6;
672 tmp.bits.gen_sub_pkt1_pb5 = gen_pkt1_pb5;
673 tmp.bits.gen_sub_pkt1_pb4 = gen_pkt1_pb4;
674 hdmi_tx_reg_write(reg_addr, tmp.u32);
675
676 return HI_SUCCESS;
677 }
678
hdmi_reg_gen_pkt2_low_set(unsigned int gen_pkt2_pb0,unsigned int gen_pkt2_pb1,unsigned int gen_pkt2_pb2,unsigned int gen_pkt2_pb3)679 int hdmi_reg_gen_pkt2_low_set(unsigned int gen_pkt2_pb0,
680 unsigned int gen_pkt2_pb1, unsigned int gen_pkt2_pb2, unsigned int gen_pkt2_pb3)
681 {
682 hi_u32 *reg_addr = NULL;
683 gen_sub_pkt2_low tmp;
684
685 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt2l.u32);
686 tmp.u32 = hdmi_tx_reg_read(reg_addr);
687 tmp.bits.gen_sub_pkt2_pb3 = gen_pkt2_pb3;
688 tmp.bits.gen_sub_pkt2_pb2 = gen_pkt2_pb2;
689 tmp.bits.gen_sub_pkt2_pb1 = gen_pkt2_pb1;
690 tmp.bits.gen_sub_pkt2_pb0 = gen_pkt2_pb0;
691 hdmi_tx_reg_write(reg_addr, tmp.u32);
692
693 return HI_SUCCESS;
694 }
695
hdmi_reg_gen_pkt2_high_set(unsigned int gen_pkt2_pb4,unsigned int gen_pkt2_pb5,unsigned int gen_pkt2_pb6)696 int hdmi_reg_gen_pkt2_high_set(unsigned int gen_pkt2_pb4, unsigned int gen_pkt2_pb5, unsigned int gen_pkt2_pb6)
697 {
698 hi_u32 *reg_addr = NULL;
699 gen_sub_pkt2_high tmp;
700
701 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt2h.u32);
702 tmp.u32 = hdmi_tx_reg_read(reg_addr);
703 tmp.bits.gen_sub_pkt2_pb6 = gen_pkt2_pb6;
704 tmp.bits.gen_sub_pkt2_pb5 = gen_pkt2_pb5;
705 tmp.bits.gen_sub_pkt2_pb4 = gen_pkt2_pb4;
706 hdmi_tx_reg_write(reg_addr, tmp.u32);
707
708 return HI_SUCCESS;
709 }
710
hdmi_reg_gen_pkt3_low_set(unsigned int gen_pkt3_pb0,unsigned int gen_pkt3_pb1,unsigned int gen_pkt3_pb2,unsigned int gen_pkt3_pb3)711 int hdmi_reg_gen_pkt3_low_set(unsigned int gen_pkt3_pb0,
712 unsigned int gen_pkt3_pb1, unsigned int gen_pkt3_pb2, unsigned int gen_pkt3_pb3)
713 {
714 hi_u32 *reg_addr = NULL;
715 gen_sub_pkt3_low tmp;
716
717 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt3l.u32);
718 tmp.u32 = hdmi_tx_reg_read(reg_addr);
719 tmp.bits.gen_sub_pkt3_pb3 = gen_pkt3_pb3;
720 tmp.bits.gen_sub_pkt3_pb2 = gen_pkt3_pb2;
721 tmp.bits.gen_sub_pkt3_pb1 = gen_pkt3_pb1;
722 tmp.bits.gen_sub_pkt3_pb0 = gen_pkt3_pb0;
723 hdmi_tx_reg_write(reg_addr, tmp.u32);
724
725 return HI_SUCCESS;
726 }
727
hdmi_reg_gen_pkt3_high_set(unsigned int gen_pkt3_pb4,unsigned int gen_pkt3_pb5,unsigned int gen_pkt3_pb6)728 int hdmi_reg_gen_pkt3_high_set(unsigned int gen_pkt3_pb4, unsigned int gen_pkt3_pb5, unsigned int gen_pkt3_pb6)
729 {
730 hi_u32 *reg_addr = NULL;
731 gen_sub_pkt3_high tmp;
732
733 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt3h.u32);
734 tmp.u32 = hdmi_tx_reg_read(reg_addr);
735 tmp.bits.gen_sub_pkt3_pb6 = gen_pkt3_pb6;
736 tmp.bits.gen_sub_pkt3_pb5 = gen_pkt3_pb5;
737 tmp.bits.gen_sub_pkt3_pb4 = gen_pkt3_pb4;
738 hdmi_tx_reg_write(reg_addr, tmp.u32);
739
740 return HI_SUCCESS;
741 }
742
hdmi_reg_gen_pkt_header_get(gen_pkt_header * gen_header)743 int hdmi_reg_gen_pkt_header_get(gen_pkt_header *gen_header)
744 {
745 hi_u32 *reg_addr = NULL;
746 gen_pkt_header tmp;
747
748 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt_head.u32);
749 tmp.u32 = hdmi_tx_reg_read(reg_addr);
750 gen_header->bits.gen_pkt_hb2 = tmp.bits.gen_pkt_hb2;
751 gen_header->bits.gen_pkt_hb1 = tmp.bits.gen_pkt_hb1;
752 gen_header->bits.gen_pkt_hb0 = tmp.bits.gen_pkt_hb0;
753
754 return HI_SUCCESS;
755 }
756
hdmi_reg_gen_pkt0_low_get(gen_sub_pkt0_low * gen_pkt0_low)757 int hdmi_reg_gen_pkt0_low_get(gen_sub_pkt0_low *gen_pkt0_low)
758 {
759 hi_u32 *reg_addr = NULL;
760 gen_sub_pkt0_low tmp;
761
762 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt0l.u32);
763 tmp.u32 = hdmi_tx_reg_read(reg_addr);
764 gen_pkt0_low->bits.gen_sub_pkt0_pb3 = tmp.bits.gen_sub_pkt0_pb3;
765 gen_pkt0_low->bits.gen_sub_pkt0_pb2 = tmp.bits.gen_sub_pkt0_pb2;
766 gen_pkt0_low->bits.gen_sub_pkt0_pb1 = tmp.bits.gen_sub_pkt0_pb1;
767 gen_pkt0_low->bits.gen_sub_pkt0_pb0 = tmp.bits.gen_sub_pkt0_pb0;
768
769 return HI_SUCCESS;
770 }
771
hdmi_reg_gen_pkt0_high_get(gen_sub_pkt0_high * gen_pkt0_high)772 int hdmi_reg_gen_pkt0_high_get(gen_sub_pkt0_high *gen_pkt0_high)
773 {
774 hi_u32 *reg_addr = NULL;
775 gen_sub_pkt0_high tmp;
776
777 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt0h.u32);
778 tmp.u32 = hdmi_tx_reg_read(reg_addr);
779 gen_pkt0_high->bits.gen_sub_pkt0_pb6 = tmp.bits.gen_sub_pkt0_pb6;
780 gen_pkt0_high->bits.gen_sub_pkt0_pb5 = tmp.bits.gen_sub_pkt0_pb5;
781 gen_pkt0_high->bits.gen_sub_pkt0_pb4 = tmp.bits.gen_sub_pkt0_pb4;
782
783 return HI_SUCCESS;
784 }
785
hdmi_reg_gen_pkt1_low_get(gen_sub_pkt1_low * gen_pkt1_low)786 int hdmi_reg_gen_pkt1_low_get(gen_sub_pkt1_low *gen_pkt1_low)
787 {
788 hi_u32 *reg_addr = NULL;
789 gen_sub_pkt1_low tmp;
790
791 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt1l.u32);
792 tmp.u32 = hdmi_tx_reg_read(reg_addr);
793 gen_pkt1_low->bits.gen_sub_pkt1_pb3 = tmp.bits.gen_sub_pkt1_pb3;
794 gen_pkt1_low->bits.gen_sub_pkt1_pb2 = tmp.bits.gen_sub_pkt1_pb2;
795 gen_pkt1_low->bits.gen_sub_pkt1_pb1 = tmp.bits.gen_sub_pkt1_pb1;
796 gen_pkt1_low->bits.gen_sub_pkt1_pb0 = tmp.bits.gen_sub_pkt1_pb0;
797
798 return HI_SUCCESS;
799 }
800
hdmi_reg_gen_pkt1_high_get(gen_sub_pkt1_high * gen_pkt1_high)801 int hdmi_reg_gen_pkt1_high_get(gen_sub_pkt1_high *gen_pkt1_high)
802 {
803 hi_u32 *reg_addr = NULL;
804 gen_sub_pkt1_high tmp;
805
806 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt1h.u32);
807 tmp.u32 = hdmi_tx_reg_read(reg_addr);
808 gen_pkt1_high->bits.gen_sub_pkt1_pb6 = tmp.bits.gen_sub_pkt1_pb6;
809 gen_pkt1_high->bits.gen_sub_pkt1_pb5 = tmp.bits.gen_sub_pkt1_pb5;
810 gen_pkt1_high->bits.gen_sub_pkt1_pb4 = tmp.bits.gen_sub_pkt1_pb4;
811
812 return HI_SUCCESS;
813 }
814
hdmi_reg_gen_pkt2_low_get(gen_sub_pkt2_low * gen_pkt2_low)815 int hdmi_reg_gen_pkt2_low_get(gen_sub_pkt2_low *gen_pkt2_low)
816 {
817 hi_u32 *reg_addr = NULL;
818 gen_sub_pkt2_low tmp;
819
820 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt2l.u32);
821 tmp.u32 = hdmi_tx_reg_read(reg_addr);
822 gen_pkt2_low->bits.gen_sub_pkt2_pb3 = tmp.bits.gen_sub_pkt2_pb3;
823 gen_pkt2_low->bits.gen_sub_pkt2_pb2 = tmp.bits.gen_sub_pkt2_pb2;
824 gen_pkt2_low->bits.gen_sub_pkt2_pb1 = tmp.bits.gen_sub_pkt2_pb1;
825 gen_pkt2_low->bits.gen_sub_pkt2_pb0 = tmp.bits.gen_sub_pkt2_pb0;
826
827 return HI_SUCCESS;
828 }
829
hdmi_reg_gen_pkt2_high_get(gen_sub_pkt2_high * gen_pkt2_high)830 int hdmi_reg_gen_pkt2_high_get(gen_sub_pkt2_high *gen_pkt2_high)
831 {
832 hi_u32 *reg_addr = NULL;
833 gen_sub_pkt2_high tmp;
834
835 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt2h.u32);
836 tmp.u32 = hdmi_tx_reg_read(reg_addr);
837 gen_pkt2_high->bits.gen_sub_pkt2_pb6 = tmp.bits.gen_sub_pkt2_pb6;
838 gen_pkt2_high->bits.gen_sub_pkt2_pb5 = tmp.bits.gen_sub_pkt2_pb5;
839 gen_pkt2_high->bits.gen_sub_pkt2_pb4 = tmp.bits.gen_sub_pkt2_pb4;
840
841 return HI_SUCCESS;
842 }
843
hdmi_reg_gen_pkt3_low_get(gen_sub_pkt3_low * gen_pkt3_low)844 int hdmi_reg_gen_pkt3_low_get(gen_sub_pkt3_low *gen_pkt3_low)
845 {
846 hi_u32 *reg_addr = NULL;
847 gen_sub_pkt3_low tmp;
848
849 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt3l.u32);
850 tmp.u32 = hdmi_tx_reg_read(reg_addr);
851 gen_pkt3_low->bits.gen_sub_pkt3_pb3 = tmp.bits.gen_sub_pkt3_pb3;
852 gen_pkt3_low->bits.gen_sub_pkt3_pb2 = tmp.bits.gen_sub_pkt3_pb2;
853 gen_pkt3_low->bits.gen_sub_pkt3_pb1 = tmp.bits.gen_sub_pkt3_pb1;
854 gen_pkt3_low->bits.gen_sub_pkt3_pb0 = tmp.bits.gen_sub_pkt3_pb0;
855
856 return HI_SUCCESS;
857 }
858
hdmi_reg_gen_pkt3_high_get(gen_sub_pkt3_high * gen_pkt3_high)859 int hdmi_reg_gen_pkt3_high_get(gen_sub_pkt3_high *gen_pkt3_high)
860 {
861 hi_u32 *reg_addr = NULL;
862 gen_sub_pkt3_high tmp;
863
864 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_pkt3h.u32);
865 tmp.u32 = hdmi_tx_reg_read(reg_addr);
866 gen_pkt3_high->bits.gen_sub_pkt3_pb6 = tmp.bits.gen_sub_pkt3_pb6;
867 gen_pkt3_high->bits.gen_sub_pkt3_pb5 = tmp.bits.gen_sub_pkt3_pb5;
868 gen_pkt3_high->bits.gen_sub_pkt3_pb4 = tmp.bits.gen_sub_pkt3_pb4;
869
870 return HI_SUCCESS;
871 }
872
hdmi_reg_gamut_pkt_header_get(gamut_pkt_header * gamut_header)873 int hdmi_reg_gamut_pkt_header_get(gamut_pkt_header *gamut_header)
874 {
875 hi_u32 *reg_addr = NULL;
876 gamut_pkt_header tmp;
877
878 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gamut_pkt_head.u32);
879 tmp.u32 = hdmi_tx_reg_read(reg_addr);
880 gamut_header->bits.gamut_pkt_hb2 = tmp.bits.gamut_pkt_hb2;
881 gamut_header->bits.gamut_pkt_hb1 = tmp.bits.gamut_pkt_hb1;
882 gamut_header->bits.gamut_pkt_hb0 = tmp.bits.gamut_pkt_hb0;
883
884 return HI_SUCCESS;
885 }
886
hdmi_reg_gamut_pkt0_low_get(gamut_sub_pkt0_low * gamut_pkt0_low)887 int hdmi_reg_gamut_pkt0_low_get(gamut_sub_pkt0_low *gamut_pkt0_low)
888 {
889 hi_u32 *reg_addr = NULL;
890 gamut_sub_pkt0_low tmp;
891
892 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gamut_pkt0l.u32);
893 tmp.u32 = hdmi_tx_reg_read(reg_addr);
894 gamut_pkt0_low->bits.gamut_sub_pkt0_pb3 = tmp.bits.gamut_sub_pkt0_pb3;
895 gamut_pkt0_low->bits.gamut_sub_pkt0_pb2 = tmp.bits.gamut_sub_pkt0_pb2;
896 gamut_pkt0_low->bits.gamut_sub_pkt0_pb1 = tmp.bits.gamut_sub_pkt0_pb1;
897 gamut_pkt0_low->bits.gamut_sub_pkt0_pb0 = tmp.bits.gamut_sub_pkt0_pb0;
898
899 return HI_SUCCESS;
900 }
901
hdmi_reg_gamut_pkt0_high_get(gamut_sub_pkt0_high * gamut_pkt0_high)902 int hdmi_reg_gamut_pkt0_high_get(gamut_sub_pkt0_high *gamut_pkt0_high)
903 {
904 hi_u32 *reg_addr = NULL;
905 gamut_sub_pkt0_high tmp;
906
907 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gamut_pkt0h.u32);
908 tmp.u32 = hdmi_tx_reg_read(reg_addr);
909 gamut_pkt0_high->bits.gamut_sub_pkt0_pb6 = tmp.bits.gamut_sub_pkt0_pb6;
910 gamut_pkt0_high->bits.gamut_sub_pkt0_pb5 = tmp.bits.gamut_sub_pkt0_pb5;
911 gamut_pkt0_high->bits.gamut_sub_pkt0_pb4 = tmp.bits.gamut_sub_pkt0_pb4;
912
913 return HI_SUCCESS;
914 }
915
hdmi_reg_gamut_pkt1_low_get(gamut_sub_pkt1_low * gamut_pkt1_low)916 int hdmi_reg_gamut_pkt1_low_get(gamut_sub_pkt1_low *gamut_pkt1_low)
917 {
918 hi_u32 *reg_addr = NULL;
919 gamut_sub_pkt1_low tmp;
920
921 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gamut_pkt1l.u32);
922 tmp.u32 = hdmi_tx_reg_read(reg_addr);
923 gamut_pkt1_low->bits.gamut_sub_pkt1_pb3 = tmp.bits.gamut_sub_pkt1_pb3;
924 gamut_pkt1_low->bits.gamut_sub_pkt1_pb2 = tmp.bits.gamut_sub_pkt1_pb2;
925 gamut_pkt1_low->bits.gamut_sub_pkt1_pb1 = tmp.bits.gamut_sub_pkt1_pb1;
926 gamut_pkt1_low->bits.gamut_sub_pkt1_pb0 = tmp.bits.gamut_sub_pkt1_pb0;
927
928 return HI_SUCCESS;
929 }
930
hdmi_reg_gamut_pkt1_high_get(gamut_sub_pkt1_high * gamut_pkt1_high)931 int hdmi_reg_gamut_pkt1_high_get(gamut_sub_pkt1_high *gamut_pkt1_high)
932 {
933 hi_u32 *reg_addr = NULL;
934 gamut_sub_pkt1_high tmp;
935
936 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gamut_pkt1h.u32);
937 tmp.u32 = hdmi_tx_reg_read(reg_addr);
938 gamut_pkt1_high->bits.gamut_sub_pkt1_pb6 = tmp.bits.gamut_sub_pkt1_pb6;
939 gamut_pkt1_high->bits.gamut_sub_pkt1_pb5 = tmp.bits.gamut_sub_pkt1_pb5;
940 gamut_pkt1_high->bits.gamut_sub_pkt1_pb4 = tmp.bits.gamut_sub_pkt1_pb4;
941
942 return HI_SUCCESS;
943 }
944
hdmi_reg_gamut_pkt2_low_get(gamut_sub_pkt2_low * gamut_pkt2_low)945 int hdmi_reg_gamut_pkt2_low_get(gamut_sub_pkt2_low *gamut_pkt2_low)
946 {
947 hi_u32 *reg_addr = NULL;
948 gamut_sub_pkt2_low tmp;
949
950 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gamut_pkt2l.u32);
951 tmp.u32 = hdmi_tx_reg_read(reg_addr);
952 gamut_pkt2_low->bits.gamut_sub_pkt2_pb3 = tmp.bits.gamut_sub_pkt2_pb3;
953 gamut_pkt2_low->bits.gamut_sub_pkt2_pb2 = tmp.bits.gamut_sub_pkt2_pb2;
954 gamut_pkt2_low->bits.gamut_sub_pkt2_pb1 = tmp.bits.gamut_sub_pkt2_pb1;
955 gamut_pkt2_low->bits.gamut_sub_pkt2_pb0 = tmp.bits.gamut_sub_pkt2_pb0;
956
957 return HI_SUCCESS;
958 }
959
hdmi_reg_gamut_pkt2_high_get(gamut_sub_pkt2_high * gamut_pkt2_high)960 int hdmi_reg_gamut_pkt2_high_get(gamut_sub_pkt2_high *gamut_pkt2_high)
961 {
962 hi_u32 *reg_addr = NULL;
963 gamut_sub_pkt2_high tmp;
964
965 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gamut_pkt2h.u32);
966 tmp.u32 = hdmi_tx_reg_read(reg_addr);
967 gamut_pkt2_high->bits.gamut_sub_pkt2_pb6 = tmp.bits.gamut_sub_pkt2_pb6;
968 gamut_pkt2_high->bits.gamut_sub_pkt2_pb5 = tmp.bits.gamut_sub_pkt2_pb5;
969 gamut_pkt2_high->bits.gamut_sub_pkt2_pb4 = tmp.bits.gamut_sub_pkt2_pb4;
970
971 return HI_SUCCESS;
972 }
973
hdmi_reg_gamut_pkt3_low_get(gamut_sub_pkt3_low * gamut_pkt3_low)974 int hdmi_reg_gamut_pkt3_low_get(gamut_sub_pkt3_low *gamut_pkt3_low)
975 {
976 hi_u32 *reg_addr = NULL;
977 gamut_sub_pkt3_low tmp;
978
979 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gamut_pkt3l.u32);
980 tmp.u32 = hdmi_tx_reg_read(reg_addr);
981 gamut_pkt3_low->bits.gamut_sub_pkt3_pb3 = tmp.bits.gamut_sub_pkt3_pb3;
982 gamut_pkt3_low->bits.gamut_sub_pkt3_pb2 = tmp.bits.gamut_sub_pkt3_pb2;
983 gamut_pkt3_low->bits.gamut_sub_pkt3_pb1 = tmp.bits.gamut_sub_pkt3_pb1;
984 gamut_pkt3_low->bits.gamut_sub_pkt3_pb0 = tmp.bits.gamut_sub_pkt3_pb0;
985
986 return HI_SUCCESS;
987 }
988
hdmi_reg_gamut_pkt3_high_get(gamut_sub_pkt3_high * gamut_pkt3_high)989 int hdmi_reg_gamut_pkt3_high_get(gamut_sub_pkt3_high *gamut_pkt3_high)
990 {
991 hi_u32 *reg_addr = NULL;
992 gamut_sub_pkt3_high tmp;
993
994 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gamut_pkt3h.u32);
995 tmp.u32 = hdmi_tx_reg_read(reg_addr);
996 gamut_pkt3_high->bits.gamut_sub_pkt3_pb6 = tmp.bits.gamut_sub_pkt3_pb6;
997 gamut_pkt3_high->bits.gamut_sub_pkt3_pb5 = tmp.bits.gamut_sub_pkt3_pb5;
998 gamut_pkt3_high->bits.gamut_sub_pkt3_pb4 = tmp.bits.gamut_sub_pkt3_pb4;
999
1000 return HI_SUCCESS;
1001 }
1002
hdmi_reg_vsif_header_set(unsigned int hb0,unsigned int hb1,unsigned int hb2)1003 int hdmi_reg_vsif_header_set(unsigned int hb0, unsigned int hb1, unsigned int hb2)
1004 {
1005 hi_u32 *reg_addr = NULL;
1006 vsif_pkt_header tmp;
1007
1008 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt_head.u32);
1009 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1010 tmp.bits.vsif_pkt_hb2 = hb2;
1011 tmp.bits.vsif_pkt_hb1 = hb1;
1012 tmp.bits.vsif_pkt_hb0 = hb0;
1013 hdmi_tx_reg_write(reg_addr, tmp.u32);
1014
1015 return HI_SUCCESS;
1016 }
1017
hdmi_reg_vsif_pkt0_low_set(unsigned int vsif_pkt0_pb0,unsigned int vsif_pkt0_pb1,unsigned int vsif_pkt0_pb2,unsigned int vsif_pkt0_pb3)1018 int hdmi_reg_vsif_pkt0_low_set(unsigned int vsif_pkt0_pb0,
1019 unsigned int vsif_pkt0_pb1, unsigned int vsif_pkt0_pb2, unsigned int vsif_pkt0_pb3)
1020 {
1021 hi_u32 *reg_addr = NULL;
1022 vsif_sub_pkt0_low tmp;
1023
1024 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt0l.u32);
1025 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1026 tmp.bits.vsif_sub_pkt0_pb3 = vsif_pkt0_pb3;
1027 tmp.bits.vsif_sub_pkt0_pb2 = vsif_pkt0_pb2;
1028 tmp.bits.vsif_sub_pkt0_pb1 = vsif_pkt0_pb1;
1029 tmp.bits.vsif_sub_pkt0_pb0 = vsif_pkt0_pb0;
1030 hdmi_tx_reg_write(reg_addr, tmp.u32);
1031
1032 return HI_SUCCESS;
1033 }
1034
hdmi_reg_vsif_pkt0_high_set(unsigned int vsif_pkt0_pb4,unsigned int vsif_pkt0_pb5,unsigned int vsif_pkt0_pb6)1035 int hdmi_reg_vsif_pkt0_high_set(unsigned int vsif_pkt0_pb4, unsigned int vsif_pkt0_pb5, unsigned int vsif_pkt0_pb6)
1036 {
1037 hi_u32 *reg_addr = NULL;
1038 vsif_sub_pkt0_high tmp;
1039
1040 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt0h.u32);
1041 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1042 tmp.bits.vsif_sub_pkt0_pb6 = vsif_pkt0_pb6;
1043 tmp.bits.vsif_sub_pkt0_pb5 = vsif_pkt0_pb5;
1044 tmp.bits.vsif_sub_pkt0_pb4 = vsif_pkt0_pb4;
1045 hdmi_tx_reg_write(reg_addr, tmp.u32);
1046
1047 return HI_SUCCESS;
1048 }
1049
hdmi_reg_vsif_pkt1_low_set(unsigned int vsif_pkt1_pb0,unsigned int vsif_pkt1_pb1,unsigned int vsif_pkt1_pb2,unsigned int vsif_pkt1_pb3)1050 int hdmi_reg_vsif_pkt1_low_set(unsigned int vsif_pkt1_pb0,
1051 unsigned int vsif_pkt1_pb1, unsigned int vsif_pkt1_pb2, unsigned int vsif_pkt1_pb3)
1052 {
1053 hi_u32 *reg_addr = NULL;
1054 vsif_sub_pkt1_low tmp;
1055
1056 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt1l.u32);
1057 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1058 tmp.bits.vsif_sub_pkt1_pb3 = vsif_pkt1_pb3;
1059 tmp.bits.vsif_sub_pkt1_pb2 = vsif_pkt1_pb2;
1060 tmp.bits.vsif_sub_pkt1_pb1 = vsif_pkt1_pb1;
1061 tmp.bits.vsif_sub_pkt1_pb0 = vsif_pkt1_pb0;
1062 hdmi_tx_reg_write(reg_addr, tmp.u32);
1063
1064 return HI_SUCCESS;
1065 }
1066
hdmi_reg_vsif_pkt1_high_set(unsigned int vsif_pkt1_pb4,unsigned int vsif_pkt1_pb5,unsigned int vsif_pkt1_pb6)1067 int hdmi_reg_vsif_pkt1_high_set(unsigned int vsif_pkt1_pb4, unsigned int vsif_pkt1_pb5, unsigned int vsif_pkt1_pb6)
1068 {
1069 hi_u32 *reg_addr = NULL;
1070 vsif_sub_pkt1_high tmp;
1071
1072 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt1h.u32);
1073 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1074 tmp.bits.vsif_sub_pkt1_pb6 = vsif_pkt1_pb6;
1075 tmp.bits.vsif_sub_pkt1_pb5 = vsif_pkt1_pb5;
1076 tmp.bits.vsif_sub_pkt1_pb4 = vsif_pkt1_pb4;
1077 hdmi_tx_reg_write(reg_addr, tmp.u32);
1078
1079 return HI_SUCCESS;
1080 }
1081
hdmi_reg_vsif_pkt2_low_set(unsigned int vsif_pkt2_pb0,unsigned int vsif_pkt2_pb1,unsigned int vsif_pkt2_pb2,unsigned int vsif_pkt2_pb3)1082 int hdmi_reg_vsif_pkt2_low_set(unsigned int vsif_pkt2_pb0,
1083 unsigned int vsif_pkt2_pb1, unsigned int vsif_pkt2_pb2, unsigned int vsif_pkt2_pb3)
1084 {
1085 hi_u32 *reg_addr = NULL;
1086 vsif_sub_pkt2_low tmp;
1087
1088 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt2l.u32);
1089 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1090 tmp.bits.vsif_sub_pkt2_pb3 = vsif_pkt2_pb3;
1091 tmp.bits.vsif_sub_pkt2_pb2 = vsif_pkt2_pb2;
1092 tmp.bits.vsif_sub_pkt2_pb1 = vsif_pkt2_pb1;
1093 tmp.bits.vsif_sub_pkt2_pb0 = vsif_pkt2_pb0;
1094 hdmi_tx_reg_write(reg_addr, tmp.u32);
1095
1096 return HI_SUCCESS;
1097 }
1098
hdmi_reg_vsif_pkt2_high_set(unsigned int vsif_pkt2_pb4,unsigned int vsif_pkt2_pb5,unsigned int vsif_pkt2_pb6)1099 int hdmi_reg_vsif_pkt2_high_set(unsigned int vsif_pkt2_pb4, unsigned int vsif_pkt2_pb5, unsigned int vsif_pkt2_pb6)
1100 {
1101 hi_u32 *reg_addr = NULL;
1102 vsif_sub_pkt2_high tmp;
1103
1104 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt2h.u32);
1105 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1106 tmp.bits.vsif_sub_pkt2_pb6 = vsif_pkt2_pb6;
1107 tmp.bits.vsif_sub_pkt2_pb5 = vsif_pkt2_pb5;
1108 tmp.bits.vsif_sub_pkt2_pb4 = vsif_pkt2_pb4;
1109 hdmi_tx_reg_write(reg_addr, tmp.u32);
1110
1111 return HI_SUCCESS;
1112 }
1113
hdmi_reg_vsif_pkt3_low_set(unsigned int vsif_pkt3_pb0,unsigned int vsif_pkt3_pb1,unsigned int vsif_pkt3_pb2,unsigned int vsif_pkt3_pb3)1114 int hdmi_reg_vsif_pkt3_low_set(unsigned int vsif_pkt3_pb0,
1115 unsigned int vsif_pkt3_pb1, unsigned int vsif_pkt3_pb2, unsigned int vsif_pkt3_pb3)
1116 {
1117 hi_u32 *reg_addr = NULL;
1118 vsif_sub_pkt3_low tmp;
1119
1120 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt3l.u32);
1121 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1122 tmp.bits.vsif_sub_pkt3_pb3 = vsif_pkt3_pb3;
1123 tmp.bits.vsif_sub_pkt3_pb2 = vsif_pkt3_pb2;
1124 tmp.bits.vsif_sub_pkt3_pb1 = vsif_pkt3_pb1;
1125 tmp.bits.vsif_sub_pkt3_pb0 = vsif_pkt3_pb0;
1126 hdmi_tx_reg_write(reg_addr, tmp.u32);
1127
1128 return HI_SUCCESS;
1129 }
1130
hdmi_reg_vsif_pkt3_high_set(unsigned int vsif_pkt3_pb4,unsigned int vsif_pkt3_pb5,unsigned int vsif_pkt3_pb6)1131 int hdmi_reg_vsif_pkt3_high_set(unsigned int vsif_pkt3_pb4, unsigned int vsif_pkt3_pb5, unsigned int vsif_pkt3_pb6)
1132 {
1133 hi_u32 *reg_addr = NULL;
1134 vsif_sub_pkt3_high tmp;
1135
1136 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt3h.u32);
1137 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1138 tmp.bits.vsif_sub_pkt3_pb6 = vsif_pkt3_pb6;
1139 tmp.bits.vsif_sub_pkt3_pb5 = vsif_pkt3_pb5;
1140 tmp.bits.vsif_sub_pkt3_pb4 = vsif_pkt3_pb4;
1141 hdmi_tx_reg_write(reg_addr, tmp.u32);
1142
1143 return HI_SUCCESS;
1144 }
1145
hdmi_reg_cea_avi_rpt_en_set(unsigned int cea_avi_rpt_en)1146 int hdmi_reg_cea_avi_rpt_en_set(unsigned int cea_avi_rpt_en)
1147 {
1148 hi_u32 *reg_addr = NULL;
1149 cea_avi_cfg tmp;
1150
1151 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_cfg.u32);
1152 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1153 tmp.bits.cea_avi_rpt_en = cea_avi_rpt_en;
1154 hdmi_tx_reg_write(reg_addr, tmp.u32);
1155
1156 return HI_SUCCESS;
1157 }
1158
hdmi_reg_cea_avi_en_set(unsigned int cea_avi_en)1159 int hdmi_reg_cea_avi_en_set(unsigned int cea_avi_en)
1160 {
1161 hi_u32 *reg_addr = NULL;
1162 cea_avi_cfg tmp;
1163
1164 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_cfg.u32);
1165 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1166 tmp.bits.cea_avi_en = cea_avi_en;
1167 hdmi_tx_reg_write(reg_addr, tmp.u32);
1168
1169 return HI_SUCCESS;
1170 }
1171
hdmi_reg_vsif_pkt_header_get(vsif_pkt_header * vsif_header)1172 int hdmi_reg_vsif_pkt_header_get(vsif_pkt_header *vsif_header)
1173 {
1174 hi_u32 *reg_addr = NULL;
1175 vsif_pkt_header tmp;
1176
1177 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt_head.u32);
1178 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1179 vsif_header->bits.vsif_pkt_hb2 = tmp.bits.vsif_pkt_hb2;
1180 vsif_header->bits.vsif_pkt_hb1 = tmp.bits.vsif_pkt_hb1;
1181 vsif_header->bits.vsif_pkt_hb0 = tmp.bits.vsif_pkt_hb0;
1182
1183 return HI_SUCCESS;
1184 }
1185
hdmi_reg_vsif_pkt0_low_get(vsif_sub_pkt0_low * vsif_pkt0_low)1186 int hdmi_reg_vsif_pkt0_low_get(vsif_sub_pkt0_low *vsif_pkt0_low)
1187 {
1188 hi_u32 *reg_addr = NULL;
1189 vsif_sub_pkt0_low tmp;
1190
1191 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt0l.u32);
1192 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1193 vsif_pkt0_low->bits.vsif_sub_pkt0_pb3 = tmp.bits.vsif_sub_pkt0_pb3;
1194 vsif_pkt0_low->bits.vsif_sub_pkt0_pb2 = tmp.bits.vsif_sub_pkt0_pb2;
1195 vsif_pkt0_low->bits.vsif_sub_pkt0_pb1 = tmp.bits.vsif_sub_pkt0_pb1;
1196 vsif_pkt0_low->bits.vsif_sub_pkt0_pb0 = tmp.bits.vsif_sub_pkt0_pb0;
1197
1198 return HI_SUCCESS;
1199 }
1200
hdmi_reg_vsif_pkt0_high_get(vsif_sub_pkt0_high * vsif_pkt0_high)1201 int hdmi_reg_vsif_pkt0_high_get(vsif_sub_pkt0_high *vsif_pkt0_high)
1202 {
1203 hi_u32 *reg_addr = NULL;
1204 vsif_sub_pkt0_high tmp;
1205
1206 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt0h.u32);
1207 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1208 vsif_pkt0_high->bits.vsif_sub_pkt0_pb6 = tmp.bits.vsif_sub_pkt0_pb6;
1209 vsif_pkt0_high->bits.vsif_sub_pkt0_pb5 = tmp.bits.vsif_sub_pkt0_pb5;
1210 vsif_pkt0_high->bits.vsif_sub_pkt0_pb4 = tmp.bits.vsif_sub_pkt0_pb4;
1211
1212 return HI_SUCCESS;
1213 }
1214
hdmi_reg_vsif_pkt1_low_get(vsif_sub_pkt1_low * vsif_pkt1_low)1215 int hdmi_reg_vsif_pkt1_low_get(vsif_sub_pkt1_low *vsif_pkt1_low)
1216 {
1217 hi_u32 *reg_addr = NULL;
1218 vsif_sub_pkt1_low tmp;
1219
1220 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt1l.u32);
1221 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1222 vsif_pkt1_low->bits.vsif_sub_pkt1_pb3 = tmp.bits.vsif_sub_pkt1_pb3;
1223 vsif_pkt1_low->bits.vsif_sub_pkt1_pb2 = tmp.bits.vsif_sub_pkt1_pb2;
1224 vsif_pkt1_low->bits.vsif_sub_pkt1_pb1 = tmp.bits.vsif_sub_pkt1_pb1;
1225 vsif_pkt1_low->bits.vsif_sub_pkt1_pb0 = tmp.bits.vsif_sub_pkt1_pb0;
1226
1227 return HI_SUCCESS;
1228 }
1229
hdmi_reg_vsif_pkt1_high_get(vsif_sub_pkt1_high * vsif_pkt1_high)1230 int hdmi_reg_vsif_pkt1_high_get(vsif_sub_pkt1_high *vsif_pkt1_high)
1231 {
1232 hi_u32 *reg_addr = NULL;
1233 vsif_sub_pkt1_high tmp;
1234
1235 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt1h.u32);
1236 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1237 vsif_pkt1_high->bits.vsif_sub_pkt1_pb6 = tmp.bits.vsif_sub_pkt1_pb6;
1238 vsif_pkt1_high->bits.vsif_sub_pkt1_pb5 = tmp.bits.vsif_sub_pkt1_pb5;
1239 vsif_pkt1_high->bits.vsif_sub_pkt1_pb4 = tmp.bits.vsif_sub_pkt1_pb4;
1240
1241 return HI_SUCCESS;
1242 }
1243
hdmi_reg_vsif_pkt2_low_get(vsif_sub_pkt2_low * vsif_pkt2_low)1244 int hdmi_reg_vsif_pkt2_low_get(vsif_sub_pkt2_low *vsif_pkt2_low)
1245 {
1246 hi_u32 *reg_addr = NULL;
1247 vsif_sub_pkt2_low tmp;
1248
1249 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt2l.u32);
1250 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1251 vsif_pkt2_low->bits.vsif_sub_pkt2_pb3 = tmp.bits.vsif_sub_pkt2_pb3;
1252 vsif_pkt2_low->bits.vsif_sub_pkt2_pb2 = tmp.bits.vsif_sub_pkt2_pb2;
1253 vsif_pkt2_low->bits.vsif_sub_pkt2_pb1 = tmp.bits.vsif_sub_pkt2_pb1;
1254 vsif_pkt2_low->bits.vsif_sub_pkt2_pb0 = tmp.bits.vsif_sub_pkt2_pb0;
1255
1256 return HI_SUCCESS;
1257 }
1258
hdmi_reg_vsif_pkt2_high_get(vsif_sub_pkt2_high * vsif_pkt2_high)1259 int hdmi_reg_vsif_pkt2_high_get(vsif_sub_pkt2_high *vsif_pkt2_high)
1260 {
1261 hi_u32 *reg_addr = NULL;
1262 vsif_sub_pkt2_high tmp;
1263
1264 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt2h.u32);
1265 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1266 vsif_pkt2_high->bits.vsif_sub_pkt2_pb6 = tmp.bits.vsif_sub_pkt2_pb6;
1267 vsif_pkt2_high->bits.vsif_sub_pkt2_pb5 = tmp.bits.vsif_sub_pkt2_pb5;
1268 vsif_pkt2_high->bits.vsif_sub_pkt2_pb4 = tmp.bits.vsif_sub_pkt2_pb4;
1269
1270 return HI_SUCCESS;
1271 }
1272
hdmi_reg_vsif_pkt3_low_get(vsif_sub_pkt3_low * vsif_pkt3_low)1273 int hdmi_reg_vsif_pkt3_low_get(vsif_sub_pkt3_low *vsif_pkt3_low)
1274 {
1275 hi_u32 *reg_addr = NULL;
1276 vsif_sub_pkt3_low tmp;
1277
1278 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt3l.u32);
1279 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1280 vsif_pkt3_low->bits.vsif_sub_pkt3_pb3 = tmp.bits.vsif_sub_pkt3_pb3;
1281 vsif_pkt3_low->bits.vsif_sub_pkt3_pb2 = tmp.bits.vsif_sub_pkt3_pb2;
1282 vsif_pkt3_low->bits.vsif_sub_pkt3_pb1 = tmp.bits.vsif_sub_pkt3_pb1;
1283 vsif_pkt3_low->bits.vsif_sub_pkt3_pb0 = tmp.bits.vsif_sub_pkt3_pb0;
1284
1285 return HI_SUCCESS;
1286 }
1287
hdmi_reg_vsif_pkt3_high_get(vsif_sub_pkt3_high * vsif_pkt3_high)1288 int hdmi_reg_vsif_pkt3_high_get(vsif_sub_pkt3_high *vsif_pkt3_high)
1289 {
1290 hi_u32 *reg_addr = NULL;
1291 vsif_sub_pkt3_high tmp;
1292
1293 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_pkt3h.u32);
1294 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1295 vsif_pkt3_high->bits.vsif_sub_pkt3_pb6 = tmp.bits.vsif_sub_pkt3_pb6;
1296 vsif_pkt3_high->bits.vsif_sub_pkt3_pb5 = tmp.bits.vsif_sub_pkt3_pb5;
1297 vsif_pkt3_high->bits.vsif_sub_pkt3_pb4 = tmp.bits.vsif_sub_pkt3_pb4;
1298
1299 return HI_SUCCESS;
1300 }
1301
hdmi_reg_cea_aud_rpt_en_set(unsigned int cea_aud_rpt_en)1302 int hdmi_reg_cea_aud_rpt_en_set(unsigned int cea_aud_rpt_en)
1303 {
1304 hi_u32 *reg_addr = NULL;
1305 cea_aud_cfg tmp;
1306
1307 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aud_cfg.u32);
1308 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1309 tmp.bits.cea_aud_rpt_en = cea_aud_rpt_en;
1310 hdmi_tx_reg_write(reg_addr, tmp.u32);
1311
1312 return HI_SUCCESS;
1313 }
1314
hdmi_reg_cea_aud_en_set(unsigned int cea_aud_en)1315 int hdmi_reg_cea_aud_en_set(unsigned int cea_aud_en)
1316 {
1317 hi_u32 *reg_addr = NULL;
1318 cea_aud_cfg tmp;
1319
1320 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aud_cfg.u32);
1321 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1322 tmp.bits.cea_aud_en = cea_aud_en;
1323 hdmi_tx_reg_write(reg_addr, tmp.u32);
1324
1325 return HI_SUCCESS;
1326 }
1327
hdmi_reg_cea_gen_rpt_en_set(unsigned int cea_gen_rpt_en)1328 int hdmi_reg_cea_gen_rpt_en_set(unsigned int cea_gen_rpt_en)
1329 {
1330 hi_u32 *reg_addr = NULL;
1331 cea_gen_cfg tmp;
1332
1333 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_cfg.u32);
1334 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1335 tmp.bits.cea_gen_rpt_en = cea_gen_rpt_en;
1336 hdmi_tx_reg_write(reg_addr, tmp.u32);
1337
1338 return HI_SUCCESS;
1339 }
1340
hdmi_reg_cea_gen_en_set(unsigned int cea_gen_en)1341 int hdmi_reg_cea_gen_en_set(unsigned int cea_gen_en)
1342 {
1343 hi_u32 *reg_addr = NULL;
1344 cea_gen_cfg tmp;
1345
1346 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_cfg.u32);
1347 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1348 tmp.bits.cea_gen_en = cea_gen_en;
1349 hdmi_tx_reg_write(reg_addr, tmp.u32);
1350
1351 return HI_SUCCESS;
1352 }
1353
hdmi_reg_cea_cp_rpt_cnt_set(unsigned int cea_cp_rpt_cnt)1354 int hdmi_reg_cea_cp_rpt_cnt_set(unsigned int cea_cp_rpt_cnt)
1355 {
1356 hi_u32 *reg_addr = NULL;
1357 cea_cp_cfg tmp;
1358
1359 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->cp_cfg.u32);
1360 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1361 tmp.bits.cea_cp_rpt_cnt = cea_cp_rpt_cnt;
1362 hdmi_tx_reg_write(reg_addr, tmp.u32);
1363
1364 return HI_SUCCESS;
1365 }
1366
hdmi_reg_cea_cp_rpt_en_set(unsigned int cea_cp_rpt_en)1367 int hdmi_reg_cea_cp_rpt_en_set(unsigned int cea_cp_rpt_en)
1368 {
1369 hi_u32 *reg_addr = NULL;
1370 cea_cp_cfg tmp;
1371
1372 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->cp_cfg.u32);
1373 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1374 tmp.bits.cea_cp_rpt_en = cea_cp_rpt_en;
1375 hdmi_tx_reg_write(reg_addr, tmp.u32);
1376
1377 return HI_SUCCESS;
1378 }
1379
hdmi_reg_cea_cp_en_set(unsigned int cea_cp_en)1380 int hdmi_reg_cea_cp_en_set(unsigned int cea_cp_en)
1381 {
1382 hi_u32 *reg_addr = NULL;
1383 cea_cp_cfg tmp;
1384
1385 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->cp_cfg.u32);
1386 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1387 tmp.bits.cea_cp_en = cea_cp_en;
1388 hdmi_tx_reg_write(reg_addr, tmp.u32);
1389
1390 return HI_SUCCESS;
1391 }
1392
hdmi_reg_cea_gamut_rpt_en_set(unsigned int cea_gamut_rpt_en)1393 int hdmi_reg_cea_gamut_rpt_en_set(unsigned int cea_gamut_rpt_en)
1394 {
1395 hi_u32 *reg_addr = NULL;
1396 cea_gamut_cfg tmp;
1397
1398 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gamut_cfg.u32);
1399 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1400 tmp.bits.cea_gamut_rpt_en = cea_gamut_rpt_en;
1401 hdmi_tx_reg_write(reg_addr, tmp.u32);
1402
1403 return HI_SUCCESS;
1404 }
1405
hdmi_reg_cea_gamut_en_set(unsigned int cea_gamut_en)1406 int hdmi_reg_cea_gamut_en_set(unsigned int cea_gamut_en)
1407 {
1408 hi_u32 *reg_addr = NULL;
1409 cea_gamut_cfg tmp;
1410
1411 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gamut_cfg.u32);
1412 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1413 tmp.bits.cea_gamut_en = cea_gamut_en;
1414 hdmi_tx_reg_write(reg_addr, tmp.u32);
1415
1416 return HI_SUCCESS;
1417 }
1418
hdmi_reg_cea_vsif_rpt_en_set(unsigned int cea_vsif_rpt_en)1419 int hdmi_reg_cea_vsif_rpt_en_set(unsigned int cea_vsif_rpt_en)
1420 {
1421 hi_u32 *reg_addr = NULL;
1422 cea_vsif_cfg tmp;
1423
1424 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_cfg.u32);
1425 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1426 tmp.bits.cea_vsif_rpt_en = cea_vsif_rpt_en;
1427 hdmi_tx_reg_write(reg_addr, tmp.u32);
1428
1429 return HI_SUCCESS;
1430 }
1431
hdmi_reg_cea_vsif_en_set(unsigned int cea_vsif_en)1432 int hdmi_reg_cea_vsif_en_set(unsigned int cea_vsif_en)
1433 {
1434 hi_u32 *reg_addr = NULL;
1435 cea_vsif_cfg tmp;
1436
1437 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_cfg.u32);
1438 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1439 tmp.bits.cea_vsif_en = cea_vsif_en;
1440 hdmi_tx_reg_write(reg_addr, tmp.u32);
1441
1442 return HI_SUCCESS;
1443 }
1444
hdmi_reg_eess_mode_en_set(unsigned int eess_mode_en)1445 int hdmi_reg_eess_mode_en_set(unsigned int eess_mode_en)
1446 {
1447 hi_u32 *reg_addr = NULL;
1448 cea_avmixer_config tmp;
1449 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avmixer_cfg.u32);
1450 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1451 tmp.bits.eess_mode_en = eess_mode_en;
1452 hdmi_tx_reg_write(reg_addr, tmp.u32);
1453
1454 return HI_SUCCESS;
1455 }
1456
hdmi_reg_hdmi_dvi_sel_set(unsigned int hdmi_dvi_sel)1457 int hdmi_reg_hdmi_dvi_sel_set(unsigned int hdmi_dvi_sel)
1458 {
1459 hi_u32 *reg_addr = NULL;
1460 cea_avmixer_config tmp;
1461
1462 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avmixer_cfg.u32);
1463 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1464 tmp.bits.hdmi_dvi_sel = hdmi_dvi_sel;
1465 hdmi_tx_reg_write(reg_addr, tmp.u32);
1466
1467 return HI_SUCCESS;
1468 }
1469
hdmi_reg_dc_pkt_en_set(unsigned int dc_pkt_en)1470 int hdmi_reg_dc_pkt_en_set(unsigned int dc_pkt_en)
1471 {
1472 hi_u32 *reg_addr = NULL;
1473 cea_avmixer_config tmp;
1474
1475 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avmixer_cfg.u32);
1476 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1477 tmp.bits.dc_pkt_en = dc_pkt_en;
1478 hdmi_tx_reg_write(reg_addr, tmp.u32);
1479
1480 return HI_SUCCESS;
1481 }
1482
hdmi_reg_null_pkt_en_set(unsigned int null_pkt_en)1483 int hdmi_reg_null_pkt_en_set(unsigned int null_pkt_en)
1484 {
1485 hi_u32 *reg_addr = NULL;
1486 cea_avmixer_config tmp;
1487 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avmixer_cfg.u32);
1488 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1489 tmp.bits.null_pkt_en = null_pkt_en;
1490 hdmi_tx_reg_write(reg_addr, tmp.u32);
1491
1492 return HI_SUCCESS;
1493 }
1494
hdmi_reg_null_pkt_en_get(hi_void)1495 hi_u32 hdmi_reg_null_pkt_en_get(hi_void)
1496 {
1497 hi_u32 *reg_addr = NULL;
1498 cea_avmixer_config tmp;
1499
1500 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avmixer_cfg.u32);
1501 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1502
1503 return tmp.bits.null_pkt_en;
1504 }
1505
hdmi_reg_hdmi_mode_set(unsigned int hdmi_mode)1506 int hdmi_reg_hdmi_mode_set(unsigned int hdmi_mode)
1507 {
1508 hi_u32 *reg_addr = NULL;
1509 cea_avmixer_config tmp;
1510
1511 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avmixer_cfg.u32);
1512 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1513 tmp.bits.hdmi_mode = hdmi_mode;
1514 hdmi_tx_reg_write(reg_addr, tmp.u32);
1515
1516 return HI_SUCCESS;
1517 }
1518
hdmi_reg_cp_clr_avmute_set(unsigned int cp_clr_avmute)1519 int hdmi_reg_cp_clr_avmute_set(unsigned int cp_clr_avmute)
1520 {
1521 hi_u32 *reg_addr = NULL;
1522 cp_pkt_avmute tmp;
1523
1524 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->pkt_avmute.u32);
1525 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1526 tmp.bits.cp_clr_avmute = cp_clr_avmute;
1527 hdmi_tx_reg_write(reg_addr, tmp.u32);
1528
1529 return HI_SUCCESS;
1530 }
1531
hdmi_reg_cp_set_avmute_set(unsigned int cp_set_avmute)1532 int hdmi_reg_cp_set_avmute_set(unsigned int cp_set_avmute)
1533 {
1534 hi_u32 *reg_addr = NULL;
1535 cp_pkt_avmute tmp;
1536
1537 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->pkt_avmute.u32);
1538 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1539 tmp.bits.cp_set_avmute = cp_set_avmute;
1540 hdmi_tx_reg_write(reg_addr, tmp.u32);
1541
1542 return HI_SUCCESS;
1543 }
1544
hdmi_reg_enc_bypass_set(unsigned int enc_bypass)1545 int hdmi_reg_enc_bypass_set(unsigned int enc_bypass)
1546 {
1547 hi_u32 *reg_addr = NULL;
1548 hdmi_enc_ctrl tmp;
1549
1550 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->enc_ctrl.u32);
1551 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1552 tmp.bits.enc_bypass = enc_bypass;
1553 hdmi_tx_reg_write(reg_addr, tmp.u32);
1554
1555 return HI_SUCCESS;
1556 }
1557
hdmi_reg_enc_scr_on_set(unsigned int enc_scr_on)1558 int hdmi_reg_enc_scr_on_set(unsigned int enc_scr_on)
1559 {
1560 hi_u32 *reg_addr = NULL;
1561 hdmi_enc_ctrl tmp;
1562
1563 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->enc_ctrl.u32);
1564 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1565 tmp.bits.enc_scr_on = enc_scr_on;
1566 hdmi_tx_reg_write(reg_addr, tmp.u32);
1567
1568 return HI_SUCCESS;
1569 }
1570
hdmi_reg_enc_hdmi2_on_set(unsigned int enc_hdmi2_on)1571 int hdmi_reg_enc_hdmi2_on_set(unsigned int enc_hdmi2_on)
1572 {
1573 hi_u32 *reg_addr = NULL;
1574 hdmi_enc_ctrl tmp;
1575
1576 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->enc_ctrl.u32);
1577 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1578 tmp.bits.enc_hdmi2_on = enc_hdmi2_on;
1579 hdmi_tx_reg_write(reg_addr, tmp.u32);
1580
1581 return HI_SUCCESS;
1582 }
1583
hdmi_reg_tmds_pack_mode_get(hi_void)1584 hi_u32 hdmi_reg_tmds_pack_mode_get(hi_void)
1585 {
1586 hi_u32 *reg_addr = NULL;
1587 tx_pack_fifo_ctrl tmp;
1588
1589 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->pack_fifo_ctrl.u32);
1590 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1591 return tmp.bits.tmds_pack_mode;
1592 }
1593
hdmi_reg_pclk2tclk_stable_get(hi_void)1594 hi_u32 hdmi_reg_pclk2tclk_stable_get(hi_void)
1595 {
1596 hi_u32 *reg_addr = NULL;
1597 tx_pack_fifo_st tmp;
1598
1599 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->pack_fifo_status.u32);
1600 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1601 return tmp.bits.pclk2tclk_stable;
1602 }
1603
hdmi_reg_cea_avi_en_get(hi_void)1604 hi_u32 hdmi_reg_cea_avi_en_get(hi_void)
1605 {
1606 hi_u32 *reg_addr = NULL;
1607 cea_avi_cfg tmp;
1608
1609 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_cfg.u32);
1610 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1611 return tmp.bits.cea_avi_en;
1612 }
1613
hdmi_reg_cea_aud_en_get(hi_void)1614 hi_u32 hdmi_reg_cea_aud_en_get(hi_void)
1615 {
1616 hi_u32 *reg_addr = NULL;
1617 cea_aud_cfg tmp;
1618
1619 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->aud_cfg.u32);
1620 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1621 return tmp.bits.cea_aud_en;
1622 }
1623
hdmi_reg_cea_gen_en_get(hi_void)1624 hi_u32 hdmi_reg_cea_gen_en_get(hi_void)
1625 {
1626 hi_u32 *reg_addr = NULL;
1627 cea_gen_cfg tmp;
1628
1629 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gen_cfg.u32);
1630 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1631 return tmp.bits.cea_gen_en;
1632 }
1633
hdmi_reg_cea_cp_rpt_en_get(hi_void)1634 hi_u32 hdmi_reg_cea_cp_rpt_en_get(hi_void)
1635 {
1636 hi_u32 *reg_addr = NULL;
1637 cea_cp_cfg tmp;
1638
1639 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->cp_cfg.u32);
1640 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1641 return tmp.bits.cea_cp_rpt_en;
1642 }
1643
hdmi_reg_cea_gamut_en_get(hi_void)1644 hi_u32 hdmi_reg_cea_gamut_en_get(hi_void)
1645 {
1646 hi_u32 *reg_addr = NULL;
1647 cea_gamut_cfg tmp;
1648
1649 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->gamut_cfg.u32);
1650 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1651 return tmp.bits.cea_gamut_en;
1652 }
1653
hdmi_reg_cea_vsif_rpt_en_get(hi_void)1654 hi_u32 hdmi_reg_cea_vsif_rpt_en_get(hi_void)
1655 {
1656 hi_u32 *reg_addr = NULL;
1657 cea_vsif_cfg tmp;
1658
1659 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->vsif_cfg.u32);
1660 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1661 return tmp.bits.cea_vsif_rpt_en;
1662 }
1663
hdmi_reg_dc_pkt_en_get(hi_void)1664 hi_u32 hdmi_reg_dc_pkt_en_get(hi_void)
1665 {
1666 hi_u32 *reg_addr = NULL;
1667 cea_avmixer_config tmp;
1668
1669 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avmixer_cfg.u32);
1670 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1671 return tmp.bits.dc_pkt_en;
1672 }
1673
hdmi_reg_hdmi_mode_get(hi_void)1674 hi_u32 hdmi_reg_hdmi_mode_get(hi_void)
1675 {
1676 hi_u32 *reg_addr = NULL;
1677 cea_avmixer_config tmp;
1678
1679 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avmixer_cfg.u32);
1680 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1681 return tmp.bits.hdmi_mode;
1682 }
1683
hdmi_reg_cp_set_avmute_get(hi_void)1684 hi_u32 hdmi_reg_cp_set_avmute_get(hi_void)
1685 {
1686 hi_u32 *reg_addr = NULL;
1687 cp_pkt_avmute tmp;
1688
1689 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->pkt_avmute.u32);
1690 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1691 return tmp.bits.cp_set_avmute;
1692 }
1693
hdmi_reg_enc_scr_on_get(hi_void)1694 hi_u32 hdmi_reg_enc_scr_on_get(hi_void)
1695 {
1696 hi_u32 *reg_addr = NULL;
1697 hdmi_enc_ctrl tmp;
1698
1699 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->enc_ctrl.u32);
1700 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1701 return tmp.bits.enc_scr_on;
1702 }
1703
hdmi_reg_enc_hdmi2_on_get(hi_void)1704 hi_u32 hdmi_reg_enc_hdmi2_on_get(hi_void)
1705 {
1706 hi_u32 *reg_addr = NULL;
1707 hdmi_enc_ctrl tmp;
1708
1709 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->enc_ctrl.u32);
1710 tmp.u32 = hdmi_tx_reg_read(reg_addr);
1711 return tmp.bits.enc_hdmi2_on;
1712 }
1713
1714