1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #ifndef __GRAPHICS_DRV_H__ 20 #define __GRAPHICS_DRV_H__ 21 22 #include "hi_osal.h" 23 #include "hi_type.h" 24 #include "hi_common_adapt.h" 25 #include "hi_comm_vo_adapt.h" 26 #include "mkp_vo_dev.h" 27 #include "vou_def.h" 28 #include "vou_coef.h" 29 30 typedef enum { 31 HIFB_INTTYPE_VO, 32 HIFB_INTTYPE_VO_DISP, 33 HIFB_INTTYPE_WBC, 34 HIFB_INTTYPE_BUTT, 35 } fb_int_tpye; 36 37 typedef hi_s32 (*fb_int_call_back)(hi_void *paraml, hi_void *paramr); 38 39 #define GFX_SPIN_LOCK_S osal_spinlock_t 40 #define gfx_spin_lock_init(lock) osal_spin_lock_init(lock) 41 #define gfx_spin_lock_deinit(lock) osal_spin_lock_destroy(lock) 42 #define gfx_spin_lock_irqsave(lock, flag) osal_spin_lock_irqsave(lock, flag) 43 #define gfx_spin_unlock_irqrestore(lock, flag) osal_spin_unlock_irqrestore(lock, flag) 44 45 typedef struct { 46 hi_u32 start_phy_addr; 47 hi_u32 end_phy_addr; 48 } mddrc_zone_addr; 49 50 typedef struct { 51 hi_u32 ar_phy_addr; 52 hi_u32 gb_phy_addr; 53 hi_u32 offset; 54 hi_u32 stride; 55 hi_rect in_rect; 56 hi_rect out_rect; 57 } graphic_wbc_info; 58 59 typedef struct { 60 hal_disp_pixel_format pixel_fmt; /* new */ 61 hi_u64 ar_phy_addr; 62 hi_u64 gb_phy_addr; /* new */ 63 hi_u32 frame_size0; /* new */ 64 hi_u32 frame_size1; /* new */ 65 hi_u32 width; /* new */ 66 hi_u32 height; /* new */ 67 hi_bool is_lossless_a; /* new */ 68 hi_bool is_lossless; /* new */ 69 hi_u32 offset; 70 hi_u32 stride; 71 } graphic_dcmp_info; 72 73 typedef struct { 74 hi_dynamic_range dst_dynamic_range; /* destination dynamic range type */ 75 } vo_graphic_attr; 76 77 typedef struct { 78 hal_disp_layer layer_id; 79 hi_bool opened; 80 hi_bool binded; 81 hi_vo_dev binded_dev; 82 83 fb_int_call_back vo_call_back; /* VSYNC interrupt callback function */ 84 hi_void *vo_call_back_arg; 85 86 fb_int_call_back wbc_call_back; /* VSYNC interrupt callback function */ 87 hi_void *wbc_call_back_arg; 88 89 hi_vo_csc gfx_csc; 90 csc_coef_param csc_param; 91 GFX_SPIN_LOCK_S spin_lock; 92 93 hi_u32 start_section; 94 hi_u32 zone_nums; 95 vo_graphic_attr vo_gfx_attr; /* VO graphic layer attribute */ 96 } vo_gfxlayer_context; 97 98 typedef enum { 99 GF_HIHDR_G_TYP = 0, 100 GF_HIHDR_G_TYP1, 101 GF_HIHDR_G_RAND, 102 GF_HIHDR_G_MAX, 103 GF_HIHDR_G_MIN, 104 GF_HIHDR_G_ZERO, 105 GF_HIHDR_G_BUTT 106 } gf_hihdr_g_mode; 107 108 typedef enum { 109 GF_CSC_G0_TYP = 0, 110 GF_CSC_G0_TYP1, 111 GF_CSC_G0_RAND, 112 GF_CSC_G0_MAX, 113 GF_CSC_G0_MIN, 114 GF_CSC_G0_ZERO, 115 GF_CSC_G0_BUTT 116 } gf_csc_g0_mode; 117 118 typedef enum { 119 GF_SDR_IN_HDR10_OUT = 0, 120 GF_SDR_IN_HLG_OUT, 121 GF_SDR_PREMULT, 122 GF_SDR709_IN_2020_OUT, 123 GF_BUTT 124 } highdr_scene_mode; 125 126 typedef struct { 127 hi_u32 hihdr_r2y_en; 128 129 highdr_scene_mode ghdr_scene_mode; 130 } gf_csc_g0_cfg; 131 132 typedef enum { 133 VDP_GP_ORDER_NULL = 0x0, 134 VDP_GP_ORDER_CSC = 0x1, 135 VDP_GP_ORDER_ZME = 0x2, 136 VDP_GP_ORDER_CSC_ZME = 0x3, 137 VDP_GP_ORDER_ZME_CSC = 0x4, 138 139 VDP_GP_ORDER_BUTT 140 } vdp_gp_order; 141 142 typedef enum { 143 VDP_GFX_BITEXTEND_1ST = 0, 144 VDP_GFX_BITEXTEND_2ND = 0x2, 145 VDP_GFX_BITEXTEND_3RD = 0x3, 146 147 VDP_GFX_BITEXTEND_BUTT 148 } vdp_gfx_bitextend; 149 150 typedef struct { 151 hi_u32 a_data; 152 hi_u32 r_data; 153 hi_u32 g_data; 154 hi_u32 b_data; 155 } vdp_gfx_lut_data; 156 157 typedef struct { 158 hi_u32 key_r_min; 159 hi_u32 key_g_min; 160 hi_u32 key_b_min; 161 162 hi_u32 key_r_max; 163 hi_u32 key_g_max; 164 hi_u32 key_b_max; 165 166 hi_u32 key_r_msk; 167 hi_u32 key_g_msk; 168 hi_u32 key_b_msk; 169 170 hi_u32 key_mode; 171 } vdp_gfx_ckey; 172 173 typedef struct { 174 hi_u32 mask_r; 175 hi_u32 mask_g; 176 hi_u32 mask_b; 177 } vdp_gfx_mask; 178 179 typedef enum { 180 VDP_GFX_PARA_LUT = 0, 181 182 VDP_GFX_PARA_BUTT 183 } vdp_gfx_para; 184 185 typedef enum { 186 VDP_GP_PARA_ZME_HORL = 0, 187 VDP_GP_PARA_ZME_HORC, 188 VDP_GP_PARA_ZME_VERL, 189 VDP_GP_PARA_ZME_VERC, 190 191 VDP_GP_GTI_PARA_ZME_HORL, 192 VDP_GP_GTI_PARA_ZME_HORC, 193 VDP_GP_GTI_PARA_ZME_VERL, 194 VDP_GP_GTI_PARA_ZME_VERC, 195 196 VDP_GP_PARA_ZME_HOR, 197 VDP_GP_PARA_ZME_VER, 198 VDP_GP_PARA_HDR_DEGAMM, 199 VDP_GP_PARA_HDR_GAMM, 200 201 VDP_GP_PARA_BUTT 202 } vdp_gp_para; 203 204 typedef enum { 205 VDP_REQ_CTRL_16BURST_1, 206 VDP_REQ_CTRL_16BURST_2, 207 VDP_REQ_CTRL_16BURST_4, 208 VDP_REQ_CTRL_16BURST_8, 209 VDP_REQ_CTRL_BUTT 210 } vdp_req_ctrl; 211 212 typedef enum { 213 VDP_G0_ZME_TYP = 0, 214 VDP_G0_ZME_TYP1, 215 VDP_G0_ZME_RAND, 216 VDP_G0_ZME_MAX, 217 VDP_G0_ZME_MIN, 218 VDP_G0_ZME_ZERO, 219 VDP_G0_ZME_BUTT 220 } gf_g0_zme_mode; 221 222 typedef enum { 223 VDP_G0_ZME_FIR_COPY = 0, 224 VDP_G0_ZME_FIR_FILT = 1 225 } gf_g0_zme_fir_mode; 226 227 typedef struct { 228 hi_u32 ck_gt_en; 229 hi_u32 in_width; 230 hi_u32 out_width; 231 hi_u32 out_pro; 232 233 hi_u32 hfir_en; 234 hi_u32 lhmid_en; 235 hi_u32 ahmid_en; 236 hi_u32 lhfir_mode; 237 hi_u32 ahfir_mode; 238 239 hi_u32 in_height; 240 hi_u32 out_height; 241 242 hi_u32 vfir_en; 243 hi_u32 lvmid_en; 244 hi_u32 avmid_en; 245 hi_u32 lvfir_mode; 246 hi_u32 avfir_mode; 247 } gf_g0_zme_cfg; 248 249 typedef enum { 250 GF_RM_COEF_MODE_TYP = 0x0, 251 GF_RM_COEF_MODE_RAN = 0x1, 252 GF_RM_COEF_MODE_MIN = 0x2, 253 GF_RM_COEF_MODE_MAX = 0x3, 254 GF_RM_COEF_MODE_ZRO = 0x4, 255 GF_RM_COEF_MODE_CUS = 0x5, 256 GF_RM_COEF_MODE_UP = 0x6, 257 GF_RM_COEF_MODE_BUTT 258 } gf_rm_coef_mode; 259 260 typedef enum { 261 GFX_DCMP_SRC_MODE_ARGB8888 = 0, 262 GFX_DCMP_SRC_MODE_ARGB6888, 263 GFX_DCMP_SRC_MODE_ARGB1555, 264 GFX_DCMP_SRC_MODE_ARGB4444, 265 266 GFX_DCMP_SRC_MODE_BUTT 267 } gfx_dcmp_src_mode; 268 269 hi_bool graphic_drv_set_mddr_detect_zone(hal_disp_layer layer, hi_u32 start_section, hi_u32 zone_nums); 270 271 hi_s32 graphic_drv_get_hal_layer(hi_u32 layer, hal_disp_layer *hal_layer); 272 hi_s32 graphic_drv_get_layer_index(hal_disp_layer hal_layer, hi_u32 *layer); 273 274 hi_void graphic_drv_clr_wbc_mask(hal_disp_layer layer); 275 hi_void graphic_drv_clear_wbc_int_status(hal_disp_layer layer); 276 277 hi_s32 graphic_drv_check_graphic_bind_support(hi_graphic_layer gfx_layer, hi_vo_dev dev); 278 hi_s32 graphic_drv_graphic_bind_dev(hi_graphic_layer gfx_layer, hi_vo_dev dev); 279 hi_s32 graphic_drv_graphic_un_bind_dev(hi_graphic_layer gfx_layer); 280 281 hi_s32 graphic_drv_init(hi_void); 282 hi_s32 graphic_drv_exit(hi_void); 283 284 hi_s32 graphic_drv_lock_init(hi_void); 285 hi_s32 graphic_drv_lock_exit(hi_void); 286 287 hi_s32 graphic_drv_set_csc_coef(hal_disp_layer gfx_layer, hi_vo_csc *gfx_csc, csc_coef_param *csc_param); 288 hi_bool graphic_drv_is_chip_support_csc(hi_void); 289 hi_bool graphic_drv_get_layer_enable(hal_disp_layer gfx_layer); 290 hi_s32 graphic_drv_check_csc_coef(hal_disp_layer gfx_layer, hi_vo_csc *gfx_csc); 291 292 hi_s32 graphic_drv_show_proc(osal_proc_entry_t *s); 293 294 hi_void gf_func_set_g0_zme_mode(hi_u32 layer, gf_g0_zme_mode g0_zme_mode, gf_g0_zme_cfg *cfg); 295 296 #endif /* __GRAPHICS_DRV_H__ */ 297