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123

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dmt8195-afe-pcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Trevor Wu <trevor.wu@mediatek.com>
14 const: mediatek,mt8195-audio
25 reset-names:
28 memory-region:
31 Shared memory region for AFE memif. A "shared-dma-pool".
32 See ../reserved-memory/reserved-memory.txt for details.
[all …]
/kernel/linux/linux-6.6/include/sound/sof/
Ddai-intel.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
39 /* mclk 0 disable */
41 /* mclk 1 disable */
43 /* mclk keep active */
51 /* mclk early start */
55 /* mclk always on */
61 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
67 uint32_t mclk_rate; /* mclk frequency in Hz */
68 uint32_t fsync_rate; /* fsync frequency in Hz */
69 uint32_t bclk_rate; /* bclk frequency in Hz */
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dda9055.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C
59 /* Input - Gain, Select and Filter Registers */
72 /* Output - Gain, Select and Filter Registers */
251 {11289600, 2822400, 0x00, 0x00, 0x20, 1}, /* MCLK=11.2896Mhz */
252 {12000000, 2822400, 0x03, 0x61, 0x1E, 1}, /* MCLK=12Mhz */
253 {12288000, 2822400, 0x0C, 0xCC, 0x1D, 1}, /* MCLK=12.288Mhz */
254 {13000000, 2822400, 0x19, 0x45, 0x1B, 1}, /* MCLK=13Mhz */
255 {13500000, 2822400, 0x18, 0x56, 0x1A, 1}, /* MCLK=13.5Mhz */
256 {14400000, 2822400, 0x02, 0xD0, 0x19, 1}, /* MCLK=14.4Mhz */
[all …]
Dcs4270.c6 * Copyright 2007-2009 Freescale Semiconductor, Inc. This file is licensed
15 * - Software mode is supported. Stand-alone mode is not supported.
16 * - Only I2C is supported, not SPI
17 * - Support for master and slave mode
18 * - The machine driver's 'startup' function must call
19 * cs4270_set_dai_sysclk() with the value of MCLK.
20 * - Only I2S and left-justified modes are supported
21 * - Power management is supported
36 * The codec isn't really big-endian or little-endian, since the I2S
39 * way, ALSA will always match the bit patterns.
[all …]
Dwm8988.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8988.c -- WM8988 ALSA SoC audio driver
129 static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
137 static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
167 static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
168 static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
169 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
170 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
171 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
180 SOC_ENUM("Treble Cut-off", treble),
[all …]
Dda7210.c1 // SPDX-License-Identifier: GPL-2.0+
11 // Tested on SuperH Ecovec24 board with S16/S24 LE in 48KHz using I2S
223 { 12000000, 2822400, 0xE8, 0x6C, 0x2, 1}, /* MCLK=12Mhz */
224 { 13000000, 2822400, 0xDF, 0x28, 0xC, 1}, /* MCLK=13Mhz */
225 { 13500000, 2822400, 0xDB, 0x0A, 0xD, 1}, /* MCLK=13.5Mhz */
226 { 14400000, 2822400, 0xD4, 0x5A, 0x2, 1}, /* MCLK=14.4Mhz */
227 { 19200000, 2822400, 0xBB, 0x43, 0x9, 1}, /* MCLK=19.2Mhz */
228 { 19680000, 2822400, 0xB9, 0x6D, 0xA, 1}, /* MCLK=19.68Mhz */
229 { 19800000, 2822400, 0xB8, 0xFB, 0xB, 1}, /* MCLK=19.8Mhz */
231 { 12000000, 3072000, 0xF3, 0x12, 0x7, 1}, /* MCLK=12Mhz */
[all …]
Dnau8825.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
34 #define NUVOTON_CODEC_DAI "nau8825-hifi"
64 /* scaling for mclk from sysclk_src output */
99 /* over sampling rate */
238 * nau8825_sema_acquire - acquire the semaphore of nau88l25
248 * this function returns -ETIME. If the sleep is interrupted by a signal,
249 * this function will return -EINTR. It returns 0 if the semaphore was
261 ret = down_timeout(&nau8825->xtalk_sem, timeout); in nau8825_sema_acquire()
263 dev_warn(nau8825->dev, "Acquire semaphore timeout\n"); in nau8825_sema_acquire()
[all …]
Dwm8994.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8994.c -- WM8994 ALSA SoC Audio driver
5 * Copyright 2009-12 Wolfson Microelectronics plc
77 /* VU bitfields for ADC2, DAC2 not available on WM1811 */
114 struct wm8994 *control = wm8994->wm8994; in wm8958_micd_set_rate()
120 idle = !wm8994->jack_mic; in wm8958_micd_set_rate()
124 sysclk = wm8994->aifclk[1]; in wm8958_micd_set_rate()
126 sysclk = wm8994->aifclk[0]; in wm8958_micd_set_rate()
128 if (control->pdata.micd_rates) { in wm8958_micd_set_rate()
129 rates = control->pdata.micd_rates; in wm8958_micd_set_rate()
[all …]
Dmadera.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
18 #include <linux/irqchip/irq-madera.h>
22 #include <sound/madera-pdata.h>
24 #include <dt-bindings/sound/madera.h>
143 dev_err(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
145 dev_warn(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
147 dev_dbg(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
150 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
152 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
[all …]
/kernel/linux/linux-6.6/sound/soc/codecs/
Dda9055.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C
59 /* Input - Gain, Select and Filter Registers */
72 /* Output - Gain, Select and Filter Registers */
251 {11289600, 2822400, 0x00, 0x00, 0x20, 1}, /* MCLK=11.2896Mhz */
252 {12000000, 2822400, 0x03, 0x61, 0x1E, 1}, /* MCLK=12Mhz */
253 {12288000, 2822400, 0x0C, 0xCC, 0x1D, 1}, /* MCLK=12.288Mhz */
254 {13000000, 2822400, 0x19, 0x45, 0x1B, 1}, /* MCLK=13Mhz */
255 {13500000, 2822400, 0x18, 0x56, 0x1A, 1}, /* MCLK=13.5Mhz */
256 {14400000, 2822400, 0x02, 0xD0, 0x19, 1}, /* MCLK=14.4Mhz */
[all …]
Dwm8988.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8988.c -- WM8988 ALSA SoC audio driver
129 static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
137 static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
167 static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
168 static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
169 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
170 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
171 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
180 SOC_ENUM("Treble Cut-off", treble),
[all …]
Dda7210.c1 // SPDX-License-Identifier: GPL-2.0+
11 // Tested on SuperH Ecovec24 board with S16/S24 LE in 48KHz using I2S
223 { 12000000, 2822400, 0xE8, 0x6C, 0x2, 1}, /* MCLK=12Mhz */
224 { 13000000, 2822400, 0xDF, 0x28, 0xC, 1}, /* MCLK=13Mhz */
225 { 13500000, 2822400, 0xDB, 0x0A, 0xD, 1}, /* MCLK=13.5Mhz */
226 { 14400000, 2822400, 0xD4, 0x5A, 0x2, 1}, /* MCLK=14.4Mhz */
227 { 19200000, 2822400, 0xBB, 0x43, 0x9, 1}, /* MCLK=19.2Mhz */
228 { 19680000, 2822400, 0xB9, 0x6D, 0xA, 1}, /* MCLK=19.68Mhz */
229 { 19800000, 2822400, 0xB8, 0xFB, 0xB, 1}, /* MCLK=19.8Mhz */
231 { 12000000, 3072000, 0xF3, 0x12, 0x7, 1}, /* MCLK=12Mhz */
[all …]
Dwm8994.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8994.c -- WM8994 ALSA SoC Audio driver
5 * Copyright 2009-12 Wolfson Microelectronics plc
77 /* VU bitfields for ADC2, DAC2 not available on WM1811 */
114 struct wm8994 *control = wm8994->wm8994; in wm8958_micd_set_rate()
120 idle = !wm8994->jack_mic; in wm8958_micd_set_rate()
124 sysclk = wm8994->aifclk[1]; in wm8958_micd_set_rate()
126 sysclk = wm8994->aifclk[0]; in wm8958_micd_set_rate()
128 if (control->pdata.micd_rates) { in wm8958_micd_set_rate()
129 rates = control->pdata.micd_rates; in wm8958_micd_set_rate()
[all …]
Dmadera.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
18 #include <linux/irqchip/irq-madera.h>
22 #include <sound/madera-pdata.h>
24 #include <dt-bindings/sound/madera.h>
143 dev_err(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
145 dev_warn(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
147 dev_dbg(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
150 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
152 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
[all …]
/kernel/linux/linux-6.6/sound/soc/stm/
Dstm32_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
11 #include <linux/clk-provider.h>
136 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
137 I2S_CGFR_I2SDIV_SHIFT)) - 1)
198 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
199 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
205 * struct stm32_i2s_data - private data of I2S
214 * @i2smclk: master clock from I2S mclk provider
222 * @mclk_rate: master clock frequency (Hz)
[all …]
/kernel/linux/linux-6.6/sound/aoa/soundbus/i2sbus/
Dpcm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2sbus driver -- pcm routines
23 *pi = &i2sdev->in; in get_pcm_info()
25 *other = &i2sdev->out; in get_pcm_info()
28 *pi = &i2sdev->out; in get_pcm_info()
30 *other = &i2sdev->in; in get_pcm_info()
34 static int clock_and_divisors(int mclk, int sclk, int rate, int *out) in clock_and_divisors() argument
36 /* sclk must be derived from mclk! */ in clock_and_divisors()
37 if (mclk % sclk) in clock_and_divisors()
38 return -1; in clock_and_divisors()
[all …]
/kernel/linux/linux-5.10/sound/aoa/soundbus/i2sbus/
Dpcm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2sbus driver -- pcm routines
23 *pi = &i2sdev->in; in get_pcm_info()
25 *other = &i2sdev->out; in get_pcm_info()
28 *pi = &i2sdev->out; in get_pcm_info()
30 *other = &i2sdev->in; in get_pcm_info()
34 static int clock_and_divisors(int mclk, int sclk, int rate, int *out) in clock_and_divisors() argument
36 /* sclk must be derived from mclk! */ in clock_and_divisors()
37 if (mclk % sclk) in clock_and_divisors()
38 return -1; in clock_and_divisors()
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/
Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
19 stdout-path = "serial2:115200n8";
28 * - Rails that only connect to the EC (or devices that the EC talks to)
30 * - Rails _are_ included if the rails go to the AP even if the AP
31 * doesn't currently care about them / they are always on. The idea
39 * - The EC controls the enable and the EC always enables a rail as
41 * - The rails are actually connected to each other by a jumper and
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Dmmci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
6 * Copyright (C) 2010 ST-Ericsson SA
26 #include <linux/mmc/slot-gpio.h>
33 #include <linux/dma-mapping.h>
45 #define DRIVER_NAME "mmci-pl18x"
341 spin_lock_irqsave(&host->lock, flags); in mmci_card_busy()
342 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) in mmci_card_busy()
344 spin_unlock_irqrestore(&host->lock, flags); in mmci_card_busy()
354 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. in mmci_reg_delay()
[all …]
/kernel/linux/linux-6.6/drivers/mmc/host/
Dmmci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
6 * Copyright (C) 2010 ST-Ericsson SA
26 #include <linux/mmc/slot-gpio.h>
33 #include <linux/dma-mapping.h>
47 #define DRIVER_NAME "mmci-pl18x"
373 spin_lock_irqsave(&host->lock, flags); in mmci_card_busy()
374 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) in mmci_card_busy()
376 spin_unlock_irqrestore(&host->lock, flags); in mmci_card_busy()
386 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. in mmci_reg_delay()
[all …]
Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
23 #include "sdhci-cqhci.h"
24 #include "sdhci-pltfm.h"
123 #define INVALID_TUNING_PHASE -1
140 /* Max load for eMMC Vdd-io supply */
146 /* Max load for SD Vdd-io supply */
150 msm_host->var_ops->msm_readl_relaxed(host, offset)
153 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
[all …]
/kernel/linux/linux-5.10/sound/soc/stm/
Dstm32_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
134 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
135 I2S_CGFR_I2SDIV_SHIFT)) - 1)
196 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
197 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
200 * struct stm32_i2s_data - private data of I2S
216 * @mclk_rate: master clock frequency (Hz)
218 * @refcount: keep count of opened streams on I2S
246 struct platform_device *pdev = i2s->pdev; in stm32_i2s_isr()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/arm/
Dmalidp_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
28 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_mode_valid()
31 * check that the hardware can drive the required clock rate, in malidp_crtc_mode_valid()
34 long rate, req_rate = mode->crtc_clock * 1000; in malidp_crtc_mode_valid() local
37 rate = clk_round_rate(hwdev->pxlclk, req_rate); in malidp_crtc_mode_valid()
38 if (rate != req_rate) { in malidp_crtc_mode_valid()
39 DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n", in malidp_crtc_mode_valid()
52 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_atomic_enable()
54 int err = pm_runtime_get_sync(crtc->dev->dev); in malidp_crtc_atomic_enable()
61 drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm); in malidp_crtc_atomic_enable()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/arm/
Dmalidp_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
29 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_mode_valid()
32 * check that the hardware can drive the required clock rate, in malidp_crtc_mode_valid()
35 long rate, req_rate = mode->crtc_clock * 1000; in malidp_crtc_mode_valid() local
38 rate = clk_round_rate(hwdev->pxlclk, req_rate); in malidp_crtc_mode_valid()
39 if (rate != req_rate) { in malidp_crtc_mode_valid()
40 DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n", in malidp_crtc_mode_valid()
53 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_atomic_enable()
55 int err = pm_runtime_get_sync(crtc->dev->dev); in malidp_crtc_atomic_enable()
62 drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm); in malidp_crtc_atomic_enable()
[all …]
/kernel/linux/linux-6.6/drivers/iio/adc/
Dad4130.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
125 #define AD4130_INVALID_SLOT -1
137 [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3,
138 [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2,
139 [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
140 [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
141 [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
269 struct clk *mclk; member
397 return -EINVAL; in ad4130_get_reg_size()
[all …]

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