Home
last modified time | relevance | path

Searched +full:0 +full:- +full:7 +full:a +full:- +full:e (Results 1 – 25 of 1113) sorted by relevance

12345678910>>...45

/kernel/linux/linux-6.6/arch/alpha/lib/
Dev6-memset.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memset.S
8 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
13 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
15 * E - either cluster
16 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
23 * A future enhancement might be to put in a byte store loop for really
25 * a win in the kernel would depend upon the contextual usage.
43 .frame $30,0,$26,0
[all …]
Dev6-memcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memcpy.S
4 * 21264 version by Rick Gorton <rick.gorton@alpha-processor.com>
8 * - memory accessed as aligned quadwords only
9 * - uses bcmpge to compare 8 bytes in parallel
14 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
16 * E - either cluster
17 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
21 * $1,$2, - scratch
[all …]
Dev6-csum_ipv6_magic.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
29 * Swap <proto> (takes form 0xaabb)
31 * 0xbbaa0000 00000000
32 * Then turn it back into a sign extended 32-bit item
[all …]
/kernel/linux/linux-5.10/arch/alpha/lib/
Dev6-memset.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memset.S
8 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
13 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
15 * E - either cluster
16 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
23 * A future enhancement might be to put in a byte store loop for really
25 * a win in the kernel would depend upon the contextual usage.
43 .frame $30,0,$26,0
[all …]
Dev6-memcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memcpy.S
4 * 21264 version by Rick Gorton <rick.gorton@alpha-processor.com>
8 * - memory accessed as aligned quadwords only
9 * - uses bcmpge to compare 8 bytes in parallel
14 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
16 * E - either cluster
17 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
21 * $1,$2, - scratch
[all …]
Dev6-csum_ipv6_magic.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
29 * Swap <proto> (takes form 0xaabb)
31 * 0xbbaa0000 00000000
32 * Then turn it back into a sign extended 32-bit item
[all …]
/kernel/linux/linux-5.10/arch/powerpc/crypto/
Daes-tab-4k.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * crypto/aes_generic.c and are designed to be simply accessed by a combination
11 * of rlwimi/lwz instructions with a minimum of table registers (usually only
14 * instructions. E.g. evldw, evlwwsplat, ...
16 * For the safety-conscious it has to be noted that they might be vulnerable
19 * This is a quite good tradeoff for low power devices (e.g. routers) without
25 #define R(a, b, c, d) \ argument
26 0x##a##b##c##d, 0x##d##a##b##c, 0x##c##d##a##b, 0x##b##c##d##a
32 /* encryption table, same as crypto_ft_tab in crypto/aes-generic.c */
33 .long R(c6, 63, 63, a5), R(f8, 7c, 7c, 84)
[all …]
/kernel/linux/linux-6.6/arch/powerpc/crypto/
Daes-tab-4k.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * crypto/aes_generic.c and are designed to be simply accessed by a combination
11 * of rlwimi/lwz instructions with a minimum of table registers (usually only
14 * instructions. E.g. evldw, evlwwsplat, ...
16 * For the safety-conscious it has to be noted that they might be vulnerable
19 * This is a quite good tradeoff for low power devices (e.g. routers) without
25 #define R(a, b, c, d) \ argument
26 0x##a##b##c##d, 0x##d##a##b##c, 0x##c##d##a##b, 0x##b##c##d##a
32 /* encryption table, same as crypto_ft_tab in crypto/aes-generic.c */
33 .long R(c6, 63, 63, a5), R(f8, 7c, 7c, 84)
[all …]
/kernel/linux/linux-5.10/arch/m68k/fpsp040/
Dtbldo.S10 | index with a 10-bit index, with the first
11 | 7 bits the opcode, and the remaining 3
46 | instruction ;opcode-stag Notes
49 .long smovcr |$00-0 fmovecr all
50 .long smovcr |$00-1 fmovecr all
51 .long smovcr |$00-2 fmovecr all
52 .long smovcr |$00-3 fmovecr all
53 .long smovcr |$00-4 fmovecr all
54 .long smovcr |$00-5 fmovecr all
55 .long smovcr |$00-6 fmovecr all
[all …]
/kernel/linux/linux-6.6/arch/m68k/fpsp040/
Dtbldo.S10 | index with a 10-bit index, with the first
11 | 7 bits the opcode, and the remaining 3
46 | instruction ;opcode-stag Notes
49 .long smovcr |$00-0 fmovecr all
50 .long smovcr |$00-1 fmovecr all
51 .long smovcr |$00-2 fmovecr all
52 .long smovcr |$00-3 fmovecr all
53 .long smovcr |$00-4 fmovecr all
54 .long smovcr |$00-5 fmovecr all
55 .long smovcr |$00-6 fmovecr all
[all …]
/kernel/linux/linux-6.6/tools/testing/selftests/hid/tests/
Dtest_multitouch.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
20 KERNEL_MODULE = ("hid-multitouch", "hid_multitouch")
28 "NOT_SEEN_MEANS_UP": BIT(0),
35 "CONFIDENCE": BIT(7),
66 self.azimuth = 0
74 super().__init__(0, x, y)
80 self.twist = 0
91 Usage Page (0xff00)
92 Usage (0xc5)
[all …]
/kernel/linux/linux-5.10/arch/x86/crypto/
Dsha1_avx2_x86_64_asm.S2 * Implement fast SHA-1 with AVX2 instructions. (x86_64)
4 * This file is provided under a dual BSD/GPLv2 license. When using or
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
47 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
59 * SHA-1 implementation with Intel(R) AVX2 instruction set extensions.
62 *Visit http://software.intel.com/en-us/articles/
63 *and refer to improving-the-performance-of-the-secure-hash-algorithm-1/
65 *Updates 20-byte SHA-1 record at start of 'state', from 'input', for
66 *even number of 'blocks' consecutive 64-byte blocks.
100 .set A, REG_A define
[all …]
Dsha512-avx2-asm.S2 # Implement fast SHA-512 with AVX2 instructions. (x86_64)
12 # This software is available to you under a choice of one of two
22 # - Redistributions of source code must retain the above
26 # - Redistributions in binary form must reproduce the above
33 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
49 # This code schedules 1 blocks at a time, with 4 lanes per block
81 e = %rdx define
86 a = %rax define
[all …]
Dsha256-avx-asm.S2 # Implement fast SHA-256 with AVX1 instructions. (x86_64)
11 # This software is available to you under a choice of one of two
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 # This code is described in an Intel White-Paper:
41 # "Fast SHA-256 Implementations on Intel Architecture Processors"
47 # This code schedules 1 block at a time, with 4 lanes per block
58 # Add reg to mem using reg-mem add and store
66 shld $(32-(\p1)), \p2, \p2
[all …]
Dsha256-ssse3-asm.S2 # Implement fast SHA-256 with SSSE3 instructions. (x86_64)
11 # This software is available to you under a choice of one of two
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
57 # Add reg to mem using reg-mem add and store
86 SHUF_00BA = %xmm10 # shuffle xBxA -> 00BA
87 SHUF_DC00 = %xmm11 # shuffle xDxC -> DC00
[all …]
/kernel/linux/linux-6.6/arch/x86/crypto/
Dsha1_avx2_x86_64_asm.S2 * Implement fast SHA-1 with AVX2 instructions. (x86_64)
4 * This file is provided under a dual BSD/GPLv2 license. When using or
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
47 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
59 * SHA-1 implementation with Intel(R) AVX2 instruction set extensions.
62 *Visit http://software.intel.com/en-us/articles/
63 *and refer to improving-the-performance-of-the-secure-hash-algorithm-1/
65 *Updates 20-byte SHA-1 record at start of 'state', from 'input', for
66 *even number of 'blocks' consecutive 64-byte blocks.
100 .set A, REG_A define
[all …]
Dsha512-avx2-asm.S2 # Implement fast SHA-512 with AVX2 instructions. (x86_64)
12 # This software is available to you under a choice of one of two
22 # - Redistributions of source code must retain the above
26 # - Redistributions in binary form must reproduce the above
33 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
49 # This code schedules 1 blocks at a time, with 4 lanes per block
82 e = %rdx define
87 a = %rax define
[all …]
Dsha256-avx-asm.S2 # Implement fast SHA-256 with AVX1 instructions. (x86_64)
11 # This software is available to you under a choice of one of two
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 # This code is described in an Intel White-Paper:
41 # "Fast SHA-256 Implementations on Intel Architecture Processors"
47 # This code schedules 1 block at a time, with 4 lanes per block
59 # Add reg to mem using reg-mem add and store
67 shld $(32-(\p1)), \p2, \p2
[all …]
Dsha256-ssse3-asm.S2 # Implement fast SHA-256 with SSSE3 instructions. (x86_64)
11 # This software is available to you under a choice of one of two
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
58 # Add reg to mem using reg-mem add and store
87 SHUF_00BA = %xmm10 # shuffle xBxA -> 00BA
88 SHUF_DC00 = %xmm11 # shuffle xDxC -> DC00
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/st/
Dstm32mp15-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
9 adc1_ain_pins_a: adc1-ain-0 {
13 <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
14 <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
16 <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1_INP15 */
20 adc1_in6_pins_a: adc1-in6-0 {
26 adc12_ain_pins_a: adc12-ain-0 {
35 adc12_ain_pins_b: adc12-ain-1 {
[all …]
/kernel/linux/linux-6.6/lib/crypto/
Dsha256.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SHA-256, as specified in
4 * http://csrc.nist.gov/groups/STM/cavp/documents/shs/sha256-384-512.pdf
6 * SHA-256 code by Jean-Luc Cooke <jlcooke@certainkey.com>.
8 * Copyright (c) Jean-Luc Cooke <jlcooke@certainkey.com>
21 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,
22 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,
23 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
24 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174,
25 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc,
[all …]
/kernel/linux/linux-6.6/arch/mips/include/asm/
Dpgtable-32.h19 #include <asm-generic/pgtable-nopmd.h>
26 * Regarding 32-bit MIPS huge page support (and the tradeoff it entails):
28 * We use the same huge page sizes as 64-bit MIPS. Assuming a 4KB page size,
29 * our 2-level table layout would normally have a PGD entry cover a contiguous
30 * 4MB virtual address region (pointing to a 4KB PTE page of 1,024 32-bit pte_t
31 * pointers, each pointing to a 4KB physical page). The problem is that 4MB,
32 * spanning both halves of a TLB EntryLo0,1 pair, requires 2MB hardware page
35 * pointers a PTE page holds, making its last half go to waste. Correspondingly,
37 * increases to match 64-bit MIPS, but PTE lookups remain CPU cache-friendly.
39 * NOTE: We don't yet support huge pages if extended-addressing is enabled
[all …]
/kernel/linux/linux-6.6/arch/arm/crypto/
Dsha1-armv4-large.S2 @ SPDX-License-Identifier: GPL-2.0
23 @ Size/performance trade-off
28 @ armv4-small 392/+29% 1958/+64% 2250/+96%
29 @ armv4-compact 740/+89% 1552/+26% 1840/+22%
30 @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
42 @ i-cache availability, branch penalties, etc.
44 @ diverse as ARM ones: e.g., there are only two arithmetic
49 @ [***] which is also ~35% better than compiler generated code. Dual-
55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
61 @ Profiler-assisted and platform-specific optimization resulted in 10%
[all …]
/kernel/linux/linux-5.10/arch/arm/crypto/
Dsha1-armv4-large.S2 @ SPDX-License-Identifier: GPL-2.0
23 @ Size/performance trade-off
28 @ armv4-small 392/+29% 1958/+64% 2250/+96%
29 @ armv4-compact 740/+89% 1552/+26% 1840/+22%
30 @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
42 @ i-cache availability, branch penalties, etc.
44 @ diverse as ARM ones: e.g., there are only two arithmetic
49 @ [***] which is also ~35% better than compiler generated code. Dual-
55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
61 @ Profiler-assisted and platform-specific optimization resulted in 10%
[all …]
Dsha256-core.S_shipped1 @ SPDX-License-Identifier: GPL-2.0
20 @ Performance is ~2x better than gcc 3.4 generated code and in "abso-
21 @ lute" terms is ~2250 cycles per 64-byte block or ~35 cycles per
22 @ byte [on single-issue Xscale PXA250 core].
26 @ Rescheduling for dual-issue pipeline resulted in 22% improvement on
31 @ Profiler-assisted and platform-specific optimization resulted in 16%
37 @ byte in 12.5 cycles or 23% faster than integer-only code. Snapdragon
38 @ S4 does it in 12.5 cycles too, but it's 50% faster than integer-only
39 @ code (meaning that latter performs sub-optimally, nothing was done
50 # define __ARM_MAX_ARCH__ 7
[all …]

12345678910>>...45