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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #define LP_OPTIONS 0
20 * If page size and eraseblock size are 0, the sizes are taken from the
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
30 { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
33 { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
[all …]
/kernel/linux/linux-6.6/drivers/mtd/nand/raw/
Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #define LP_OPTIONS 0
20 * If page size and eraseblock size are 0, the sizes are taken from the
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
30 { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
33 { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
[all …]
/kernel/linux/linux-5.10/include/dt-bindings/iio/
Dqcom,spmi-adc7-pm8350b.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | 0x0)
15 #define PM8350B_ADC7_1P25VREF (PM8350B_SID << 8 | 0x01)
16 #define PM8350B_ADC7_VREF_VADC (PM8350B_SID << 8 | 0x02)
17 #define PM8350B_ADC7_DIE_TEMP (PM8350B_SID << 8 | 0x03)
19 #define PM8350B_ADC7_AMUX_THM1 (PM8350B_SID << 8 | 0x04)
20 #define PM8350B_ADC7_AMUX_THM2 (PM8350B_SID << 8 | 0x05)
21 #define PM8350B_ADC7_AMUX_THM3 (PM8350B_SID << 8 | 0x06)
22 #define PM8350B_ADC7_AMUX_THM4 (PM8350B_SID << 8 | 0x07)
23 #define PM8350B_ADC7_AMUX_THM5 (PM8350B_SID << 8 | 0x08)
[all …]
Dqcom,spmi-adc7-pm8350.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #define PM8350_ADC7_REF_GND (PM8350_SID << 8 | 0x0)
15 #define PM8350_ADC7_1P25VREF (PM8350_SID << 8 | 0x01)
16 #define PM8350_ADC7_VREF_VADC (PM8350_SID << 8 | 0x02)
17 #define PM8350_ADC7_DIE_TEMP (PM8350_SID << 8 | 0x03)
19 #define PM8350_ADC7_AMUX_THM1 (PM8350_SID << 8 | 0x04)
20 #define PM8350_ADC7_AMUX_THM2 (PM8350_SID << 8 | 0x05)
21 #define PM8350_ADC7_AMUX_THM3 (PM8350_SID << 8 | 0x06)
22 #define PM8350_ADC7_AMUX_THM4 (PM8350_SID << 8 | 0x07)
23 #define PM8350_ADC7_AMUX_THM5 (PM8350_SID << 8 | 0x08)
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/
Dwii-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/wii-head.S
6 * Copyright (C) 2008-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
16 * - if the high BATs are enabled or not
29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
32 mflr 8
33 clrlwi 8, 8, 3 /* convert to a real address */
34 addi 8, 8, _mmu_off - 1b
[all …]
Dgamecube-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/gamecube-head.S
6 * Copyright (C) 2004-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
28 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
31 mflr 8
32 clrlwi 8, 8, 3 /* convert to a real address */
33 addi 8, 8, _mmu_off - 1b
34 mtsrr0 8
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/
Dwii-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/wii-head.S
6 * Copyright (C) 2008-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
16 * - if the high BATs are enabled or not
29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
32 mflr 8
33 clrlwi 8, 8, 3 /* convert to a real address */
34 addi 8, 8, _mmu_off - 1b
[all …]
Dgamecube-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/gamecube-head.S
6 * Copyright (C) 2004-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
28 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
31 mflr 8
32 clrlwi 8, 8, 3 /* convert to a real address */
33 addi 8, 8, _mmu_off - 1b
34 mtsrr0 8
[all …]
/kernel/linux/linux-6.6/Documentation/driver-api/media/drivers/ccs/
Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
19 module_model_id 0x0000 16
20 module_revision_number_major 0x0002 8
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/
Dmdp_format.c1 // SPDX-License-Identifier: GPL-2.0-only
16 0x0200, 0x0000, 0x0000,
17 0x0000, 0x0200, 0x0000,
18 0x0000, 0x0000, 0x0200
20 .pre_bias = { 0x0, 0x0, 0x0 },
21 .post_bias = { 0x0, 0x0, 0x0 },
22 .pre_clamp = { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff },
23 .post_clamp = { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff },
28 0x0254, 0x0000, 0x0331,
29 0x0254, 0xff37, 0xfe60,
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/
Dmdp_format.c1 // SPDX-License-Identifier: GPL-2.0-only
18 0x0200, 0x0000, 0x0000,
19 0x0000, 0x0200, 0x0000,
20 0x0000, 0x0000, 0x0200
22 .pre_bias = { 0x0, 0x0, 0x0 },
23 .post_bias = { 0x0, 0x0, 0x0 },
24 .pre_clamp = { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff },
25 .post_clamp = { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff },
30 0x0254, 0x0000, 0x0331,
31 0x0254, 0xff37, 0xfe60,
[all …]
/kernel/linux/linux-5.10/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
[all …]
/kernel/linux/linux-6.6/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
[all …]
/kernel/linux/linux-6.6/arch/powerpc/perf/
Dhv-gpci-requests.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 #include "req-gen/_begin.h"
22 * - starting_index_kind is one of the following, depending on the event:
24 * hw_chip_id: hardware chip id or -1 for current hw chip
28 * 0xffffffffffffffff: or -1, which means it is irrelavant for the event
43 * - expose secondary index (if any counter ever uses it, only 0xA0
45 * - embed versioning info
46 * - include counter descriptions
49 #define REQUEST_NUM 0x10
52 REQUEST(__count(0, 8, processor_time_in_timebase_cycles)
[all …]
/kernel/linux/linux-5.10/arch/powerpc/perf/
Dhv-gpci-requests.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 #include "req-gen/_begin.h"
22 * - starting_index_kind is one of the following, depending on the event:
24 * hw_chip_id: hardware chip id or -1 for current hw chip
28 * 0xffffffffffffffff: or -1, which means it is irrelavant for the event
43 * - expose secondary index (if any counter ever uses it, only 0xA0
45 * - embed versioning info
46 * - include counter descriptions
49 #define REQUEST_NUM 0x10
52 REQUEST(__count(0, 8, processor_time_in_timebase_cycles)
[all …]
/kernel/linux/linux-5.10/fs/cifs/
Dcifs_uniupr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * uniupr.h - Unicode compressed case ranges
13 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 000-00f */
14 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 010-01f */
15 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 020-02f */
16 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 030-03f */
17 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 040-04f */
18 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 050-05f */
19 0, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32, /* 060-06f */
20 -32, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32, 0, 0, 0, 0, 0, /* 070-07f */
[all …]
/kernel/linux/linux-6.6/drivers/mfd/
Dmt6370.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #define MT6370_REG_DEV_INFO 0x100
20 #define MT6370_REG_CHG_IRQ1 0x1C0
21 #define MT6370_REG_CHG_MASK1 0x1E0
22 #define MT6370_REG_MAXADDR 0x1FF
27 #define MT6370_USBC_I2CADDR 0x4E
30 #define MT6370_VENID_RT5081 0x8
31 #define MT6370_VENID_RT5081A 0xA
32 #define MT6370_VENID_MT6370 0xE
33 #define MT6370_VENID_MT6371 0xF
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-davinci/
Dda830.c11 #include <linux/clk-provider.h>
16 #include <linux/irqchip/irq-davinci-cp-intc.h>
17 #include <linux/platform_data/gpio-davinci.h>
25 #include <clocksource/timer-davinci.h>
30 /* Offsets of the 8 compare registers on the da830 */
31 #define DA830_CMP12_0 0x60
32 #define DA830_CMP12_1 0x64
33 #define DA830_CMP12_2 0x68
34 #define DA830_CMP12_3 0x6c
35 #define DA830_CMP12_4 0x70
[all …]
/kernel/linux/linux-5.10/fs/jfs/
Djfs_uniupr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) International Business Machines Corp., 2000-2002
13 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 000-00f */
14 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 010-01f */
15 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 020-02f */
16 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 030-03f */
17 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 040-04f */
18 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 050-05f */
19 0,-32,-32,-32,-32,-32,-32,-32,-32,-32,-32,-32,-32,-32,-32,-32, /* 060-06f */
20 -32,-32,-32,-32,-32,-32,-32,-32,-32,-32,-32, 0, 0, 0, 0, 0, /* 070-07f */
[all …]
/kernel/linux/linux-6.6/fs/nls/
Dnls_ucs2_utils.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 000-00f */
26 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 010-01f */
27 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 020-02f */
28 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 030-03f */
29 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 040-04f */
30 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 050-05f */
31 0, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
32 -32, -32, -32, -32, -32, /* 060-06f */
33 -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
62 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
64 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
62 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
64 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
[all …]
/kernel/linux/linux-6.6/Documentation/gpu/
Dafbc.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
31 * Component 0: R
36 fourcc:modifier pair. In general, component '0' is considered to
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
[all …]
/kernel/linux/linux-5.10/Documentation/gpu/
Dafbc.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
31 * Component 0: R
36 fourcc:modifier pair. In general, component '0' is considered to
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-davinci/
Dda830.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <linux/irqchip/irq-davinci-cp-intc.h>
16 #include <clocksource/timer-davinci.h>
26 /* Offsets of the 8 compare registers on the da830 */
27 #define DA830_CMP12_0 0x60
28 #define DA830_CMP12_1 0x64
29 #define DA830_CMP12_2 0x68
30 #define DA830_CMP12_3 0x6c
31 #define DA830_CMP12_4 0x70
[all …]

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