| /kernel/linux/linux-5.10/drivers/pinctrl/spear/ |
| D | pinctrl-spear300.c | 21 #define PMX_CONFIG_REG 0x00 22 #define MODE_CONFIG_REG 0x04 25 #define NAND_MODE (1 << 0) 43 .mask = 0x0000000F, 44 .val = 0x00, 51 .mask = 0x0000000F, 52 .val = 0x01, 59 .mask = 0x0000000F, 60 .val = 0x02, 67 .mask = 0x0000000F, [all …]
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| /kernel/linux/linux-6.6/drivers/pinctrl/spear/ |
| D | pinctrl-spear300.c | 21 #define PMX_CONFIG_REG 0x00 22 #define MODE_CONFIG_REG 0x04 25 #define NAND_MODE (1 << 0) 43 .mask = 0x0000000F, 44 .val = 0x00, 51 .mask = 0x0000000F, 52 .val = 0x01, 59 .mask = 0x0000000F, 60 .val = 0x02, 67 .mask = 0x0000000F, [all …]
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| /kernel/linux/linux-5.10/arch/x86/kernel/cpu/ |
| D | scattered.c | 27 { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, 28 { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, 29 { X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 }, 30 { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 }, 31 { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 }, 32 { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 }, 33 { X86_FEATURE_CQM_MBM_LOCAL, CPUID_EDX, 2, 0x0000000f, 1 }, 34 { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 }, 35 { X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 }, 36 { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 }, [all …]
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| /kernel/linux/linux-6.6/arch/x86/kernel/cpu/ |
| D | scattered.c | 27 { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, 28 { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, 29 { X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 }, 30 { X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 }, 31 { X86_FEATURE_BHI_CTRL, CPUID_EDX, 4, 0x00000007, 2 }, 32 { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 }, 33 { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 }, 34 { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 }, 35 { X86_FEATURE_CQM_MBM_LOCAL, CPUID_EDX, 2, 0x0000000f, 1 }, 36 { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 }, [all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/ |
| D | bif_3_0_sh_mask.h | 26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L 27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007 28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L 29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001 30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L 31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000 32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L 33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005 34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L 35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002 [all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/bif/ |
| D | bif_3_0_sh_mask.h | 26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L 27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007 28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L 29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001 30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L 31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000 32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L 33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005 34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L 35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002 [all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | tegra124-nyan-blaze-emc.dtsi | 78 nvidia,emc-auto-cal-config = <0xa1430000>; 79 nvidia,emc-auto-cal-config2 = <0x00000000>; 80 nvidia,emc-auto-cal-config3 = <0x00000000>; 81 nvidia,emc-auto-cal-interval = <0x001fffff>; 82 nvidia,emc-bgbias-ctl0 = <0x00000008>; 83 nvidia,emc-cfg = <0x73240000>; 84 nvidia,emc-cfg-2 = <0x000008c5>; 85 nvidia,emc-ctt-term-ctrl = <0x00000802>; 86 nvidia,emc-mode-1 = <0x80100003>; 87 nvidia,emc-mode-2 = <0x80200008>; [all …]
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| D | tegra124-apalis-emc.dtsi | 94 nvidia,emc-auto-cal-config = <0xa1430000>; 95 nvidia,emc-auto-cal-config2 = <0x00000000>; 96 nvidia,emc-auto-cal-config3 = <0x00000000>; 97 nvidia,emc-auto-cal-interval = <0x001fffff>; 98 nvidia,emc-bgbias-ctl0 = <0x00000008>; 99 nvidia,emc-cfg = <0x73240000>; 100 nvidia,emc-cfg-2 = <0x000008c5>; 101 nvidia,emc-ctt-term-ctrl = <0x00000802>; 102 nvidia,emc-mode-1 = <0x80100003>; 103 nvidia,emc-mode-2 = <0x80200008>; [all …]
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| D | tegra124-jetson-tk1-emc.dtsi | 89 nvidia,emc-auto-cal-config = <0xa1430000>; 90 nvidia,emc-auto-cal-config2 = <0x00000000>; 91 nvidia,emc-auto-cal-config3 = <0x00000000>; 92 nvidia,emc-auto-cal-interval = <0x001fffff>; 93 nvidia,emc-bgbias-ctl0 = <0x00000008>; 94 nvidia,emc-cfg = <0x73240000>; 95 nvidia,emc-cfg-2 = <0x000008c5>; 96 nvidia,emc-ctt-term-ctrl = <0x00000802>; 97 nvidia,emc-mode-1 = <0x80100003>; 98 nvidia,emc-mode-2 = <0x80200008>; [all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/ |
| D | tegra30-asus-tf700t.dts | 18 port@0 { 92 reg = <0x10>; 111 mount-matrix = "1", "0", "0", 112 "0", "-1", "0", 113 "0", "0", "-1"; 117 mount-matrix = "0", "1", "0", 118 "1", "0", "0", 119 "0", "0", "-1"; 124 mount-matrix = "0", "-1", "0", 125 "-1", "0", "0", [all …]
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| D | tegra124-nyan-blaze-emc.dtsi | 92 0x40040001 93 0x8000000a 94 0x00000001 95 0x00000001 96 0x00000002 97 0x00000000 98 0x00000002 99 0x00000001 100 0x00000002 101 0x00000008 [all …]
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| D | tegra124-apalis-emc.dtsi | 108 0x40040001 0x8000000a 109 0x00000001 0x00000001 110 0x00000002 0x00000000 111 0x00000002 0x00000001 112 0x00000003 0x00000008 113 0x00000003 0x00000002 114 0x00000003 0x00000006 115 0x06030203 0x000a0502 116 0x77e30303 0x70000f03 117 0x001f0000 [all …]
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| D | tegra124-jetson-tk1-emc.dtsi | 104 0x40040001 105 0x8000000a 106 0x00000001 107 0x00000001 108 0x00000002 109 0x00000000 110 0x00000002 111 0x00000001 112 0x00000003 113 0x00000008 [all …]
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| D | tegra30-asus-tf300t.dts | 75 reg = <0x10>; 94 mount-matrix = "0", "-1", "0", 95 "-1", "0", "0", 96 "0", "0", "-1"; 100 mount-matrix = "-1", "0", "0", 101 "0", "1", "0", 102 "0", "0", "-1"; 107 mount-matrix = "0", "-1", "0", 108 "-1", "0", "0", 109 "0", "0", "1"; [all …]
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| /kernel/linux/linux-5.10/net/core/ |
| D | ptp_classifier.c | 16 * jneq #0x800, test_ipv6 ; ETH_P_IP ? 20 * jset #0x1fff, drop_ipv4 ; don't allow fragments 21 * ldxb 4*([14]&0xf) ; load IP header len 25 * and #0xf ; mask PTP_CLASS_VMASK 26 * or #0x10 ; PTP_CLASS_IPV4 28 * drop_ipv4: ret #0x0 ; PTP_CLASS_NONE 32 * jneq #0x86dd, test_8021q ; ETH_P_IPV6 ? 38 * and #0xf ; mask PTP_CLASS_VMASK 39 * or #0x20 ; PTP_CLASS_IPV6 41 * drop_ipv6: ret #0x0 ; PTP_CLASS_NONE [all …]
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| /kernel/linux/linux-6.6/net/core/ |
| D | ptp_classifier.c | 16 * jneq #0x800, test_ipv6 ; ETH_P_IP ? 20 * jset #0x1fff, drop_ipv4 ; don't allow fragments 21 * ldxb 4*([14]&0xf) ; load IP header len 25 * and #0xf ; mask PTP_CLASS_VMASK 26 * or #0x10 ; PTP_CLASS_IPV4 28 * drop_ipv4: ret #0x0 ; PTP_CLASS_NONE 32 * jneq #0x86dd, test_8021q ; ETH_P_IPV6 ? 38 * and #0xf ; mask PTP_CLASS_VMASK 39 * or #0x20 ; PTP_CLASS_IPV6 41 * drop_ipv6: ret #0x0 ; PTP_CLASS_NONE [all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| D | sdma0_4_0_default.h | 26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000 27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000 28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000 29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000 30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000 31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000 32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000 33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000 34 #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000 35 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f [all …]
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| D | sdma0_4_1_default.h | 26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000 27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000 28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000 29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000 30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000 31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000 32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000 33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000 34 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f 35 #define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff [all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| D | sdma0_4_0_default.h | 26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000 27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000 28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000 29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000 30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000 31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000 32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000 33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000 34 #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000 35 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f [all …]
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| D | sdma0_4_1_default.h | 26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000 27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000 28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000 29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000 30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000 31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000 32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000 33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000 34 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f 35 #define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff [all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma1/ |
| D | sdma1_4_0_default.h | 26 #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000 27 #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000 28 #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000 29 #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000 30 #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000 31 #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000 32 #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000 33 #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000 34 #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000 35 #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f [all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma1/ |
| D | sdma1_4_0_default.h | 26 #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000 27 #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000 28 #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000 29 #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000 30 #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000 31 #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000 32 #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000 33 #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000 34 #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000 35 #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f [all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_6_0_sh_mask.h | 26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L 27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008 28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L 29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010 30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L 31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000 32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L 33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002 34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L 35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001 [all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_6_0_sh_mask.h | 26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L 27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008 28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L 29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010 30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L 31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000 32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L 33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002 34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L 35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001 [all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/etnaviv/ |
| D | state_hi.xml.h | 7 http://0x04.net/cgit/index.cgi/rules-ng-ng 8 git clone git://0x04.net/rules-ng-ng 48 #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001 49 #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002 50 #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003 51 #define MMU_EXCEPTION_OUT_OF_BOUND 0x00000004 52 #define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x00000005 53 #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x00000006 54 #define VIVS_HI 0x00000000 56 #define VIVS_HI_CLOCK_CONTROL 0x00000000 [all …]
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