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/kernel/linux/linux-5.10/drivers/staging/media/rkisp1/
Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI BIT(0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/hdmi/
Dhdmi.xml.h50 HDCP_KEYS_STATE_NO_KEYS = 0,
61 DDC_WRITE = 0,
66 ACR_NONE = 0,
72 #define REG_HDMI_CTRL 0x00000000
73 #define HDMI_CTRL_ENABLE 0x00000001
74 #define HDMI_CTRL_HDMI 0x00000002
75 #define HDMI_CTRL_ENCRYPTED 0x00000004
77 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
78 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
80 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/hdmi/
Dhdmi.xml.h57 HDCP_KEYS_STATE_NO_KEYS = 0,
68 DDC_WRITE = 0,
73 ACR_NONE = 0,
79 #define REG_HDMI_CTRL 0x00000000
80 #define HDMI_CTRL_ENABLE 0x00000001
81 #define HDMI_CTRL_HDMI 0x00000002
82 #define HDMI_CTRL_ENCRYPTED 0x00000004
84 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
85 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
87 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/rockchip/rkisp1/
Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI (1 << 0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/
Ddsi_phy_14nm.xml.h56 #define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
58 #define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
60 #define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
62 #define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
64 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
65 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
71 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
78 #define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
79 #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
81 #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
[all …]
Ddsi_phy_28nm_8960.xml.h56 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN()
58 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0()
60 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1()
62 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2()
64 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x… in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH()
66 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0()
68 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1()
70 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
72 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
74 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
[all …]
Ddsi_phy_7nm.xml.h56 #define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
58 #define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
60 #define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
62 #define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
64 #define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
66 #define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
68 #define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
70 #define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
72 #define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
74 #define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h50 NON_BURST_SYNCH_PULSE = 0,
56 VID_DST_FORMAT_RGB565 = 0,
63 SWAP_RGB = 0,
72 TRIGGER_NONE = 0,
81 CMD_DST_FORMAT_RGB111 = 0,
90 LANE_SWAP_0123 = 0,
100 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
101 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
103 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dp/
Ddp_reg.h10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
[all …]
/kernel/linux/linux-5.10/tools/include/uapi/linux/
Dethtool.h21 #define ETHTOOL_GCHANNELS 0x0000003c /* Get no of channels */
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dp/
Ddp_reg.h10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
[all …]
/kernel/linux/linux-5.10/drivers/crypto/
Dpicoxcell_crypto_regs.h8 #define SPA_STATUS_OK 0
16 #define SPA_FIFO_STAT_STAT_CNT_MASK (0x3F << SPA_FIFO_STAT_STAT_OFFSET)
18 #define SPA_STATUS_RES_CODE_MASK (0x3 << SPA_STATUS_RES_CODE_OFFSET)
22 #define SPA_IRQ_EN_REG_OFFSET 0x00000000
23 #define SPA_IRQ_STAT_REG_OFFSET 0x00000004
24 #define SPA_IRQ_CTRL_REG_OFFSET 0x00000008
25 #define SPA_FIFO_STAT_REG_OFFSET 0x0000000C
26 #define SPA_SDMA_BRST_SZ_REG_OFFSET 0x00000010
27 #define SPA_SRC_PTR_REG_OFFSET 0x00000020
28 #define SPA_DST_PTR_REG_OFFSET 0x00000024
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/kernel/linux/linux-5.10/arch/mips/include/asm/
Dinst.h25 #define I_JTARGET_SFT 0
26 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
32 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
34 #define I_IMM_SFT 0
35 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
36 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
39 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
42 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
45 #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dramcfg.c32 return (nvkm_rd32(subdev->device, 0x101000) & 0x0000003c) >> 2; in nvbios_ramcfg_strap()
44 return nvbios_rd08(bios, bit_M.offset + 0); in nvbios_ramcfg_count()
47 return 0x00; in nvbios_ramcfg_count()
55 u32 xlat = 0x00000000; in nvbios_ramcfg_index()
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dramcfg.c32 return (nvkm_rd32(subdev->device, 0x101000) & 0x0000003c) >> 2; in nvbios_ramcfg_strap()
44 return nvbios_rd08(bios, bit_M.offset + 0); in nvbios_ramcfg_count()
47 return 0x00; in nvbios_ramcfg_count()
55 u32 xlat = 0x00000000; in nvbios_ramcfg_index()
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/
Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/thermal/
Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/kernel/linux/linux-6.6/tools/include/uapi/linux/
Dethtool.h21 #define ETHTOOL_GCHANNELS 0x0000003c /* Get no of channels */
102 #define ETHTOOL_GDRVINFO 0x00000003
/kernel/linux/linux-5.10/drivers/crypto/qat/qat_common/
Dadf_pf2vf_msg.h14 * bit of this register (bit 0) gets set an interrupt will be triggered
35 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
48 * by this driver; these had a Msg Origin of 0 and are ignored by this driver.
55 #define ADF_PFVF_COMPATIBILITY_VERSION 0x1 /* PF<->VF compat */
58 #define ADF_PF2VF_INT BIT(0)
60 #define ADF_PF2VF_MSGTYPE_MASK 0x0000003C
62 #define ADF_PF2VF_MSGTYPE_RESTARTING 0x01
63 #define ADF_PF2VF_MSGTYPE_VERSION_RESP 0x02
64 #define ADF_PF2VF_IN_USE_BY_PF 0x6AC20000
65 #define ADF_PF2VF_IN_USE_BY_PF_MASK 0xFFFE0000
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdkfd/
Dkfd_int_process_v11.c40 * The 44-bit packet is mapped as {context_id1[7:0],context_id0[31:0]} plus
44 * Encoding type (0 = Auto, 1 = Wave, 2 = Error)
49 * - context_id0[24:0]
51 * Auto - only context_id0[8:0] is used, which reports various interrupts
52 * generated by SQG. The rest is 0.
53 * Wave - user data sent from m0 via S_SENDMSG (context_id0[23:0])
54 * Error - Error Type (context_id0[24:21]), Error Details (context_id0[20:0])
57 * S_SENDMSG and Errors. These are 0 for Auto.
61 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
67 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0,
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv05.c38 { 0x24, 0x00 }, in nv05_devinit_meminit()
39 { 0x28, 0x00 }, in nv05_devinit_meminit()
40 { 0x24, 0x01 }, in nv05_devinit_meminit()
41 { 0x1f, 0x00 }, in nv05_devinit_meminit()
42 { 0x0f, 0x00 }, in nv05_devinit_meminit()
43 { 0x17, 0x00 }, in nv05_devinit_meminit()
44 { 0x06, 0x00 }, in nv05_devinit_meminit()
45 { 0x00, 0x00 } in nv05_devinit_meminit()
51 u32 patt = 0xdeadbeef; in nv05_devinit_meminit()
63 strap = (nvkm_rd32(device, 0x101000) & 0x0000003c) >> 2; in nv05_devinit_meminit()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv05.c38 { 0x24, 0x00 }, in nv05_devinit_meminit()
39 { 0x28, 0x00 }, in nv05_devinit_meminit()
40 { 0x24, 0x01 }, in nv05_devinit_meminit()
41 { 0x1f, 0x00 }, in nv05_devinit_meminit()
42 { 0x0f, 0x00 }, in nv05_devinit_meminit()
43 { 0x17, 0x00 }, in nv05_devinit_meminit()
44 { 0x06, 0x00 }, in nv05_devinit_meminit()
45 { 0x00, 0x00 } in nv05_devinit_meminit()
51 u32 patt = 0xdeadbeef; in nv05_devinit_meminit()
63 strap = (nvkm_rd32(device, 0x101000) & 0x0000003c) >> 2; in nv05_devinit_meminit()
[all …]
/kernel/linux/linux-5.10/arch/loongarch/include/asm/
Dinst.h30 #define I_JTARGET_SFT 0
31 #define LOONGARCHInst_JTARGET(x) (LOONGARCHInst(x) & 0x03ffffff)
34 #define LOONGARCHInst_RS(x) ((LOONGARCHInst(x) & 0x03e00000) >> I_RS_SFT)
37 #define LOONGARCHInst_RT(x) ((LOONGARCHInst(x) & 0x001f0000) >> I_RT_SFT)
39 #define I_IMM_SFT 0
40 #define LOONGARCHInst_SIMM(x) ((int)((short)(LOONGARCHInst(x) & 0xffff)))
41 #define LOONGARCHInst_UIMM(x) (LOONGARCHInst(x) & 0xffff)
44 #define LOONGARCHInst_CACHEOP(x) ((LOONGARCHInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
47 #define LOONGARCHInst_CACHESEL(x) ((LOONGARCHInst(x) & 0x00030000) >> I_CACHESEL_SFT)
50 #define LOONGARCHInst_RD(x) ((LOONGARCHInst(x) & 0x0000f800) >> I_RD_SFT)
[all …]
/kernel/linux/linux-5.10/include/linux/
Datmel-ssc.h33 #define SSC_CR 0x00000000
37 #define SSC_CR_RXEN_OFFSET 0
46 #define SSC_CMR 0x00000004
48 #define SSC_CMR_DIV_OFFSET 0
51 #define SSC_RCMR 0x00000010
59 #define SSC_RCMR_CKS_OFFSET 0
70 #define SSC_RFMR 0x00000014
72 #define SSC_RFMR_DATLEN_OFFSET 0
93 #define SSC_TCMR 0x00000018
101 #define SSC_TCMR_CKS_OFFSET 0
[all …]
/kernel/linux/linux-6.6/include/linux/
Datmel-ssc.h33 #define SSC_CR 0x00000000
37 #define SSC_CR_RXEN_OFFSET 0
46 #define SSC_CMR 0x00000004
48 #define SSC_CMR_DIV_OFFSET 0
51 #define SSC_RCMR 0x00000010
59 #define SSC_RCMR_CKS_OFFSET 0
70 #define SSC_RFMR 0x00000014
72 #define SSC_RFMR_DATLEN_OFFSET 0
93 #define SSC_TCMR 0x00000018
101 #define SSC_TCMR_CKS_OFFSET 0
[all …]

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