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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,cpm1-scc-qmc.yaml60 const: 0
63 '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
70 minimum: 0
125 reg = <0xa60 0x20>,
126 <0x3f00 0xc0>,
127 <0x2000 0x1000>;
133 #size-cells = <0>;
142 fsl,tx-ts-mask = <0x00000000 0x000000aa>;
143 fsl,rx-ts-mask = <0x00000000 0x000000aa>;
151 fsl,tx-ts-mask = <0x00000000 0x00000055>;
[all …]
/kernel/linux/linux-6.6/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
Dfifo_monitor_local.h24 #define _hive_str_mon_valid_offset 0
27 #define FIFO_CHANNEL_SP_VALID_MASK 0x55555555
28 #define FIFO_CHANNEL_SP_VALID_B_MASK 0x00000055
29 #define FIFO_CHANNEL_ISP_VALID_MASK 0x15555555
30 #define FIFO_CHANNEL_MOD_VALID_MASK 0x55555555
/kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
Dfifo_monitor_local.h24 #define _hive_str_mon_valid_offset 0
27 #define FIFO_CHANNEL_SP_VALID_MASK 0x55555555
28 #define FIFO_CHANNEL_SP_VALID_B_MASK 0x00000055
29 #define FIFO_CHANNEL_ISP_VALID_MASK 0x15555555
30 #define FIFO_CHANNEL_MOD_VALID_MASK 0x55555555
/kernel/linux/linux-6.6/sound/soc/codecs/
Dcs35l45-tables.c15 { 0x00000040, 0x00000055 },
16 { 0x00000040, 0x000000AA },
17 { 0x00000044, 0x00000055 },
18 { 0x00000044, 0x000000AA },
19 { 0x00006480, 0x0830500A },
20 { 0x00007C60, 0x1000850B },
21 { CS35L45_BOOST_OV_CFG, 0x007000D0 },
22 { CS35L45_LDPM_CONFIG, 0x0001B636 },
23 { 0x00002C08, 0x00000009 },
24 { 0x00006850, 0x0A30FFC4 },
[all …]
Dcs35l41-lib.c20 { CS35L41_PWR_CTRL1, 0x00000000 },
21 { CS35L41_PWR_CTRL2, 0x00000000 },
22 { CS35L41_PWR_CTRL3, 0x01000010 },
23 { CS35L41_GPIO_PAD_CONTROL, 0x00000000 },
24 { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 },
25 { CS35L41_TST_FS_MON0, 0x00020016 },
26 { CS35L41_BSTCVRT_COEFF, 0x00002424 },
27 { CS35L41_BSTCVRT_SLOPE_LBST, 0x00007500 },
28 { CS35L41_BSTCVRT_PEAK_CUR, 0x0000004A },
29 { CS35L41_SP_ENABLES, 0x00000000 },
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/include/nvhw/class/
Dclc57d.h27 #define NVC57D_SET_CONTEXT_DMA_NOTIFIER (0x00000208)
28 #define NVC57D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
30 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0…
31 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0
32 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
33 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
35 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
36 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
38 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
39 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
[all …]
Dclc57e.h27 #define NVC57E_SET_SIZE (0x00000224)
28 #define NVC57E_SET_SIZE_WIDTH 15:0
30 #define NVC57E_SET_STORAGE (0x00000228)
31 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT 3:0
32 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000)
33 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
34 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
35 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
36 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
37 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
[all …]
Dclc37d.h27 #define NV_DISP_NOTIFIER 0x00000000
28 #define NV_DISP_NOTIFIER_SIZEOF 0x00000010
29 #define NV_DISP_NOTIFIER__0 0x00000000
30 #define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0
33 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000
34 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001
39 #define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000
40 #define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001
41 #define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002
42 #define NV_DISP_NOTIFIER__1 0x00000001
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/geode/
Dvideo_gx.c34 { 40123, POSTDIV3, 0x00000BF2 }, /* 24.9230 */
35 { 39721, 0, 0x00000037 }, /* 25.1750 */
36 { 35308, POSTDIV3|PREMULT2, 0x00000B1A }, /* 28.3220 */
37 { 31746, POSTDIV3, 0x000002D2 }, /* 31.5000 */
38 { 27777, POSTDIV3|PREMULT2, 0x00000FE2 }, /* 36.0000 */
39 { 26666, POSTDIV3, 0x0000057A }, /* 37.5000 */
40 { 25000, POSTDIV3, 0x0000030A }, /* 40.0000 */
41 { 22271, 0, 0x00000063 }, /* 44.9000 */
42 { 20202, 0, 0x0000054B }, /* 49.5000 */
43 { 20000, 0, 0x0000026E }, /* 50.0000 */
[all …]
/kernel/linux/linux-6.6/drivers/video/fbdev/geode/
Dvideo_gx.c34 { 40123, POSTDIV3, 0x00000BF2 }, /* 24.9230 */
35 { 39721, 0, 0x00000037 }, /* 25.1750 */
36 { 35308, POSTDIV3|PREMULT2, 0x00000B1A }, /* 28.3220 */
37 { 31746, POSTDIV3, 0x000002D2 }, /* 31.5000 */
38 { 27777, POSTDIV3|PREMULT2, 0x00000FE2 }, /* 36.0000 */
39 { 26666, POSTDIV3, 0x0000057A }, /* 37.5000 */
40 { 25000, POSTDIV3, 0x0000030A }, /* 40.0000 */
41 { 22271, 0, 0x00000063 }, /* 44.9000 */
42 { 20202, 0, 0x0000054B }, /* 49.5000 */
43 { 20000, 0, 0x0000026E }, /* 50.0000 */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Ddacnv50.c33 nvkm_mask(device, 0x614280 + doff, 0x07070707, 0x00000000); in nv50_dac_clock()
44 nvkm_wr32(device, 0x61a00c + doff, 0x00100000 | loadval); in nv50_dac_sense()
47 loadval = nvkm_mask(device, 0x61a00c + doff, 0xffffffff, 0x00000000); in nv50_dac_sense()
50 if (!(loadval & 0x80000000)) in nv50_dac_sense()
53 return (loadval & 0x38000000) >> 27; in nv50_dac_sense()
60 if (!(nvkm_rd32(device, 0x61a004 + doff) & 0x80000000)) in nv50_dac_power_wait()
71 const u32 shift = normal ? 0 : 16; in nv50_dac_power()
72 const u32 state = 0x80000000 | (0x00000040 * ! pu | in nv50_dac_power()
73 0x00000010 * ! data | in nv50_dac_power()
74 0x00000004 * ! vsync | in nv50_dac_power()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/include/nvhw/class/
Dclc57e.h27 #define NVC57E_SET_SIZE (0x00000224)
28 #define NVC57E_SET_SIZE_WIDTH 15:0
30 #define NVC57E_SET_STORAGE (0x00000228)
31 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT 3:0
32 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000)
33 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
34 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
35 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
36 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
37 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
[all …]
Dclc37d.h27 #define NV_DISP_NOTIFIER 0x00000000
28 #define NV_DISP_NOTIFIER_SIZEOF 0x00000010
29 #define NV_DISP_NOTIFIER__0 0x00000000
30 #define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0
33 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000
34 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001
39 #define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000
40 #define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001
41 #define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002
42 #define NV_DISP_NOTIFIER__1 0x00000001
[all …]
/kernel/linux/linux-6.6/arch/m68k/coldfire/
Dm5272.c32 unsigned char ledbank = 0xff;
36 DEFINE_CLK(pll, "pll.0", MCF_CLK);
37 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
40 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
41 CLKDEV_INIT(NULL, "sys.0", &clk_sys),
42 CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
46 CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
48 CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
49 CLKDEV_INIT("fec.0", NULL, &clk_sys),
60 v = (v & ~0x000000ff) | 0x00000055; in m5272_uarts_init()
[all …]
/kernel/linux/linux-5.10/arch/m68k/coldfire/
Dm5272.c31 unsigned char ledbank = 0xff;
35 DEFINE_CLK(pll, "pll.0", MCF_CLK);
36 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
37 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
41 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
43 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
44 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
68 v = (v & ~0x000000ff) | 0x00000055; in m5272_uarts_init()
72 v = (v & ~0x000003fc) | 0x000002a8; in m5272_uarts_init()
82 __raw_writew(0, MCFSIM_WIRR); in m5272_cpu_reset()
[all …]
/kernel/linux/linux-6.6/lib/math/
Dtest_div64.c20 0x00000000ab275080,
21 0x0000000fe73c1959,
22 0x000000e54c0a74b1,
23 0x00000d4398ff1ef9,
24 0x0000a18c2ee1c097,
25 0x00079fb80b072e4a,
26 0x0072db27380dd689,
27 0x0842f488162e2284,
28 0xf66745411d8ab063,
32 #define TEST_DIV64_DIVISOR_0 0x00000009
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/st/sti/bdisp/
Dbdisp-reg.h8 /* 0 - General */
87 #define BLT_CTL 0x0A00
88 #define BLT_ITS 0x0A04
89 #define BLT_STA1 0x0A08
90 #define BLT_AQ1_CTL 0x0A60
91 #define BLT_AQ1_IP 0x0A64
92 #define BLT_AQ1_LNA 0x0A68
93 #define BLT_AQ1_STA 0x0A6C
94 #define BLT_ITM0 0x0AD0
96 #define BLT_PLUGS1_OP2 0x0B04
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/sti/bdisp/
Dbdisp-reg.h8 /* 0 - General */
87 #define BLT_CTL 0x0A00
88 #define BLT_ITS 0x0A04
89 #define BLT_STA1 0x0A08
90 #define BLT_AQ1_CTL 0x0A60
91 #define BLT_AQ1_IP 0x0A64
92 #define BLT_AQ1_LNA 0x0A68
93 #define BLT_AQ1_STA 0x0A6C
94 #define BLT_ITM0 0x0AD0
96 #define BLT_PLUGS1_OP2 0x0B04
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
Dmdfld_tmd_vid.c89 drm_mode_set_crtcinfo(mode, 0); in tmd_vid_get_config_mode()
106 return 0; in tmd_vid_get_panel_info()
119 static u32 tmd_cmd_mcap_off[] = {0x000000b2};
120 static u32 tmd_cmd_enable_lane_switch[] = {0x000101ef};
121 static u32 tmd_cmd_set_lane_num[] = {0x006360ef};
122 static u32 tmd_cmd_pushing_clock0[] = {0x00cc2fef};
123 static u32 tmd_cmd_pushing_clock1[] = {0x00dd6eef};
124 static u32 tmd_cmd_set_mode[] = {0x000000b3};
125 static u32 tmd_cmd_set_sync_pulse_mode[] = {0x000961ef};
126 static u32 tmd_cmd_set_column[] = {0x0100002a, 0x000000df};
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxgf119.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x0000a9, 1, 0x01, 0x0000ffff },
34 { 0x000038, 1, 0x01, 0x0fac6881 },
35 { 0x00003d, 1, 0x01, 0x00000001 },
36 { 0x0000e8, 8, 0x01, 0x00000400 },
37 { 0x000078, 8, 0x01, 0x00000300 },
38 { 0x000050, 1, 0x01, 0x00000011 },
39 { 0x000058, 8, 0x01, 0x00000008 },
40 { 0x000208, 8, 0x01, 0x00000001 },
41 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
Dctxgk208.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x000039, 3, 0x01, 0x00000000 },
34 { 0x0000a9, 1, 0x01, 0x0000ffff },
35 { 0x000038, 1, 0x01, 0x0fac6881 },
36 { 0x00003d, 1, 0x01, 0x00000001 },
37 { 0x0000e8, 8, 0x01, 0x00000400 },
38 { 0x000078, 8, 0x01, 0x00000300 },
39 { 0x000050, 1, 0x01, 0x00000011 },
40 { 0x000058, 8, 0x01, 0x00000008 },
41 { 0x000208, 8, 0x01, 0x00000001 },
[all …]
Dctxgk110.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x000039, 3, 0x01, 0x00000000 },
34 { 0x0000a9, 1, 0x01, 0x0000ffff },
35 { 0x000038, 1, 0x01, 0x0fac6881 },
36 { 0x00003d, 1, 0x01, 0x00000001 },
37 { 0x0000e8, 8, 0x01, 0x00000400 },
38 { 0x000078, 8, 0x01, 0x00000300 },
39 { 0x000050, 1, 0x01, 0x00000011 },
40 { 0x000058, 8, 0x01, 0x00000008 },
41 { 0x000208, 8, 0x01, 0x00000001 },
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxgf119.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x0000a9, 1, 0x01, 0x0000ffff },
34 { 0x000038, 1, 0x01, 0x0fac6881 },
35 { 0x00003d, 1, 0x01, 0x00000001 },
36 { 0x0000e8, 8, 0x01, 0x00000400 },
37 { 0x000078, 8, 0x01, 0x00000300 },
38 { 0x000050, 1, 0x01, 0x00000011 },
39 { 0x000058, 8, 0x01, 0x00000008 },
40 { 0x000208, 8, 0x01, 0x00000001 },
41 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
Dctxgk208.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x000039, 3, 0x01, 0x00000000 },
34 { 0x0000a9, 1, 0x01, 0x0000ffff },
35 { 0x000038, 1, 0x01, 0x0fac6881 },
36 { 0x00003d, 1, 0x01, 0x00000001 },
37 { 0x0000e8, 8, 0x01, 0x00000400 },
38 { 0x000078, 8, 0x01, 0x00000300 },
39 { 0x000050, 1, 0x01, 0x00000011 },
40 { 0x000058, 8, 0x01, 0x00000008 },
41 { 0x000208, 8, 0x01, 0x00000001 },
[all …]
Dctxgk110.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x000039, 3, 0x01, 0x00000000 },
34 { 0x0000a9, 1, 0x01, 0x0000ffff },
35 { 0x000038, 1, 0x01, 0x0fac6881 },
36 { 0x00003d, 1, 0x01, 0x00000001 },
37 { 0x0000e8, 8, 0x01, 0x00000400 },
38 { 0x000078, 8, 0x01, 0x00000300 },
39 { 0x000050, 1, 0x01, 0x00000011 },
40 { 0x000058, 8, 0x01, 0x00000008 },
41 { 0x000208, 8, 0x01, 0x00000001 },
[all …]

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