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/kernel/linux/linux-6.6/drivers/scsi/lpfc/
Dlpfc_hw4.h36 * #define example_bit_field_MASK 0x03
47 * bf_set(example_bit_field, &t1, 0);
63 #define get_wqe_reqtag(x) (((x)->wqe.words[9] >> 0) & 0xFFFF)
64 #define get_wqe_tmo(x) (((x)->wqe.words[7] >> 24) & 0x00FF)
79 #define lpfc_sli_intf_valid_MASK 0x00000007
83 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
85 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
87 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
89 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
93 #define lpfc_sli_intf_if_type_MASK 0x0000000F
[all …]
/kernel/linux/linux-5.10/drivers/scsi/lpfc/
Dlpfc_hw4.h35 * #define example_bit_field_MASK 0x03
46 * bf_set(example_bit_field, &t1, 0);
70 #define lpfc_sli_intf_valid_MASK 0x00000007
74 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
76 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
78 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
80 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
84 #define lpfc_sli_intf_if_type_MASK 0x0000000F
86 #define LPFC_SLI_INTF_IF_TYPE_0 0
91 #define lpfc_sli_intf_sli_family_MASK 0x0000000F
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8188eu/hal/
Dmac_cfg.c14 0x026, 0x00000041,
15 0x027, 0x00000035,
16 0x428, 0x0000000A,
17 0x429, 0x00000010,
18 0x430, 0x00000000,
19 0x431, 0x00000001,
20 0x432, 0x00000002,
21 0x433, 0x00000004,
22 0x434, 0x00000005,
23 0x435, 0x00000006,
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c13 #define XGBE_CTRL_OFFSET 0x0c
14 #define XGBE_SGMII_1_OFFSET 0x0114
15 #define XGBE_SGMII_2_OFFSET 0x0214
18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
31 #define PHY_A(serdes) 0
40 {0x0000, 0x00800002, 0x00ff00ff},
41 {0x0014, 0x00003838, 0x0000ffff},
42 {0x0060, 0x1c44e438, 0xffffffff},
43 {0x0064, 0x00c18400, 0x00ffffff},
44 {0x0068, 0x17078200, 0xffffff00},
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c13 #define XGBE_CTRL_OFFSET 0x0c
14 #define XGBE_SGMII_1_OFFSET 0x0114
15 #define XGBE_SGMII_2_OFFSET 0x0214
18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
31 #define PHY_A(serdes) 0
40 {0x0000, 0x00800002, 0x00ff00ff},
41 {0x0014, 0x00003838, 0x0000ffff},
42 {0x0060, 0x1c44e438, 0xffffffff},
43 {0x0064, 0x00c18400, 0x00ffffff},
44 {0x0068, 0x17078200, 0xffffff00},
[all …]
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/hal/
DHalHWImg8723B_MAC.c16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
31 pDM_Odm->TypeGLNA << 0 | in CheckPositive()
40 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) in CheckPositive()
42 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) in CheckPositive()
48 cond1 &= 0x000F0FFF; in CheckPositive()
49 driver1 &= 0x000F0FFF; in CheckPositive()
52 u32 bitMask = 0; in CheckPositive()
53 if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE */ in CheckPositive()
56 if ((cond1 & BIT0) != 0) /* GLNA */ in CheckPositive()
57 bitMask |= 0x000000FF; in CheckPositive()
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/
DHalHWImg8723B_MAC.c16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
31 pDM_Odm->TypeGLNA << 0 | in CheckPositive()
41 "===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n", in CheckPositive()
51 "===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n", in CheckPositive()
62 " (Platform, Interface) = (0x%X, 0x%X)\n", in CheckPositive()
72 " (Board, Package) = (0x%X, 0x%X)\n", in CheckPositive()
82 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) in CheckPositive()
84 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) in CheckPositive()
90 cond1 &= 0x000F0FFF; in CheckPositive()
91 driver1 &= 0x000F0FFF; in CheckPositive()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/
Ddsi_phy_28nm.xml.h56 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN()
58 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_0()
60 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_1()
62 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_2()
64 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_3()
66 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_4()
68 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0… in REG_DSI_28nm_PHY_LN_TEST_DATAPATH()
70 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_DEBUG_SEL()
72 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_TEST_STR_0()
74 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_TEST_STR_1()
[all …]
Ddsi_phy_20nm.xml.h56 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_20nm_PHY_LN()
58 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_0()
60 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_1()
62 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_2()
64 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_3()
66 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_4()
68 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0… in REG_DSI_20nm_PHY_LN_TEST_DATAPATH()
70 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_DEBUG_SEL()
72 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } in REG_DSI_20nm_PHY_LN_TEST_STR_0()
74 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_TEST_STR_1()
[all …]
Ddsi_phy_28nm_8960.xml.h56 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN()
58 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0()
60 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1()
62 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2()
64 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x… in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH()
66 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0()
68 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1()
70 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
72 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
74 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
Dtonga_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
41 #define SDMA_SUBOP_TIMESTAMP_SET 0
44 #define SDMA_SUBOP_COPY_LINEAR 0
50 #define SDMA_SUBOP_WRITE_LINEAR 0
54 #define SDMA_PKT_HEADER_op_offset 0
55 #define SDMA_PKT_HEADER_op_mask 0x000000FF
56 #define SDMA_PKT_HEADER_op_shift 0
60 #define SDMA_PKT_HEADER_sub_op_offset 0
61 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF
71 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
[all …]
Dvega10_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
42 #define SDMA_SUBOP_TIMESTAMP_SET 0
45 #define SDMA_SUBOP_COPY_LINEAR 0
53 #define SDMA_SUBOP_WRITE_LINEAR 0
55 #define SDMA_SUBOP_PTEPDE_GEN 0
65 #define SDMA_OP_AQL_COPY 0
66 #define SDMA_OP_AQL_BARRIER_OR 0
69 #define SDMA_PKT_HEADER_op_offset 0
70 #define SDMA_PKT_HEADER_op_mask 0x000000FF
71 #define SDMA_PKT_HEADER_op_shift 0
[all …]
Diceland_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
41 #define SDMA_SUBOP_TIMESTAMP_SET 0
44 #define SDMA_SUBOP_COPY_LINEAR 0
50 #define SDMA_SUBOP_WRITE_LINEAR 0
54 #define SDMA_PKT_HEADER_op_offset 0
55 #define SDMA_PKT_HEADER_op_mask 0x000000FF
56 #define SDMA_PKT_HEADER_op_shift 0
60 #define SDMA_PKT_HEADER_sub_op_offset 0
61 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF
71 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
[all …]
Dsdma_v6_0_0_pkt_open.h26 #define SDMA_OP_NOP 0
44 #define SDMA_SUBOP_TIMESTAMP_SET 0
47 #define SDMA_SUBOP_COPY_LINEAR 0
61 #define SDMA_SUBOP_WRITE_LINEAR 0
64 #define SDMA_SUBOP_PTEPDE_GEN 0
76 #define SDMA_OP_AQL_COPY 0
77 #define SDMA_OP_AQL_BARRIER_OR 0
80 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16)
84 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11)
92 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2)
[all …]
Dnavi10_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
44 #define SDMA_SUBOP_TIMESTAMP_SET 0
47 #define SDMA_SUBOP_COPY_LINEAR 0
60 #define SDMA_SUBOP_WRITE_LINEAR 0
63 #define SDMA_SUBOP_PTEPDE_GEN 0
73 #define SDMA_OP_AQL_COPY 0
74 #define SDMA_OP_AQL_BARRIER_OR 0
77 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16)
81 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11)
89 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dtonga_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
41 #define SDMA_SUBOP_TIMESTAMP_SET 0
44 #define SDMA_SUBOP_COPY_LINEAR 0
50 #define SDMA_SUBOP_WRITE_LINEAR 0
54 #define SDMA_PKT_HEADER_op_offset 0
55 #define SDMA_PKT_HEADER_op_mask 0x000000FF
56 #define SDMA_PKT_HEADER_op_shift 0
60 #define SDMA_PKT_HEADER_sub_op_offset 0
61 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF
71 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
[all …]
Dvega10_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
42 #define SDMA_SUBOP_TIMESTAMP_SET 0
45 #define SDMA_SUBOP_COPY_LINEAR 0
53 #define SDMA_SUBOP_WRITE_LINEAR 0
55 #define SDMA_SUBOP_PTEPDE_GEN 0
65 #define SDMA_OP_AQL_COPY 0
66 #define SDMA_OP_AQL_BARRIER_OR 0
69 #define SDMA_PKT_HEADER_op_offset 0
70 #define SDMA_PKT_HEADER_op_mask 0x000000FF
71 #define SDMA_PKT_HEADER_op_shift 0
[all …]
Diceland_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
41 #define SDMA_SUBOP_TIMESTAMP_SET 0
44 #define SDMA_SUBOP_COPY_LINEAR 0
50 #define SDMA_SUBOP_WRITE_LINEAR 0
54 #define SDMA_PKT_HEADER_op_offset 0
55 #define SDMA_PKT_HEADER_op_mask 0x000000FF
56 #define SDMA_PKT_HEADER_op_shift 0
60 #define SDMA_PKT_HEADER_sub_op_offset 0
61 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF
71 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
[all …]
Dnavi10_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
44 #define SDMA_SUBOP_TIMESTAMP_SET 0
47 #define SDMA_SUBOP_COPY_LINEAR 0
60 #define SDMA_SUBOP_WRITE_LINEAR 0
63 #define SDMA_SUBOP_PTEPDE_GEN 0
73 #define SDMA_OP_AQL_COPY 0
74 #define SDMA_OP_AQL_BARRIER_OR 0
77 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16)
81 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11)
89 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h50 NON_BURST_SYNCH_PULSE = 0,
56 VID_DST_FORMAT_RGB565 = 0,
63 SWAP_RGB = 0,
72 TRIGGER_NONE = 0,
81 CMD_DST_FORMAT_RGB111 = 0,
90 LANE_SWAP_0123 = 0,
100 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
101 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
103 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/ralink/rt2x00/
Drt2400pci.h20 #define RF2420 0x0000
21 #define RF2421 0x0001
32 #define CSR_REG_BASE 0x0000
33 #define CSR_REG_SIZE 0x014c
34 #define EEPROM_BASE 0x0000
35 #define EEPROM_SIZE 0x0100
36 #define BBP_BASE 0x0000
37 #define BBP_SIZE 0x0020
38 #define RF_BASE 0x0004
39 #define RF_SIZE 0x000c
[all …]
Drt2500pci.h20 #define RF2522 0x0000
21 #define RF2523 0x0001
22 #define RF2524 0x0002
23 #define RF2525 0x0003
24 #define RF2525E 0x0004
25 #define RF5222 0x0010
43 #define CSR_REG_BASE 0x0000
44 #define CSR_REG_SIZE 0x0174
45 #define EEPROM_BASE 0x0000
46 #define EEPROM_SIZE 0x0200
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/ralink/rt2x00/
Drt2400pci.h20 #define RF2420 0x0000
21 #define RF2421 0x0001
32 #define CSR_REG_BASE 0x0000
33 #define CSR_REG_SIZE 0x014c
34 #define EEPROM_BASE 0x0000
35 #define EEPROM_SIZE 0x0100
36 #define BBP_BASE 0x0000
37 #define BBP_SIZE 0x0020
38 #define RF_BASE 0x0004
39 #define RF_SIZE 0x000c
[all …]
Drt2500pci.h20 #define RF2522 0x0000
21 #define RF2523 0x0001
22 #define RF2524 0x0002
23 #define RF2525 0x0003
24 #define RF2525E 0x0004
25 #define RF5222 0x0010
43 #define CSR_REG_BASE 0x0000
44 #define CSR_REG_SIZE 0x0174
45 #define EEPROM_BASE 0x0000
46 #define EEPROM_SIZE 0x0200
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/via/
Dvia_3d_reg.h27 #define HC_REG_BASE 0x0400
29 #define HC_REG_TRANS_SPACE 0x0040
31 #define HC_ParaN_MASK 0xffffffff
32 #define HC_Para_MASK 0x00ffffff
33 #define HC_SubA_MASK 0xff000000
37 #define HC_REG_TRANS_SET 0x003c
38 #define HC_ParaSubType_MASK 0xff000000
39 #define HC_ParaType_MASK 0x00ff0000
40 #define HC_ParaOS_MASK 0x0000ff00
41 #define HC_ParaAdr_MASK 0x000000ff
[all …]

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