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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra20-colibri.dtsi11 memory@0 {
17 reg = <0x00000000 0x10000000>;
32 pinctrl-0 = <&state_default>;
424 <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
426 <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
440 nand@0 {
441 reg = <0>;
449 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
477 reg = <0x34>;
506 regulator-name = "VDD_CPU_1.0V";
[all …]
Dtegra20-paz00.dts24 memory@0 {
25 reg = <0x00000000 0x20000000>;
51 pinctrl-0 = <&state_default>;
287 reg = <0x1e>;
300 reg = <0x7000c500 0x100>;
303 #size-cells = <0>;
317 emc-tables@0 {
318 nvidia,ram-code = <0x0>;
320 #size-cells = <0>;
326 nvidia,emc-registers = <0x0000000a 0x00000016
[all …]
Dtegra20-seaboard.dts21 memory@0 {
22 reg = <0x00000000 0x40000000>;
49 pinctrl-0 = <&state_default>;
340 reg = <0x1a>;
347 micdet-cfg = <0>;
349 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
355 reg = <0x44>;
362 reg = <0x68>;
376 #size-cells = <0>;
381 pinctrl-0 = <&state_i2cmux_ddc>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/
Dtegra20-colibri.dtsi11 memory@0 {
17 reg = <0x00000000 0x10000000>;
57 pinctrl-0 = <&state_default>;
449 <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
451 <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
469 nand@0 {
470 reg = <0>;
478 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
506 reg = <0x34>;
535 regulator-name = "VDD_CPU_1.0V";
[all …]
Dtegra20-paz00.dts28 memory@0 {
29 reg = <0x00000000 0x20000000>;
55 pinctrl-0 = <&state_default>;
303 reg = <0x1e>;
335 reg = <0x34>;
471 reg = <0x4c>;
484 nvidia,cpu-pwr-off-time = <0>;
486 nvidia,core-pwr-off-time = <0>;
494 emc-tables@0 {
495 nvidia,ram-code = <0x0>;
[all …]
Dtegra20-seaboard.dts21 memory@0 {
22 reg = <0x00000000 0x40000000>;
49 pinctrl-0 = <&state_default>;
342 reg = <0x1a>;
349 micdet-cfg = <0>;
351 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
357 reg = <0x44>;
364 reg = <0x68>;
386 reg = <0xc>;
393 reg = <0x34>;
[all …]
/kernel/linux/linux-6.6/drivers/media/rc/keymaps/
Drc-hisi-tv-demo.c12 { 0x00000092, KEY_NUMERIC_1},
13 { 0x00000093, KEY_NUMERIC_2},
14 { 0x000000cc, KEY_NUMERIC_3},
15 { 0x0000009f, KEY_NUMERIC_4},
16 { 0x0000008e, KEY_NUMERIC_5},
17 { 0x0000008f, KEY_NUMERIC_6},
18 { 0x000000c8, KEY_NUMERIC_7},
19 { 0x00000094, KEY_NUMERIC_8},
20 { 0x0000008a, KEY_NUMERIC_9},
21 { 0x0000008b, KEY_NUMERIC_0},
[all …]
/kernel/linux/linux-5.10/drivers/media/rc/keymaps/
Drc-hisi-tv-demo.c12 { 0x00000092, KEY_NUMERIC_1},
13 { 0x00000093, KEY_NUMERIC_2},
14 { 0x000000cc, KEY_NUMERIC_3},
15 { 0x0000009f, KEY_NUMERIC_4},
16 { 0x0000008e, KEY_NUMERIC_5},
17 { 0x0000008f, KEY_NUMERIC_6},
18 { 0x000000c8, KEY_NUMERIC_7},
19 { 0x00000094, KEY_NUMERIC_8},
20 { 0x0000008a, KEY_NUMERIC_9},
21 { 0x0000008b, KEY_NUMERIC_0},
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/
Ddsi_phy_7nm.xml.h56 #define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
58 #define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
60 #define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
62 #define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
64 #define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
66 #define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
68 #define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
70 #define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
72 #define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
74 #define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
[all …]
Ddsi_phy_10nm.xml.h56 #define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
58 #define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
60 #define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
62 #define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
64 #define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
66 #define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
68 #define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
70 #define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
72 #define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
74 #define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
[all …]
Ddsi_phy_28nm.xml.h56 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN()
58 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_0()
60 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_1()
62 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_2()
64 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_3()
66 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_4()
68 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0… in REG_DSI_28nm_PHY_LN_TEST_DATAPATH()
70 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_DEBUG_SEL()
72 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_TEST_STR_0()
74 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_TEST_STR_1()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/hdmi/
Dhdmi.xml.h50 HDCP_KEYS_STATE_NO_KEYS = 0,
61 DDC_WRITE = 0,
66 ACR_NONE = 0,
72 #define REG_HDMI_CTRL 0x00000000
73 #define HDMI_CTRL_ENABLE 0x00000001
74 #define HDMI_CTRL_HDMI 0x00000002
75 #define HDMI_CTRL_ENCRYPTED 0x00000004
77 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
78 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
80 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/hdmi/
Dhdmi.xml.h57 HDCP_KEYS_STATE_NO_KEYS = 0,
68 DDC_WRITE = 0,
73 ACR_NONE = 0,
79 #define REG_HDMI_CTRL 0x00000000
80 #define HDMI_CTRL_ENABLE 0x00000001
81 #define HDMI_CTRL_HDMI 0x00000002
82 #define HDMI_CTRL_ENCRYPTED 0x00000004
84 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
85 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
87 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h50 NON_BURST_SYNCH_PULSE = 0,
56 VID_DST_FORMAT_RGB565 = 0,
63 SWAP_RGB = 0,
72 TRIGGER_NONE = 0,
81 CMD_DST_FORMAT_RGB111 = 0,
90 LANE_SWAP_0123 = 0,
100 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
101 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
103 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra20-emc.yaml38 const: 0
41 const: 0
145 "^emc-table@[0-9]+$":
165 const: 0
172 "^emc-table@[0-9]+$":
199 reg = <0x7000f400 0x400>;
200 interrupts = <0 78 4>;
207 #interconnect-cells = <0>;
209 #size-cells = <0>;
213 emc-tables@0 {
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dp/
Ddp_reg.h10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dp/
Ddp_reg.h10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
[all …]
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/hal/
DHalHWImg8723B_MAC.c16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
31 pDM_Odm->TypeGLNA << 0 | in CheckPositive()
40 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) in CheckPositive()
42 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) in CheckPositive()
48 cond1 &= 0x000F0FFF; in CheckPositive()
49 driver1 &= 0x000F0FFF; in CheckPositive()
52 u32 bitMask = 0; in CheckPositive()
53 if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE */ in CheckPositive()
56 if ((cond1 & BIT0) != 0) /* GLNA */ in CheckPositive()
57 bitMask |= 0x000000FF; in CheckPositive()
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/
DHalHWImg8723B_MAC.c16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
31 pDM_Odm->TypeGLNA << 0 | in CheckPositive()
41 "===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n", in CheckPositive()
51 "===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n", in CheckPositive()
62 " (Platform, Interface) = (0x%X, 0x%X)\n", in CheckPositive()
72 " (Board, Package) = (0x%X, 0x%X)\n", in CheckPositive()
82 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) in CheckPositive()
84 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) in CheckPositive()
90 cond1 &= 0x000F0FFF; in CheckPositive()
91 driver1 &= 0x000F0FFF; in CheckPositive()
[all …]
/kernel/linux/linux-5.10/drivers/staging/media/rkisp1/
Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI BIT(0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/rockchip/rkisp1/
Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI (1 << 0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
Dtable.c8 0x800, 0x80040000,
9 0x804, 0x00000003,
10 0x808, 0x0000FC00,
11 0x80C, 0x0000000A,
12 0x810, 0x10001331,
13 0x814, 0x020C3D10,
14 0x818, 0x02200385,
15 0x81C, 0x00000000,
16 0x820, 0x01000100,
17 0x824, 0x00190204,
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
Dtable.c8 0x800, 0x80040000,
9 0x804, 0x00000003,
10 0x808, 0x0000FC00,
11 0x80C, 0x0000000A,
12 0x810, 0x10001331,
13 0x814, 0x020C3D10,
14 0x818, 0x02200385,
15 0x81C, 0x00000000,
16 0x820, 0x01000100,
17 0x824, 0x00190204,
[all …]

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