| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | prm33xx.h | 22 #define AM33XX_PRM_BASE 0x44E00000
29 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
30 #define AM33XX_PRM_PER_MOD 0x0C00
31 #define AM33XX_PRM_WKUP_MOD 0x0D00
32 #define AM33XX_PRM_MPU_MOD 0x0E00
33 #define AM33XX_PRM_DEVICE_MOD 0x0F00
34 #define AM33XX_PRM_RTC_MOD 0x1000
35 #define AM33XX_PRM_GFX_MOD 0x1100
36 #define AM33XX_PRM_CEFUSE_MOD 0x1200
41 #define AM33XX_REVISION_PRM_OFFSET 0x0000
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| D | prcm_mpu44xx.h | 27 #define OMAP4430_PRCM_MPU_BASE 0x48243000
33 #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
34 #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
35 #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
36 #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
39 #define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
40 #define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
53 #define OMAP4_REVISION_PRCM_OFFSET 0x0000
54 … OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
57 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
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| D | cm33xx.h | 25 #define AM33XX_CM_BASE 0x44e00000
31 #define AM33XX_CM_PER_MOD 0x0000
32 #define AM33XX_CM_WKUP_MOD 0x0400
33 #define AM33XX_CM_DPLL_MOD 0x0500
34 #define AM33XX_CM_MPU_MOD 0x0600
35 #define AM33XX_CM_DEVICE_MOD 0x0700
36 #define AM33XX_CM_RTC_MOD 0x0800
37 #define AM33XX_CM_GFX_MOD 0x0900
38 #define AM33XX_CM_CEFUSE_MOD 0x0A00
43 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
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| D | prm7xx.h | 26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
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| /kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
| D | cm33xx.h | 17 #define AM33XX_CM_BASE 0x44e00000
23 #define AM33XX_CM_PER_MOD 0x0000
24 #define AM33XX_CM_WKUP_MOD 0x0400
25 #define AM33XX_CM_DPLL_MOD 0x0500
26 #define AM33XX_CM_MPU_MOD 0x0600
27 #define AM33XX_CM_DEVICE_MOD 0x0700
28 #define AM33XX_CM_RTC_MOD 0x0800
29 #define AM33XX_CM_GFX_MOD 0x0900
30 #define AM33XX_CM_CEFUSE_MOD 0x0A00
33 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
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| D | prcm_mpu44xx.h | 27 #define OMAP4430_PRCM_MPU_BASE 0x48243000
33 #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
34 #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
35 #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
36 #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
39 #define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
40 #define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
53 #define OMAP4_REVISION_PRCM_OFFSET 0x0000
54 … OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
57 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
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| D | prm33xx.h | 14 #define AM33XX_PRM_BASE 0x44E00000
21 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
22 #define AM33XX_PRM_PER_MOD 0x0C00
23 #define AM33XX_PRM_WKUP_MOD 0x0D00
24 #define AM33XX_PRM_MPU_MOD 0x0E00
25 #define AM33XX_PRM_DEVICE_MOD 0x0F00
26 #define AM33XX_PRM_RTC_MOD 0x1000
27 #define AM33XX_PRM_GFX_MOD 0x1100
28 #define AM33XX_PRM_CEFUSE_MOD 0x1200
31 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/ast/ |
| D | ast_dram_tables.h | 12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/ast/ |
| D | ast_dram_tables.h | 12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
[all …]
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| /kernel/linux/linux-6.6/sound/soc/codecs/ |
| D | sgtl5000.h | 14 #define SGTL5000_CHIP_ID 0x0000
15 #define SGTL5000_CHIP_DIG_POWER 0x0002
16 #define SGTL5000_CHIP_CLK_CTRL 0x0004
17 #define SGTL5000_CHIP_I2S_CTRL 0x0006
18 #define SGTL5000_CHIP_SSS_CTRL 0x000a
19 #define SGTL5000_CHIP_ADCDAC_CTRL 0x000e
20 #define SGTL5000_CHIP_DAC_VOL 0x0010
21 #define SGTL5000_CHIP_PAD_STRENGTH 0x0014
22 #define SGTL5000_CHIP_ANA_ADC_CTRL 0x0020
23 #define SGTL5000_CHIP_ANA_HP_CTRL 0x0022
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| /kernel/linux/linux-5.10/sound/soc/codecs/ |
| D | sgtl5000.h | 14 #define SGTL5000_CHIP_ID 0x0000
15 #define SGTL5000_CHIP_DIG_POWER 0x0002
16 #define SGTL5000_CHIP_CLK_CTRL 0x0004
17 #define SGTL5000_CHIP_I2S_CTRL 0x0006
18 #define SGTL5000_CHIP_SSS_CTRL 0x000a
19 #define SGTL5000_CHIP_ADCDAC_CTRL 0x000e
20 #define SGTL5000_CHIP_DAC_VOL 0x0010
21 #define SGTL5000_CHIP_PAD_STRENGTH 0x0014
22 #define SGTL5000_CHIP_ANA_ADC_CTRL 0x0020
23 #define SGTL5000_CHIP_ANA_HP_CTRL 0x0022
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| /kernel/linux/linux-5.10/include/linux/ |
| D | microchipphy.h | 9 #define LAN88XX_INT_MASK (0x19)
10 #define LAN88XX_INT_MASK_MDINTPIN_EN_ (0x8000)
11 #define LAN88XX_INT_MASK_SPEED_CHANGE_ (0x4000)
12 #define LAN88XX_INT_MASK_LINK_CHANGE_ (0x2000)
13 #define LAN88XX_INT_MASK_FDX_CHANGE_ (0x1000)
14 #define LAN88XX_INT_MASK_AUTONEG_ERR_ (0x0800)
15 #define LAN88XX_INT_MASK_AUTONEG_DONE_ (0x0400)
16 #define LAN88XX_INT_MASK_POE_DETECT_ (0x0200)
17 #define LAN88XX_INT_MASK_SYMBOL_ERR_ (0x0100)
18 #define LAN88XX_INT_MASK_FAST_LINK_FAIL_ (0x0080)
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| /kernel/linux/linux-6.6/include/linux/ |
| D | microchipphy.h | 9 #define LAN88XX_INT_MASK (0x19)
10 #define LAN88XX_INT_MASK_MDINTPIN_EN_ (0x8000)
11 #define LAN88XX_INT_MASK_SPEED_CHANGE_ (0x4000)
12 #define LAN88XX_INT_MASK_LINK_CHANGE_ (0x2000)
13 #define LAN88XX_INT_MASK_FDX_CHANGE_ (0x1000)
14 #define LAN88XX_INT_MASK_AUTONEG_ERR_ (0x0800)
15 #define LAN88XX_INT_MASK_AUTONEG_DONE_ (0x0400)
16 #define LAN88XX_INT_MASK_POE_DETECT_ (0x0200)
17 #define LAN88XX_INT_MASK_SYMBOL_ERR_ (0x0100)
18 #define LAN88XX_INT_MASK_FAST_LINK_FAIL_ (0x0080)
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_scl_filters.c | 31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_scl_filters.c | 31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
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| /kernel/linux/linux-6.6/drivers/media/usb/gspca/ |
| D | spca501.c | 29 #define Arowana300KCMOSCamera 0
53 .priv = 0},
56 #define SPCA50X_REG_USB 0x2 /* spca505 501 */
65 #define SPCA501_SNAPBIT 0x80
66 #define SPCA501_SNAPCTRL 0x10
78 #define SPCA501_PROP_SNAP(d) ((d) & 0x40)
79 #define SPCA501_PROP_SNAP_CTRL(d) ((d) & 0x10)
80 #define SPCA501_PROP_COMP_THRESH(d) (((d) & 0x0e) >> 1)
81 #define SPCA501_PROP_COMP_QUANT(d) (((d) & 0x70) >> 4)
84 #define SPCA501_REG_CCDSP 0x01
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| /kernel/linux/linux-5.10/drivers/media/usb/gspca/ |
| D | spca501.c | 29 #define Arowana300KCMOSCamera 0
53 .priv = 0},
56 #define SPCA50X_REG_USB 0x2 /* spca505 501 */
65 #define SPCA501_SNAPBIT 0x80
66 #define SPCA501_SNAPCTRL 0x10
78 #define SPCA501_PROP_SNAP(d) ((d) & 0x40)
79 #define SPCA501_PROP_SNAP_CTRL(d) ((d) & 0x10)
80 #define SPCA501_PROP_COMP_THRESH(d) (((d) & 0x0e) >> 1)
81 #define SPCA501_PROP_COMP_QUANT(d) (((d) & 0x70) >> 4)
84 #define SPCA501_REG_CCDSP 0x01
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| /kernel/linux/linux-5.10/drivers/net/dsa/mv88e6xxx/ |
| D | port.h | 16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/rockchip/ |
| D | phy-rockchip-naneng-combphy.c | 3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
24 #define PHYREG6 0x14
29 #define PHYREG7 0x18
33 #define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
34 #define PHYREG7_RX_RTERM_SHIFT 0
37 #define PHYREG8 0x1C
40 #define PHYREG11 0x28
41 #define PHYREG11_SU_TRIM_0_7 0xF0
43 #define PHYREG12 0x2C
46 #define PHYREG13 0x30
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| /kernel/linux/linux-6.6/drivers/dma/dw-edma/ |
| D | dw-edma-v0-regs.h | 15 #define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)
16 #define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)
18 #define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)
21 #define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)
22 #define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)
25 #define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)
28 u32 ch_control1; /* 0x0000 */
29 u32 ch_control2; /* 0x0004 */
30 u32 transfer_size; /* 0x0008 */
32 u64 reg; /* 0x000c..0x0010 */
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| /kernel/linux/linux-6.6/include/linux/mfd/ |
| D | lochnagar1_regs.h | 15 #define LOCHNAGAR1_CDC_AIF1_SEL 0x0008
16 #define LOCHNAGAR1_CDC_AIF2_SEL 0x0009
17 #define LOCHNAGAR1_CDC_AIF3_SEL 0x000A
18 #define LOCHNAGAR1_CDC_MCLK1_SEL 0x000B
19 #define LOCHNAGAR1_CDC_MCLK2_SEL 0x000C
20 #define LOCHNAGAR1_CDC_AIF_CTRL1 0x000D
21 #define LOCHNAGAR1_CDC_AIF_CTRL2 0x000E
22 #define LOCHNAGAR1_EXT_AIF_CTRL 0x000F
23 #define LOCHNAGAR1_DSP_AIF1_SEL 0x0010
24 #define LOCHNAGAR1_DSP_AIF2_SEL 0x0011
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| D | idt8a340_reg.h | 3 * Based on 5.2.0, Family Programming Guide (Sept 30, 2020)
10 #define PAGE_ADDR_BASE 0x0000
11 #define PAGE_ADDR 0x00fc
13 #define HW_REVISION 0x8180
14 #define REV_ID 0x007a
16 #define HW_DPLL_0 (0x8a00)
17 #define HW_DPLL_1 (0x8b00)
18 #define HW_DPLL_2 (0x8c00)
19 #define HW_DPLL_3 (0x8d00)
20 #define HW_DPLL_4 (0x8e00)
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| /kernel/linux/linux-5.10/include/linux/mfd/ |
| D | lochnagar1_regs.h | 15 #define LOCHNAGAR1_CDC_AIF1_SEL 0x0008
16 #define LOCHNAGAR1_CDC_AIF2_SEL 0x0009
17 #define LOCHNAGAR1_CDC_AIF3_SEL 0x000A
18 #define LOCHNAGAR1_CDC_MCLK1_SEL 0x000B
19 #define LOCHNAGAR1_CDC_MCLK2_SEL 0x000C
20 #define LOCHNAGAR1_CDC_AIF_CTRL1 0x000D
21 #define LOCHNAGAR1_CDC_AIF_CTRL2 0x000E
22 #define LOCHNAGAR1_EXT_AIF_CTRL 0x000F
23 #define LOCHNAGAR1_DSP_AIF1_SEL 0x0010
24 #define LOCHNAGAR1_DSP_AIF2_SEL 0x0011
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| /kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7785.c | 70 [DIV4_P] = DIV4(0, 0x0f80, 0),
71 [DIV4_DU] = DIV4(4, 0x0ff0, 0),
72 [DIV4_GA] = DIV4(8, 0x0030, 0),
73 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
74 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
75 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
76 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
77 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
80 #define MSTPCR0 0xffc80030
81 #define MSTPCR1 0xffc80034
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| /kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7785.c | 70 [DIV4_P] = DIV4(0, 0x0f80, 0),
71 [DIV4_DU] = DIV4(4, 0x0ff0, 0),
72 [DIV4_GA] = DIV4(8, 0x0030, 0),
73 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
74 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
75 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
76 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
77 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
80 #define MSTPCR0 0xffc80030
81 #define MSTPCR1 0xffc80034
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