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/kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/
Ddw_hdmi-rockchip.c22 #define RK3228_GRF_SOC_CON2 0x0408
25 #define RK3228_GRF_SOC_CON6 0x0418
30 #define RK3288_GRF_SOC_CON6 0x025C
32 #define RK3328_GRF_SOC_CON2 0x0408
37 #define RK3328_GRF_SOC_CON3 0x040c
43 #define RK3328_GRF_SOC_CON4 0x0410
50 #define RK3399_GRF_SOC_CON20 0x6250
83 { 0x00b3, 0x0000},
84 { 0x2153, 0x0000},
85 { 0x40f3, 0x0000}
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
Dcm2_44xx.h26 #define OMAP4430_CM2_BASE 0x4a008000
32 #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM2_CKGEN_INST 0x0100
34 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
35 #define OMAP4430_CM2_CORE_INST 0x0700
36 #define OMAP4430_CM2_IVAHD_INST 0x0f00
37 #define OMAP4430_CM2_CAM_INST 0x1000
38 #define OMAP4430_CM2_DSS_INST 0x1100
39 #define OMAP4430_CM2_GFX_INST 0x1200
40 #define OMAP4430_CM2_L3INIT_INST 0x1300
[all …]
Dcm1_54xx.h22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
28 #define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300
31 #define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400
32 #define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500
33 #define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00
34 #define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00
37 #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
38 #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000
[all …]
Dcm33xx.h25 #define AM33XX_CM_BASE 0x44e00000
31 #define AM33XX_CM_PER_MOD 0x0000
32 #define AM33XX_CM_WKUP_MOD 0x0400
33 #define AM33XX_CM_DPLL_MOD 0x0500
34 #define AM33XX_CM_MPU_MOD 0x0600
35 #define AM33XX_CM_DEVICE_MOD 0x0700
36 #define AM33XX_CM_RTC_MOD 0x0800
37 #define AM33XX_CM_GFX_MOD 0x0900
38 #define AM33XX_CM_CEFUSE_MOD 0x0A00
43 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
Dcm1_44xx.h26 #define OMAP4430_CM1_BASE 0x4a004000
32 #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM1_CKGEN_INST 0x0100
34 #define OMAP4430_CM1_MPU_INST 0x0300
35 #define OMAP4430_CM1_TESLA_INST 0x0400
36 #define OMAP4430_CM1_ABE_INST 0x0500
37 #define OMAP4430_CM1_RESTORE_INST 0x0e00
38 #define OMAP4430_CM1_INSTR_INST 0x0f00
41 #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
42 #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
[all …]
Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
Dcm2_7xx.h23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
Dcm2_54xx.h22 #define OMAP54XX_CM_CORE_BASE 0x4a008000
28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600
31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700
32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200
33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300
34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400
35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500
36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
[all …]
Dprm3xxx.h33 #define OMAP3_PRM_REVISION_OFFSET 0x0004
34 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
35 #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
36 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
38 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
39 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
40 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
41 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
44 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
45 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/rockchip/
Ddw_hdmi-rockchip.c22 #define RK3228_GRF_SOC_CON2 0x0408
25 #define RK3228_GRF_SOC_CON6 0x0418
30 #define RK3288_GRF_SOC_CON6 0x025C
32 #define RK3328_GRF_SOC_CON2 0x0408
37 #define RK3328_GRF_SOC_CON3 0x040c
43 #define RK3328_GRF_SOC_CON4 0x0410
50 #define RK3399_GRF_SOC_CON20 0x6250
53 #define RK3568_GRF_VO_CON1 0x0364
95 { 0x00b3, 0x0000},
96 { 0x2153, 0x0000},
[all …]
/kernel/linux/linux-6.6/include/linux/platform_data/
Dgpio-omap.h18 #define OMAP1_MPUIO_BASE 0xfffb5000
24 #define OMAP_MPUIO_INPUT_LATCH 0x00
25 #define OMAP_MPUIO_OUTPUT 0x04
26 #define OMAP_MPUIO_IO_CNTL 0x08
27 #define OMAP_MPUIO_KBR_LATCH 0x10
28 #define OMAP_MPUIO_KBC 0x14
29 #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
30 #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
31 #define OMAP_MPUIO_KBD_INT 0x20
32 #define OMAP_MPUIO_GPIO_INT 0x24
[all …]
/kernel/linux/linux-5.10/include/linux/platform_data/
Dgpio-omap.h18 #define OMAP1_MPUIO_BASE 0xfffb5000
24 #define OMAP_MPUIO_INPUT_LATCH 0x00
25 #define OMAP_MPUIO_OUTPUT 0x04
26 #define OMAP_MPUIO_IO_CNTL 0x08
27 #define OMAP_MPUIO_KBR_LATCH 0x10
28 #define OMAP_MPUIO_KBC 0x14
29 #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
30 #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
31 #define OMAP_MPUIO_KBD_INT 0x20
32 #define OMAP_MPUIO_GPIO_INT 0x24
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx6qdl-mba6.dtsi30 pinctrl-0 = <&pinctrl_gpiobeeper>;
37 pinctrl-0 = <&pinctrl_gpiobuttons>;
64 pinctrl-0 = <&pinctrl_gpioled>;
90 pinctrl-0 = <&pinctrl_regpcie>;
95 gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
112 pinctrl-0 = <&pinctrl_audmux>;
155 pinctrl-0 = <&pinctrl_can1>;
161 pinctrl-0 = <&pinctrl_can2>;
167 pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>;
168 cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>;
[all …]
Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dprm3xxx.h33 #define OMAP3_PRM_REVISION_OFFSET 0x0004
34 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
35 #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
36 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
38 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
39 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
40 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
41 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
44 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
45 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
[all …]
/kernel/linux/linux-6.6/Documentation/admin-guide/media/
Ddvb-usb-cinergyT2-cardlist.rst11 :stub-columns: 0
15 * - TerraTec/qanu USB2.0 Highspeed DVB-T Receiver
16 - 0ccd:0x0038
/kernel/linux/linux-5.10/Documentation/admin-guide/media/
Ddvb-usb-cinergyT2-cardlist.rst11 :stub-columns: 0
15 * - TerraTec/qanu USB2.0 Highspeed DVB-T Receiver
16 - 0ccd:0x0038
/kernel/linux/linux-6.6/include/linux/
Drio_ids.h12 #define RIO_VID_IDT 0x0038
13 #define RIO_DID_IDT70K200 0x0310
14 #define RIO_DID_IDTCPS8 0x035c
15 #define RIO_DID_IDTCPS12 0x035d
16 #define RIO_DID_IDTCPS16 0x035b
17 #define RIO_DID_IDTCPS6Q 0x035f
18 #define RIO_DID_IDTCPS10Q 0x035e
19 #define RIO_DID_IDTCPS1848 0x0374
20 #define RIO_DID_IDTCPS1432 0x0375
21 #define RIO_DID_IDTCPS1616 0x0379
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/kernel/linux/linux-6.6/drivers/media/usb/gspca/
Dxirlink_cit.c29 module_param(ibm_netcam_pro, int, 0);
44 #define CIT_MODEL0 0 /* bcd version 0.01 cams ie the xvp-500 */
125 {0, 0x0000, 0x010c},
126 {0, 0x0006, 0x012c},
127 {0, 0x0078, 0x012d},
128 {0, 0x0046, 0x012f},
129 {0, 0xd141, 0x0124},
130 {0, 0x0000, 0x0127},
131 {0, 0xfea8, 0x0124},
132 {1, 0x0000, 0x0116},
[all …]

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