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/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
Dcm33xx.h25 #define AM33XX_CM_BASE 0x44e00000
31 #define AM33XX_CM_PER_MOD 0x0000
32 #define AM33XX_CM_WKUP_MOD 0x0400
33 #define AM33XX_CM_DPLL_MOD 0x0500
34 #define AM33XX_CM_MPU_MOD 0x0600
35 #define AM33XX_CM_DEVICE_MOD 0x0700
36 #define AM33XX_CM_RTC_MOD 0x0800
37 #define AM33XX_CM_GFX_MOD 0x0900
38 #define AM33XX_CM_CEFUSE_MOD 0x0A00
43 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
Dprm3xxx.h33 #define OMAP3_PRM_REVISION_OFFSET 0x0004
34 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
35 #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
36 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
38 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
39 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
40 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
41 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
44 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
45 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
[all …]
Dcm2_7xx.h23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
/kernel/linux/linux-5.10/drivers/media/usb/gspca/
Dbenq.c39 if (gspca_dev->usb_err < 0) in reg_w()
41 ret = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), in reg_w()
42 0x02, in reg_w()
47 0, in reg_w()
49 if (ret < 0) { in reg_w()
62 return 0; in sd_config()
68 return 0; in sd_init()
77 /* create 4 URBs - 2 on endpoint 0x83 and 2 on 0x082 */ in sd_start()
83 for (n = 0; n < 4; n++) { in sd_start()
101 n & 1 ? 0x82 : 0x83); in sd_start()
[all …]
/kernel/linux/linux-6.6/drivers/media/usb/gspca/
Dbenq.c39 if (gspca_dev->usb_err < 0) in reg_w()
41 ret = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), in reg_w()
42 0x02, in reg_w()
47 0, in reg_w()
49 if (ret < 0) { in reg_w()
62 return 0; in sd_config()
68 return 0; in sd_init()
77 /* create 4 URBs - 2 on endpoint 0x83 and 2 on 0x082 */ in sd_start()
83 for (n = 0; n < 4; n++) { in sd_start()
101 n & 1 ? 0x82 : 0x83); in sd_start()
[all …]
/kernel/linux/linux-6.6/include/linux/platform_data/
Dgpio-omap.h18 #define OMAP1_MPUIO_BASE 0xfffb5000
24 #define OMAP_MPUIO_INPUT_LATCH 0x00
25 #define OMAP_MPUIO_OUTPUT 0x04
26 #define OMAP_MPUIO_IO_CNTL 0x08
27 #define OMAP_MPUIO_KBR_LATCH 0x10
28 #define OMAP_MPUIO_KBC 0x14
29 #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
30 #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
31 #define OMAP_MPUIO_KBD_INT 0x20
32 #define OMAP_MPUIO_GPIO_INT 0x24
[all …]
/kernel/linux/linux-5.10/include/linux/platform_data/
Dgpio-omap.h18 #define OMAP1_MPUIO_BASE 0xfffb5000
24 #define OMAP_MPUIO_INPUT_LATCH 0x00
25 #define OMAP_MPUIO_OUTPUT 0x04
26 #define OMAP_MPUIO_IO_CNTL 0x08
27 #define OMAP_MPUIO_KBR_LATCH 0x10
28 #define OMAP_MPUIO_KBC 0x14
29 #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
30 #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
31 #define OMAP_MPUIO_KBD_INT 0x20
32 #define OMAP_MPUIO_GPIO_INT 0x24
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_6_1_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
Dnbio_7_0_offset.h27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
Dnbio_7_4_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_6_1_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
Dnbio_7_0_offset.h27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
Dnbio_7_4_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
/kernel/linux/linux-5.10/sound/soc/mediatek/mt2701/
Dmt2701-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON4 0x0010
14 #define AUDIO_TOP_CON5 0x0014
15 #define AFE_DAIBT_CON0 0x001c
16 #define AFE_MRGIF_CON 0x003c
17 #define ASMI_TIMING_CON1 0x0100
18 #define ASMO_TIMING_CON1 0x0104
19 #define PWR1_ASM_CON1 0x0108
20 #define ASYS_TOP_CON 0x0600
21 #define ASYS_I2SIN1_CON 0x0604
[all …]
/kernel/linux/linux-6.6/sound/soc/mediatek/mt2701/
Dmt2701-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON4 0x0010
14 #define AUDIO_TOP_CON5 0x0014
15 #define AFE_DAIBT_CON0 0x001c
16 #define AFE_MRGIF_CON 0x003c
17 #define ASMI_TIMING_CON1 0x0100
18 #define ASMO_TIMING_CON1 0x0104
19 #define PWR1_ASM_CON1 0x0108
20 #define ASYS_TOP_CON 0x0600
21 #define ASYS_I2SIN1_CON 0x0604
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dprm3xxx.h33 #define OMAP3_PRM_REVISION_OFFSET 0x0004
34 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
35 #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
36 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
38 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
39 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
40 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
41 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
44 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
45 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
/kernel/linux/linux-5.10/drivers/clk/sirf/
Datlas6.h2 #define SIRFSOC_CLKC_CLK_EN0 0x0000
3 #define SIRFSOC_CLKC_CLK_EN1 0x0004
4 #define SIRFSOC_CLKC_REF_CFG 0x0020
5 #define SIRFSOC_CLKC_CPU_CFG 0x0024
6 #define SIRFSOC_CLKC_MEM_CFG 0x0028
7 #define SIRFSOC_CLKC_MEMDIV_CFG 0x002C
8 #define SIRFSOC_CLKC_SYS_CFG 0x0030
9 #define SIRFSOC_CLKC_IO_CFG 0x0034
10 #define SIRFSOC_CLKC_DSP_CFG 0x0038
11 #define SIRFSOC_CLKC_GFX_CFG 0x003c
[all …]

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