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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_6_1_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
Dnbio_7_0_offset.h27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
Dnbio_7_4_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
Dnbio_2_3_offset.h27 // base address: 0x0
28 …BIF_BX_PF_MM_INDEX 0x0000
29 …ne mmBIF_BX_PF_MM_INDEX_BASE_IDX 0
30 …BIF_BX_PF_MM_DATA 0x0001
31 …ne mmBIF_BX_PF_MM_DATA_BASE_IDX 0
32 …BIF_BX_PF_MM_INDEX_HI 0x0006
33 …ne mmBIF_BX_PF_MM_INDEX_HI_BASE_IDX 0
37 // base address: 0x0
38 …SYSHUB_INDEX_OVLP 0x0008
39 …ne mmSYSHUB_INDEX_OVLP_BASE_IDX 0
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_6_1_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
Dnbio_7_0_offset.h27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
Dnbio_7_4_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
Dnbio_2_3_offset.h27 // base address: 0x0
28 …BIF_BX_PF_MM_INDEX 0x0000
29 …ne mmBIF_BX_PF_MM_INDEX_BASE_IDX 0
30 …BIF_BX_PF_MM_DATA 0x0001
31 …ne mmBIF_BX_PF_MM_DATA_BASE_IDX 0
32 …BIF_BX_PF_MM_INDEX_HI 0x0006
33 …ne mmBIF_BX_PF_MM_INDEX_HI_BASE_IDX 0
37 // base address: 0x0
38 …SYSHUB_INDEX_OVLP 0x0008
39 …ne mmSYSHUB_INDEX_OVLP_BASE_IDX 0
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dcm2_44xx.h26 #define OMAP4430_CM2_BASE 0x4a008000
32 #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM2_CKGEN_INST 0x0100
34 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
35 #define OMAP4430_CM2_CORE_INST 0x0700
36 #define OMAP4430_CM2_IVAHD_INST 0x0f00
37 #define OMAP4430_CM2_CAM_INST 0x1000
38 #define OMAP4430_CM2_DSS_INST 0x1100
39 #define OMAP4430_CM2_GFX_INST 0x1200
40 #define OMAP4430_CM2_L3INIT_INST 0x1300
[all …]
Dcm1_54xx.h22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
28 #define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300
31 #define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400
32 #define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500
33 #define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00
34 #define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00
37 #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
38 #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000
[all …]
Dcm2_7xx.h23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
Dcm33xx.h25 #define AM33XX_CM_BASE 0x44e00000
31 #define AM33XX_CM_PER_MOD 0x0000
32 #define AM33XX_CM_WKUP_MOD 0x0400
33 #define AM33XX_CM_DPLL_MOD 0x0500
34 #define AM33XX_CM_MPU_MOD 0x0600
35 #define AM33XX_CM_DEVICE_MOD 0x0700
36 #define AM33XX_CM_RTC_MOD 0x0800
37 #define AM33XX_CM_GFX_MOD 0x0900
38 #define AM33XX_CM_CEFUSE_MOD 0x0A00
43 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
Dcm1_44xx.h26 #define OMAP4430_CM1_BASE 0x4a004000
32 #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM1_CKGEN_INST 0x0100
34 #define OMAP4430_CM1_MPU_INST 0x0300
35 #define OMAP4430_CM1_TESLA_INST 0x0400
36 #define OMAP4430_CM1_ABE_INST 0x0500
37 #define OMAP4430_CM1_RESTORE_INST 0x0e00
38 #define OMAP4430_CM1_INSTR_INST 0x0f00
41 #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
42 #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
/kernel/linux/linux-6.6/drivers/clk/mediatek/
Dclk-mt8195-apmixedsys.c17 .set_ofs = 0x8,
18 .clr_ofs = 0x8,
19 .sta_ofs = 0x8,
62 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
63 0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9),
64 PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
65 0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9),
66 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
67 0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0, 0x0368, 0, 9),
68 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
[all …]
Dclk-mt8186-topckgen.c22 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2, 0),
23 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2, 0),
24 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4, 0),
25 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16, 0),
26 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2, 0),
28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4, 0),
29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
/kernel/linux/linux-6.6/include/linux/
Di8042.h13 #define I8042_CMD_CTL_RCTR 0x0120
14 #define I8042_CMD_CTL_WCTR 0x1060
15 #define I8042_CMD_CTL_TEST 0x01aa
17 #define I8042_CMD_KBD_DISABLE 0x00ad
18 #define I8042_CMD_KBD_ENABLE 0x00ae
19 #define I8042_CMD_KBD_TEST 0x01ab
20 #define I8042_CMD_KBD_LOOP 0x11d2
22 #define I8042_CMD_AUX_DISABLE 0x00a7
23 #define I8042_CMD_AUX_ENABLE 0x00a8
24 #define I8042_CMD_AUX_TEST 0x01a9
[all …]
/kernel/linux/linux-5.10/include/linux/
Di8042.h12 #define I8042_CMD_CTL_RCTR 0x0120
13 #define I8042_CMD_CTL_WCTR 0x1060
14 #define I8042_CMD_CTL_TEST 0x01aa
16 #define I8042_CMD_KBD_DISABLE 0x00ad
17 #define I8042_CMD_KBD_ENABLE 0x00ae
18 #define I8042_CMD_KBD_TEST 0x01ab
19 #define I8042_CMD_KBD_LOOP 0x11d2
21 #define I8042_CMD_AUX_DISABLE 0x00a7
22 #define I8042_CMD_AUX_ENABLE 0x00a8
23 #define I8042_CMD_AUX_TEST 0x01a9
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dintel,lgm-emmc-phy.yaml31 const: 0
55 reg = <0xe0200000 0x100>;
61 reg = <0x00a8 0x10>;
63 #phy-cells = <0>;
70 reg = <0x20290000 0x54>;
73 #phy-cells = <0>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dintel,lgm-emmc-phy.yaml31 const: 0
55 reg = <0xe0200000 0x100>;
61 reg = <0x00a8 0x10>;
63 #phy-cells = <0>;
70 reg = <0x20290000 0x54>;
73 #phy-cells = <0>;
/kernel/linux/linux-6.6/arch/s390/include/asm/
Dlowcore.h25 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
26 __u32 ipl_parmblock_ptr; /* 0x0014 */
27 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
28 __u32 ext_params; /* 0x0080 */
31 __u16 ext_cpu_addr; /* 0x0084 */
32 __u16 ext_int_code; /* 0x0086 */
36 __u32 svc_int_code; /* 0x0088 */
39 __u16 pgm_ilc; /* 0x008c */
40 __u16 pgm_code; /* 0x008e */
44 __u32 data_exc_code; /* 0x0090 */
[all …]

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