Searched +full:0 +full:x01c (Results 1 – 25 of 442) sorted by relevance
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| /kernel/linux/linux-5.10/drivers/gpu/drm/vc4/ |
| D | vc4_hdmi_regs.h | 6 #define VC4_HDMI_PACKET_STRIDE 0x24
9 VC4_INVALID = 0,
147 VC4_HD_REG(HDMI_M_CTL, 0x000c),
148 VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
149 VC4_HD_REG(HDMI_MAI_THR, 0x0018),
150 VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
151 VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
152 VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
153 VC4_HD_REG(HDMI_VID_CTL, 0x0038),
154 VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp.h | 10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/meson/ |
| D | axg-audio.h | 16 #define AUDIO_CLK_GATE_EN 0x000
17 #define AUDIO_MCLK_A_CTRL 0x004
18 #define AUDIO_MCLK_B_CTRL 0x008
19 #define AUDIO_MCLK_C_CTRL 0x00C
20 #define AUDIO_MCLK_D_CTRL 0x010
21 #define AUDIO_MCLK_E_CTRL 0x014
22 #define AUDIO_MCLK_F_CTRL 0x018
23 #define AUDIO_MST_PAD_CTRL0 0x01c
24 #define AUDIO_MST_PAD_CTRL1 0x020
25 #define AUDIO_SW_RESET 0x024
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/vc4/ |
| D | vc4_hdmi_regs.h | 8 #define VC4_HDMI_PACKET_STRIDE 0x24
11 VC4_INVALID = 0,
166 VC4_HD_REG(HDMI_M_CTL, 0x000c),
167 VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
168 VC4_HD_REG(HDMI_MAI_THR, 0x0018),
169 VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
170 VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
171 VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
172 VC4_HD_REG(HDMI_VID_CTL, 0x0038),
173 VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/meson/ |
| D | axg-audio.h | 16 #define AUDIO_CLK_GATE_EN 0x000
17 #define AUDIO_MCLK_A_CTRL 0x004
18 #define AUDIO_MCLK_B_CTRL 0x008
19 #define AUDIO_MCLK_C_CTRL 0x00C
20 #define AUDIO_MCLK_D_CTRL 0x010
21 #define AUDIO_MCLK_E_CTRL 0x014
22 #define AUDIO_MCLK_F_CTRL 0x018
23 #define AUDIO_MST_PAD_CTRL0 0x01c
24 #define AUDIO_MST_PAD_CTRL1 0x020
25 #define AUDIO_SW_RESET 0x024
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| D | clk-mt8195-apusys_pll.c | 18 #define MT8195_PLL_EN_BIT (0)
19 #define MT8195_PCW_SHIFT (0)
33 .en_mask = 0, \
34 .flags = 0, \
35 .rst_bar_mask = 0, \
42 .tuner_reg = 0, \
43 .tuner_en_reg = 0, \
44 .tuner_en_bit = 0, \
47 .pcw_chg_reg = 0, \
48 .en_reg = 0, \
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp-qserdes-txrx.h | 10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
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| D | phy-qcom-qmp-qserdes-txrx-v4.h | 10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
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| D | phy-qcom-qmp-qserdes-txrx-v5.h | 11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
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| D | phy-qcom-qmp-pcs-pcie-v4_20.h | 9 #define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
10 #define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
11 #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
12 #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
13 #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
14 #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
15 #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
16 #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
17 #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
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| D | phy-qcom-qmp-pcs-pcie-v6_20.h | 10 #define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c
11 #define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018
12 #define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
13 #define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
14 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
15 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
16 #define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c
17 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
18 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184
19 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c
[all …]
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| D | phy-qcom-qmp-pcs-pcie-v5_20.h | 10 #define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c
11 #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
12 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
13 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
14 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
15 #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
16 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
17 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
18 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
19 #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
[all …]
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| D | phy-qcom-qmp-pcs-usb-v5.h | 10 #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
11 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
12 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
13 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
14 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
15 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
16 #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
17 #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
18 #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
19 #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
[all …]
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| D | phy-qcom-qmp-pcs-usb-v4.h | 10 #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
11 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
12 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
13 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
14 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
15 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
16 #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
17 #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
18 #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
19 #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/mediatek/ |
| D | mtk_wed_wo.h | 37 MTK_WED_WO_EVT_LOG_DUMP = 0x1,
38 MTK_WED_WO_EVT_PROFILING = 0x2,
39 MTK_WED_WO_EVT_RXCNT_INFO = 0x3,
47 MTK_WED_WARP_CMD_FLAG_RSP = BIT(0),
52 #define MTK_WED_WO_CPU_MCUSYS_RESET_ADDR 0x15194050
53 #define MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK 0x20
54 #define MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK 0x1
95 #define MTK_WO_MCU_CFG_LS_BASE 0
96 #define MTK_WO_MCU_CFG_LS_HW_VER_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x000)
97 #define MTK_WO_MCU_CFG_LS_FW_VER_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x004)
[all …]
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| /kernel/linux/linux-6.6/drivers/dma/dw-axi-dmac/ |
| D | dw-axi-dmac.h | 23 #define DMAC_MAX_BLK_SIZE 0x200000
147 #define COMMON_REG_LEN 0x100
148 #define CHAN_REG_LEN 0x100
151 #define DMAC_ID 0x000 /* R DMAC ID */
152 #define DMAC_COMPVER 0x008 /* R DMAC Component Version */
153 #define DMAC_CFG 0x010 /* R/W DMAC Configuration */
154 #define DMAC_CHEN 0x018 /* R/W DMAC Channel Enable */
155 #define DMAC_CHEN_L 0x018 /* R/W DMAC Channel Enable 00-31 */
156 #define DMAC_CHEN_H 0x01C /* R/W DMAC Channel Enable 32-63 */
157 #define DMAC_CHSUSPREG 0x020 /* R/W DMAC Channel Suspend */
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/via/ |
| D | accel.h | 14 #define MMIO_VGABASE 0x8000
15 #define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)
16 #define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)
17 #define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)
18 #define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)
21 #define HW_Cursor_ON 0
27 #define VIA_MMIO_BLTBASE 0x200000
28 #define VIA_MMIO_BLTSIZE 0x200000
31 #define VIA_REG_GECMD 0x000
32 #define VIA_REG_GEMODE 0x004
[all …]
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| /kernel/linux/linux-6.6/drivers/video/fbdev/via/ |
| D | accel.h | 14 #define MMIO_VGABASE 0x8000
15 #define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)
16 #define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)
17 #define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)
18 #define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)
21 #define HW_Cursor_ON 0
27 #define VIA_MMIO_BLTBASE 0x200000
28 #define VIA_MMIO_BLTSIZE 0x200000
31 #define VIA_REG_GECMD 0x000
32 #define VIA_REG_GEMODE 0x004
[all …]
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| /kernel/linux/linux-5.10/drivers/dma/dw-edma/ |
| D | dw-edma-v0-regs.h | 15 #define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)
16 #define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)
18 #define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)
21 #define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)
22 #define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)
25 #define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)
28 u32 ch_control1; /* 0x000 */
29 u32 ch_control2; /* 0x004 */
30 u32 transfer_size; /* 0x008 */
31 u32 sar_low; /* 0x00c */
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | brcm,spi-bcm-qspi.yaml | 103 reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
105 interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;
115 #address-cells = <0x1>;
116 #size-cells = <0x0>;
118 flash@0 {
119 #size-cells = <0x2>;
120 #address-cells = <0x2>;
122 reg = <0x0>;
123 spi-max-frequency = <0x2625a00>;
132 reg = <0xf0416000 0x180>;
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/mediatek/mdp3/ |
| D | mdp_reg_rsz.h | 10 #define PRZ_ENABLE 0x000
11 #define PRZ_CONTROL_1 0x004
12 #define PRZ_CONTROL_2 0x008
13 #define PRZ_INPUT_IMAGE 0x010
14 #define PRZ_OUTPUT_IMAGE 0x014
15 #define PRZ_HORIZONTAL_COEFF_STEP 0x018
16 #define PRZ_VERTICAL_COEFF_STEP 0x01c
17 #define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET 0x020
18 #define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET 0x024
19 #define PRZ_LUMA_VERTICAL_INTEGER_OFFSET 0x028
[all …]
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| D | mdp_reg_wdma.h | 10 #define WDMA_EN 0x008
11 #define WDMA_RST 0x00c
12 #define WDMA_CFG 0x014
13 #define WDMA_SRC_SIZE 0x018
14 #define WDMA_CLIP_SIZE 0x01c
15 #define WDMA_CLIP_COORD 0x020
16 #define WDMA_DST_W_IN_BYTE 0x028
17 #define WDMA_ALPHA 0x02c
18 #define WDMA_BUF_CON2 0x03c
19 #define WDMA_DST_UV_PITCH 0x078
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | vf610-pinfunc.h | 14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hwio.h | 13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define INTR2_CLEAR 0x02c
20 #define HIST_INTR_EN 0x01c
21 #define HIST_INTR_STATUS 0x020
22 #define HIST_INTR_CLEAR 0x024
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/vf/ |
| D | vf610-pinfunc.h | 14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
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