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15 #define MUX_SEL_AUD 0x020016 #define MUX_ENABLE_AUD 0x030017 #define MUX_STAT_AUD 0x040018 #define MUX_IGNORE_AUD 0x050019 #define DIV_AUD0 0x060020 #define DIV_AUD1 0x060421 #define DIV_STAT_AUD0 0x070022 #define DIV_STAT_AUD1 0x070423 #define EN_ACLK_AUD 0x080024 #define EN_PCLK_AUD 0x0900[all …]
18 #define AM43XX_PRM_OCP_SOCKET_INST 0x000019 #define AM43XX_PRM_MPU_INST 0x030020 #define AM43XX_PRM_GFX_INST 0x040021 #define AM43XX_PRM_RTC_INST 0x050022 #define AM43XX_PRM_TAMPER_INST 0x060023 #define AM43XX_PRM_CEFUSE_INST 0x070024 #define AM43XX_PRM_PER_INST 0x080025 #define AM43XX_PRM_WKUP_INST 0x200026 #define AM43XX_PRM_DEVICE_INST 0x400029 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004[all …]
21 #define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */22 #define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */23 #define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */24 #define TI81XX_CM_SGX_MOD 0x0900 /* 256B */27 #define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */28 #define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */29 #define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */32 #define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x000033 #define TI81XX_CM_ALWON_L3_MED_CLKDM 0x000434 #define TI81XX_CM_ETHERNET_CLKDM 0x0004[all …]
26 #define OMAP4430_CM2_BASE 0x4a00800032 #define OMAP4430_CM2_OCP_SOCKET_INST 0x000033 #define OMAP4430_CM2_CKGEN_INST 0x010034 #define OMAP4430_CM2_ALWAYS_ON_INST 0x060035 #define OMAP4430_CM2_CORE_INST 0x070036 #define OMAP4430_CM2_IVAHD_INST 0x0f0037 #define OMAP4430_CM2_CAM_INST 0x100038 #define OMAP4430_CM2_DSS_INST 0x110039 #define OMAP4430_CM2_GFX_INST 0x120040 #define OMAP4430_CM2_L3INIT_INST 0x1300[all …]
12 #define RIO_VID_FREESCALE 0x000213 #define RIO_DID_MPC8560 0x000315 #define RIO_VID_TUNDRA 0x000d16 #define RIO_DID_TSI500 0x050017 #define RIO_DID_TSI568 0x056818 #define RIO_DID_TSI572 0x057219 #define RIO_DID_TSI574 0x057420 #define RIO_DID_TSI576 0x0578 /* Same ID as Tsi578 */21 #define RIO_DID_TSI577 0x057722 #define RIO_DID_TSI578 0x0578[all …]
22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a00400028 #define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x000029 #define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x010030 #define OMAP54XX_CM_CORE_AON_MPU_INST 0x030031 #define OMAP54XX_CM_CORE_AON_DSP_INST 0x040032 #define OMAP54XX_CM_CORE_AON_ABE_INST 0x050035 #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x000036 #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x000037 #define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x0000
26 #define OMAP4430_CM1_BASE 0x4a00400032 #define OMAP4430_CM1_OCP_SOCKET_INST 0x000033 #define OMAP4430_CM1_CKGEN_INST 0x010034 #define OMAP4430_CM1_MPU_INST 0x030035 #define OMAP4430_CM1_TESLA_INST 0x040036 #define OMAP4430_CM1_ABE_INST 0x050039 #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x000040 #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x000041 #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
15 #define AM43XX_PRM_OCP_SOCKET_INST 0x000016 #define AM43XX_PRM_MPU_INST 0x030017 #define AM43XX_PRM_GFX_INST 0x040018 #define AM43XX_PRM_RTC_INST 0x050019 #define AM43XX_PRM_TAMPER_INST 0x060020 #define AM43XX_PRM_CEFUSE_INST 0x070021 #define AM43XX_PRM_PER_INST 0x080022 #define AM43XX_PRM_WKUP_INST 0x200023 #define AM43XX_PRM_DEVICE_INST 0x400026 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004[all …]
13 #define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */14 #define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */15 #define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */16 #define TI81XX_CM_SGX_MOD 0x0900 /* 256B */19 #define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */20 #define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */21 #define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */24 #define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x000025 #define TI81XX_CM_ALWON_L3_MED_CLKDM 0x000426 #define TI81XX_CM_ETHERNET_CLKDM 0x0004[all …]
22 #define OMAP54XX_CM_CORE_BASE 0x4a00800028 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x000029 #define OMAP54XX_CM_CORE_CKGEN_INST 0x010030 #define OMAP54XX_CM_CORE_COREAON_INST 0x060031 #define OMAP54XX_CM_CORE_CORE_INST 0x070032 #define OMAP54XX_CM_CORE_IVA_INST 0x120033 #define OMAP54XX_CM_CORE_CAM_INST 0x130034 #define OMAP54XX_CM_CORE_DSS_INST 0x140035 #define OMAP54XX_CM_CORE_GPU_INST 0x150036 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600[all …]
24 #define OMAP54XX_PRM_BASE 0x4ae0600031 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x000032 #define OMAP54XX_PRM_CKGEN_INST 0x010033 #define OMAP54XX_PRM_MPU_INST 0x030034 #define OMAP54XX_PRM_DSP_INST 0x040035 #define OMAP54XX_PRM_ABE_INST 0x050036 #define OMAP54XX_PRM_COREAON_INST 0x060037 #define OMAP54XX_PRM_CORE_INST 0x070038 #define OMAP54XX_PRM_IVA_INST 0x120039 #define OMAP54XX_PRM_CAM_INST 0x1300[all …]
23 #define DRA7XX_CM_CORE_AON_BASE 0x4a00500029 #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x000030 #define DRA7XX_CM_CORE_AON_CKGEN_INST 0x010031 #define DRA7XX_CM_CORE_AON_MPU_INST 0x030032 #define DRA7XX_CM_CORE_AON_DSP1_INST 0x040033 #define DRA7XX_CM_CORE_AON_IPU_INST 0x050034 #define DRA7XX_CM_CORE_AON_DSP2_INST 0x060035 #define DRA7XX_CM_CORE_AON_EVE1_INST 0x064036 #define DRA7XX_CM_CORE_AON_EVE2_INST 0x068037 #define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0[all …]
26 #define DRA7XX_PRM_BASE 0x4ae0600033 #define DRA7XX_PRM_OCP_SOCKET_INST 0x000034 #define DRA7XX_PRM_CKGEN_INST 0x010035 #define DRA7XX_PRM_MPU_INST 0x030036 #define DRA7XX_PRM_DSP1_INST 0x040037 #define DRA7XX_PRM_IPU_INST 0x050038 #define DRA7XX_PRM_COREAON_INST 0x062839 #define DRA7XX_PRM_CORE_INST 0x070040 #define DRA7XX_PRM_IVA_INST 0x0f0041 #define DRA7XX_PRM_CAM_INST 0x1000[all …]
11 #define UDA1380_CLK 0x0012 #define UDA1380_IFACE 0x0113 #define UDA1380_PM 0x0214 #define UDA1380_AMIX 0x0315 #define UDA1380_HP 0x0416 #define UDA1380_MVOL 0x1017 #define UDA1380_MIXVOL 0x1118 #define UDA1380_MODE 0x1219 #define UDA1380_DEEMP 0x1320 #define UDA1380_MIXER 0x14[all …]
12 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */13 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */14 #define AC_M_CXR 0x0200 /* shv Context Register */15 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */16 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */17 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */18 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */19 #define AC_M_RESET 0x0700 /* hv Reset Reg */20 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */21 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */[all …]
18 - #clock-cells : from common clock binding; shall be set to 0.31 #clock-cells = <0>;33 reg = <0x021c>, <0x0220>;38 #clock-cells = <0>;44 reg = <0x0500>, <0x0530>, <0x0520>;
22 #define APM_STATE_READY 0x000023 #define APM_STATE_STANDBY 0x000124 #define APM_STATE_SUSPEND 0x000225 #define APM_STATE_OFF 0x000326 #define APM_STATE_BUSY 0x000427 #define APM_STATE_REJECT 0x000528 #define APM_STATE_OEM_SYS 0x002029 #define APM_STATE_OEM_DEV 0x004030 #define APM_STATE_DISABLE 0x000031 #define APM_STATE_ENABLE 0x0001[all …]
35 #define QCA7K_SPI_WRITE (0 << 15)37 #define QCA7K_SPI_EXTERNAL (0 << 14)41 #define QCASPI_HW_BUF_LEN 0xC5B44 #define SPI_REG_BFR_SIZE 0x010045 #define SPI_REG_WRBUF_SPC_AVA 0x020046 #define SPI_REG_RDBUF_BYTE_AVA 0x030047 #define SPI_REG_SPI_CONFIG 0x040048 #define SPI_REG_SPI_STATUS 0x050049 #define SPI_REG_INTR_CAUSE 0x0C0050 #define SPI_REG_INTR_ENABLE 0x0D00[all …]
42 #define ETHERTYPE_PUP 0x020043 #define ETHERTYPE_SPRITE 0x050044 #define ETHERTYPE_IP 0x080045 #define ETHERTYPE_ARP 0x080646 #define ETHERTYPE_REVARP 0x803547 #define ETHERTYPE_AT 0x809B48 #define ETHERTYPE_AARP 0x80F349 #define ETHERTYPE_VLAN 0x810050 #define ETHERTYPE_IPX 0x813751 #define ETHERTYPE_IPV6 0x86dd[all …]