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/kernel/linux/linux-6.6/drivers/clk/samsung/
Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/kernel/linux/linux-6.6/drivers/media/dvb-frontends/
Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/kernel/linux/linux-5.10/arch/sh/include/mach-se/mach/
Dmrshpc.h9 if ((__raw_readw(MRSHPC_CSR) & 0x000c) != 0) in mrshpc_setup_windows()
12 if ((__raw_readw(MRSHPC_CSR) & 0x0080) == 0) { in mrshpc_setup_windows()
13 __raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ in mrshpc_setup_windows()
15 __raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */ in mrshpc_setup_windows()
23 __raw_writew(0x8a84, MRSHPC_MW0CR1); in mrshpc_setup_windows()
24 if((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) in mrshpc_setup_windows()
26 __raw_writew(0x0b00, MRSHPC_MW0CR2); in mrshpc_setup_windows()
28 /* common mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
29 __raw_writew(0x0300, MRSHPC_MW0CR2); in mrshpc_setup_windows()
32 __raw_writew(0x8a85, MRSHPC_MW1CR1); in mrshpc_setup_windows()
[all …]
/kernel/linux/linux-6.6/arch/sh/include/mach-se/mach/
Dmrshpc.h9 if ((__raw_readw(MRSHPC_CSR) & 0x000c) != 0) in mrshpc_setup_windows()
12 if ((__raw_readw(MRSHPC_CSR) & 0x0080) == 0) { in mrshpc_setup_windows()
13 __raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ in mrshpc_setup_windows()
15 __raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */ in mrshpc_setup_windows()
23 __raw_writew(0x8a84, MRSHPC_MW0CR1); in mrshpc_setup_windows()
24 if((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) in mrshpc_setup_windows()
26 __raw_writew(0x0b00, MRSHPC_MW0CR2); in mrshpc_setup_windows()
28 /* common mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
29 __raw_writew(0x0300, MRSHPC_MW0CR2); in mrshpc_setup_windows()
32 __raw_writew(0x8a85, MRSHPC_MW1CR1); in mrshpc_setup_windows()
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Domap3xxx-clocks.dtsi9 #clock-cells = <0>;
15 #clock-cells = <0>;
18 reg = <0x0d40>;
22 #clock-cells = <0>;
27 reg = <0x1270>;
32 #clock-cells = <0>;
35 reg = <0x0d70>;
40 #clock-cells = <0>;
48 #clock-cells = <0>;
56 #clock-cells = <0>;
[all …]
Domap3430es1-clocks.dtsi9 #clock-cells = <0>;
12 reg = <0x0b10>;
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
21 reg = <0x0b40>;
26 #clock-cells = <0>;
34 #clock-cells = <0>;
37 reg = <0x0b00>;
42 #clock-cells = <0>;
45 reg = <0x0b00>;
[all …]
Domap34xx-omap36xx-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
21 reg = <0x0a14>;
25 #clock-cells = <0>;
28 reg = <0x0a14>;
33 #clock-cells = <0>;
36 reg = <0x0a14>;
41 #clock-cells = <0>;
44 reg = <0x0a14>;
45 ti,bit-shift = <0>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ti/
Dgate.txt33 - #clock-cells : from common clock binding; shall be set to 0
47 #clock-cells = <0>;
50 reg = <0x0a00>;
55 #clock-cells = <0>;
58 reg = <0x0a00>;
63 #clock-cells = <0>;
66 reg = <0x0e00>;
67 ti,bit-shift = <0>;
71 #clock-cells = <0>;
74 reg = <0x059c>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/
Dgate.txt33 - #clock-cells : from common clock binding; shall be set to 0
46 #clock-cells = <0>;
49 reg = <0x0a00>;
54 #clock-cells = <0>;
57 reg = <0x0a00>;
62 #clock-cells = <0>;
65 reg = <0x0e00>;
66 ti,bit-shift = <0>;
70 #clock-cells = <0>;
73 reg = <0x059c>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-mtk-tphy.txt5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
23 the child's base address to 0, the physical address
72 reg = <0 0x11290000 0 0x800>;
78 reg = <0 0x11290800 0 0x100>;
85 reg = <0 0x11290800 0 0x700>;
92 reg = <0 0x11291000 0 0x100>;
113 phy-names = "usb2-0", "usb3-0";
122 shared 0x0000 SPLLC
123 0x0100 FMREG
124 u2 port0 0x0800 U2PHY_COM
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
Dprcm_mpu7xx.h24 #define DRA7XX_PRCM_MPU_BASE 0x48243000
30 #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
31 #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
32 #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
33 #define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
34 #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
35 #define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
38 #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
39 #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
45 #define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
Dprcm_mpu54xx.h24 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
30 #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
31 #define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
32 #define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
33 #define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
34 #define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
35 #define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
38 #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
39 #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
52 #define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
Dcm33xx.h17 #define AM33XX_CM_BASE 0x44e00000
23 #define AM33XX_CM_PER_MOD 0x0000
24 #define AM33XX_CM_WKUP_MOD 0x0400
25 #define AM33XX_CM_DPLL_MOD 0x0500
26 #define AM33XX_CM_MPU_MOD 0x0600
27 #define AM33XX_CM_DEVICE_MOD 0x0700
28 #define AM33XX_CM_RTC_MOD 0x0800
29 #define AM33XX_CM_GFX_MOD 0x0900
30 #define AM33XX_CM_CEFUSE_MOD 0x0A00
33 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/netronome/nfp/nfpcore/
Dnfp_dev.c13 .qc_idx_mask = GENMASK(8, 0),
14 .qc_addr_offset = 0x400000,
19 .pcie_cfg_expbar_offset = 0x0a00,
20 .pcie_expl_offset = 0xd000,
21 .qc_area_sz = 0x100000,
25 .qc_idx_mask = GENMASK(8, 0),
26 .qc_addr_offset = 0,
32 .qc_idx_mask = GENMASK(7, 0),
33 .qc_addr_offset = 0x80000,
38 .pcie_cfg_expbar_offset = 0x0400,
[all …]
/kernel/linux/linux-6.6/drivers/net/phy/
Dmdio-open-alliance.h14 #define MDIO_OATC14_PLCA_IDVER 0xca00 /* PLCA ID and version */
15 #define MDIO_OATC14_PLCA_CTRL0 0xca01 /* PLCA Control register 0 */
16 #define MDIO_OATC14_PLCA_CTRL1 0xca02 /* PLCA Control register 1 */
17 #define MDIO_OATC14_PLCA_STATUS 0xca03 /* PLCA Status register */
18 #define MDIO_OATC14_PLCA_TOTMR 0xca04 /* PLCA TO Timer register */
19 #define MDIO_OATC14_PLCA_BURST 0xca05 /* PLCA BURST mode register */
22 #define MDIO_OATC14_PLCA_IDM 0xff00 /* PLCA MAP ID */
23 #define MDIO_OATC14_PLCA_VER 0x00ff /* PLCA MAP version */
30 #define MDIO_OATC14_PLCA_NCNT 0xff00 /* PLCA node count */
31 #define MDIO_OATC14_PLCA_ID 0x00ff /* PLCA local node ID */
[all …]
/kernel/linux/linux-6.6/drivers/net/dsa/mv88e6xxx/
Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
/kernel/linux/patches/linux-5.10/prebuilts/usr/include/linux/
Dmdio.h67 #define MDIO_PMA_LASI_RXCTRL 0x9000
68 #define MDIO_PMA_LASI_TXCTRL 0x9001
69 #define MDIO_PMA_LASI_CTRL 0x9002
70 #define MDIO_PMA_LASI_RXSTAT 0x9003
71 #define MDIO_PMA_LASI_TXSTAT 0x9004
72 #define MDIO_PMA_LASI_STAT 0x9005
74 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
78 #define MDIO_PMA_CTRL1_LOOPBACK 0x0001
85 #define MDIO_AN_CTRL1_XNP 0x2000
86 #define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400
[all …]
/kernel/linux/patches/linux-6.6/prebuilts/usr/include/linux/
Dmdio.h67 #define MDIO_PMA_LASI_RXCTRL 0x9000
68 #define MDIO_PMA_LASI_TXCTRL 0x9001
69 #define MDIO_PMA_LASI_CTRL 0x9002
70 #define MDIO_PMA_LASI_RXSTAT 0x9003
71 #define MDIO_PMA_LASI_TXSTAT 0x9004
72 #define MDIO_PMA_LASI_STAT 0x9005
74 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
78 #define MDIO_PMA_CTRL1_LOOPBACK 0x0001
85 #define MDIO_AN_CTRL1_XNP 0x2000
86 #define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dprcm_mpu7xx.h24 #define DRA7XX_PRCM_MPU_BASE 0x48243000
30 #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
31 #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
32 #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
33 #define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
34 #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
35 #define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
38 #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
39 #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
45 #define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
Dprcm_mpu54xx.h24 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
30 #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
31 #define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
32 #define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
33 #define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
34 #define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
35 #define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
38 #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
39 #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
52 #define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
Dif_ether.h17 #define ETH_MAX_MTU 0xFFFFU
18 #define ETH_P_LOOP 0x0060
19 #define ETH_P_PUP 0x0200
20 #define ETH_P_PUPAT 0x0201
21 #define ETH_P_TSN 0x22F0
22 #define ETH_P_ERSPAN2 0x22EB
23 #define ETH_P_IP 0x0800
24 #define ETH_P_X25 0x0805
25 #define ETH_P_ARP 0x0806
26 #define ETH_P_BPQ 0x08FF
[all …]

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