| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | mdio-mux-gpio.txt | 18 #size-cells = <0>;
19 reg = <0x11800 0x00001900 0x0 0x40>;
29 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
32 #size-cells = <0>;
37 #size-cells = <0>;
41 marvell,reg-init = <3 0x10 0 0x5777>,
42 <3 0x11 0 0x00aa>,
43 <3 0x12 0 0x4105>,
44 <3 0x13 0 0x0a60>;
50 marvell,reg-init = <3 0x10 0 0x5777>,
[all …]
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| D | mdio-mux.txt | 9 - #size-cells = <0>;
18 - #size-cells = <0>;
28 #size-cells = <0>;
29 reg = <0x11800 0x00001900 0x0 0x40>;
39 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
42 #size-cells = <0>;
47 #size-cells = <0>;
51 marvell,reg-init = <3 0x10 0 0x5777>,
52 <3 0x11 0 0x00aa>,
53 <3 0x12 0 0x4105>,
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | mdio-mux-gpio.yaml | 44 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
47 #size-cells = <0>;
52 #size-cells = <0>;
56 marvell,reg-init = <3 0x10 0 0x5777>,
57 <3 0x11 0 0x00aa>,
58 <3 0x12 0 0x4105>,
59 <3 0x13 0 0x0a60>;
65 marvell,reg-init = <3 0x10 0 0x5777>,
66 <3 0x11 0 0x00aa>,
67 <3 0x12 0 0x4105>,
[all …]
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/cavium-octeon/ |
| D | octeon_3xxx.dts | 13 soc@0 {
15 phy0: ethernet-phy@0 {
19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
24 reg = <0>;
31 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
35 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
42 marvell,reg-init = <3 0x10 0 0x5777>,
[all …]
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| D | octeon_68xx.dts | 16 soc@0 {
26 * 1) Controller register (0 or 7)
27 * 2) Bit within the register (0..63)
29 #address-cells = <0>;
31 reg = <0x10701 0x00000000 0x0 0x4000000>;
37 reg = <0x10700 0x00000800 0x0 0x100>;
40 * 1) GPIO pin number (0..15)
49 interrupts = <7 0>, <7 1>, <7 2>, <7 3>,
58 #size-cells = <0>;
59 reg = <0x11800 0x00003800 0x0 0x40>;
[all …]
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| /kernel/linux/linux-6.6/arch/mips/boot/dts/cavium-octeon/ |
| D | octeon_3xxx.dts | 13 soc@0 {
15 phy0: ethernet-phy@0 {
19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
24 reg = <0>;
31 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
35 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
42 marvell,reg-init = <3 0x10 0 0x5777>,
[all …]
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| D | octeon_68xx.dts | 16 soc@0 {
26 * 1) Controller register (0 or 7)
27 * 2) Bit within the register (0..63)
29 #address-cells = <0>;
31 reg = <0x10701 0x00000000 0x0 0x4000000>;
37 reg = <0x10700 0x00000800 0x0 0x100>;
40 * 1) GPIO pin number (0..15)
49 interrupts = <7 0>, <7 1>, <7 2>, <7 3>,
58 #size-cells = <0>;
59 reg = <0x11800 0x00003800 0x0 0x40>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | cm2_54xx.h | 22 #define OMAP54XX_CM_CORE_BASE 0x4a008000
28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600
31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700
32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200
33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300
34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400
35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500
36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
[all …]
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| D | prm54xx.h | 24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/vce/ |
| D | vce_4_0_offset.h | 27 // base address: 0x22000
28 …VCE_STATUS 0x0a01
29 …ne mmVCE_STATUS_BASE_IDX 0
30 …VCE_VCPU_CNTL 0x0a05
31 …ne mmVCE_VCPU_CNTL_BASE_IDX 0
32 …VCE_VCPU_CACHE_OFFSET0 0x0a09
33 …ne mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0
34 …VCE_VCPU_CACHE_SIZE0 0x0a0a
35 …ne mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0
36 …VCE_VCPU_CACHE_OFFSET1 0x0a0b
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/vce/ |
| D | vce_4_0_offset.h | 27 // base address: 0x22000
28 …VCE_STATUS 0x0a01
29 …ne mmVCE_STATUS_BASE_IDX 0
30 …VCE_VCPU_CNTL 0x0a05
31 …ne mmVCE_VCPU_CNTL_BASE_IDX 0
32 …VCE_VCPU_CACHE_OFFSET0 0x0a09
33 …ne mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0
34 …VCE_VCPU_CACHE_SIZE0 0x0a0a
35 …ne mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0
36 …VCE_VCPU_CACHE_OFFSET1 0x0a0b
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/st/sti/bdisp/ |
| D | bdisp-reg.h | 8 /* 0 - General */
87 #define BLT_CTL 0x0A00
88 #define BLT_ITS 0x0A04
89 #define BLT_STA1 0x0A08
90 #define BLT_AQ1_CTL 0x0A60
91 #define BLT_AQ1_IP 0x0A64
92 #define BLT_AQ1_LNA 0x0A68
93 #define BLT_AQ1_STA 0x0A6C
94 #define BLT_ITM0 0x0AD0
96 #define BLT_PLUGS1_OP2 0x0B04
[all …]
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| /kernel/linux/linux-5.10/drivers/media/platform/sti/bdisp/ |
| D | bdisp-reg.h | 8 /* 0 - General */
87 #define BLT_CTL 0x0A00
88 #define BLT_ITS 0x0A04
89 #define BLT_STA1 0x0A08
90 #define BLT_AQ1_CTL 0x0A60
91 #define BLT_AQ1_IP 0x0A64
92 #define BLT_AQ1_LNA 0x0A68
93 #define BLT_AQ1_STA 0x0A6C
94 #define BLT_ITM0 0x0AD0
96 #define BLT_PLUGS1_OP2 0x0B04
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/ |
| D | rtw8723d.h | 20 IQK_ROUND_INVALID = 0xff,
37 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
53 u8 channel_plan; /* 0xb8 */
57 u8 pa_type; /* 0xbc */
58 u8 lna_type_2g[2]; /* 0xbd */
68 u8 rf_antenna_option; /* 0xc9 */
77 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
81 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
83 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
85 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
[all …]
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| /kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw88/ |
| D | rtw8723d.h | 20 IQK_ROUND_INVALID = 0xff,
37 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
45 u8 res4[48]; /* 0xd0 */
46 u8 vender_id[2]; /* 0x100 */
47 u8 product_id[2]; /* 0x102 */
48 u8 usb_option; /* 0x104 */
49 u8 res5[2]; /* 0x105 */
50 u8 mac_addr[ETH_ALEN]; /* 0x107 */
54 u8 res4[0x4a]; /* 0xd0 */
55 u8 mac_addr[ETH_ALEN]; /* 0x11a */
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_scl_filters.c | 31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_scl_filters.c | 31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
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| /kernel/linux/linux-6.6/drivers/media/i2c/ccs/ |
| D | smiapp-reg-defs.h | 16 #define SMIAPP_REG_U16_MODEL_ID (0x0000 | CCS_FL_16BIT)
17 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR 0x0002
18 #define SMIAPP_REG_U8_MANUFACTURER_ID 0x0003
19 #define SMIAPP_REG_U8_SMIA_VERSION 0x0004
20 #define SMIAPP_REG_U8_FRAME_COUNT 0x0005
21 #define SMIAPP_REG_U8_PIXEL_ORDER 0x0006
22 #define SMIAPP_REG_U16_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT)
23 #define SMIAPP_REG_U8_PIXEL_DEPTH 0x000c
24 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR 0x0010
25 #define SMIAPP_REG_U8_SMIAPP_VERSION 0x0011
[all …]
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| /kernel/linux/linux-5.10/drivers/media/i2c/smiapp/ |
| D | smiapp-reg-defs.h | 16 #define SMIAPP_REG_U16_MODEL_ID SMIAPP_REG_MK_U16(0x0000)
17 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR SMIAPP_REG_MK_U8(0x0002)
18 #define SMIAPP_REG_U8_MANUFACTURER_ID SMIAPP_REG_MK_U8(0x0003)
19 #define SMIAPP_REG_U8_SMIA_VERSION SMIAPP_REG_MK_U8(0x0004)
20 #define SMIAPP_REG_U8_FRAME_COUNT SMIAPP_REG_MK_U8(0x0005)
21 #define SMIAPP_REG_U8_PIXEL_ORDER SMIAPP_REG_MK_U8(0x0006)
22 #define SMIAPP_REG_U16_DATA_PEDESTAL SMIAPP_REG_MK_U16(0x0008)
23 #define SMIAPP_REG_U8_PIXEL_DEPTH SMIAPP_REG_MK_U8(0x000c)
24 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR SMIAPP_REG_MK_U8(0x0010)
25 #define SMIAPP_REG_U8_SMIAPP_VERSION SMIAPP_REG_MK_U8(0x0011)
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | imx8ulp-pinfunc.h | 13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/microchip/ |
| D | lan743x_main.h | 15 #define ID_REV (0x00)
16 #define ID_REV_ID_MASK_ (0xFFFF0000)
17 #define ID_REV_ID_LAN7430_ (0x74300000)
18 #define ID_REV_ID_LAN7431_ (0x74310000)
20 (((id_rev) & 0xFFF00000) == 0x74300000)
21 #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
22 #define ID_REV_CHIP_REV_A0_ (0x00000000)
23 #define ID_REV_CHIP_REV_B0_ (0x00000010)
25 #define FPGA_REV (0x04)
26 #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_6_0_d.h | 26 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0x00CE
27 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0x00DE
28 #define ixMC_IO_DEBUG_ACMD_MISC_D0 0x00AE
29 #define ixMC_IO_DEBUG_ACMD_MISC_D1 0x00BE
30 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0x00EE
31 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0x00FE
32 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x010E
33 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x011E
34 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x018E
35 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x019E
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_6_0_d.h | 26 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0x00CE
27 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0x00DE
28 #define ixMC_IO_DEBUG_ACMD_MISC_D0 0x00AE
29 #define ixMC_IO_DEBUG_ACMD_MISC_D1 0x00BE
30 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0x00EE
31 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0x00FE
32 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x010E
33 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x011E
34 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x018E
35 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x019E
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/microchip/ |
| D | lan743x_main.h | 15 #define ID_REV (0x00)
16 #define ID_REV_ID_MASK_ (0xFFFF0000)
17 #define ID_REV_ID_LAN7430_ (0x74300000)
18 #define ID_REV_ID_LAN7431_ (0x74310000)
19 #define ID_REV_ID_LAN743X_ (0x74300000)
20 #define ID_REV_ID_A011_ (0xA0110000) // PCI11010
21 #define ID_REV_ID_A041_ (0xA0410000) // PCI11414
22 #define ID_REV_ID_A0X1_ (0xA0010000)
24 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \
25 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/sibyte/ |
| D | sb1250_regs.h | 46 * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
51 #define A_MC_BASE_0 0x0010051000
52 #define A_MC_BASE_1 0x0010052000
53 #define MC_REGISTER_SPACING 0x1000
58 #define R_MC_CONFIG 0x0000000100
59 #define R_MC_DRAMCMD 0x0000000120
60 #define R_MC_DRAMMODE 0x0000000140
61 #define R_MC_TIMING1 0x0000000160
62 #define R_MC_TIMING2 0x0000000180
63 #define R_MC_CS_START 0x00000001A0
[all …]
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