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/kernel/linux/linux-6.6/drivers/clk/samsung/
Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
Dclk-exynos5433.c50 #define ISP_PLL_LOCK 0x0000
51 #define AUD_PLL_LOCK 0x0004
52 #define ISP_PLL_CON0 0x0100
53 #define ISP_PLL_CON1 0x0104
54 #define ISP_PLL_FREQ_DET 0x0108
55 #define AUD_PLL_CON0 0x0110
56 #define AUD_PLL_CON1 0x0114
57 #define AUD_PLL_CON2 0x0118
58 #define AUD_PLL_FREQ_DET 0x011c
59 #define MUX_SEL_TOP0 0x0200
[all …]
/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
Dclk-exynos5433.c27 #define ISP_PLL_LOCK 0x0000
28 #define AUD_PLL_LOCK 0x0004
29 #define ISP_PLL_CON0 0x0100
30 #define ISP_PLL_CON1 0x0104
31 #define ISP_PLL_FREQ_DET 0x0108
32 #define AUD_PLL_CON0 0x0110
33 #define AUD_PLL_CON1 0x0114
34 #define AUD_PLL_CON2 0x0118
35 #define AUD_PLL_FREQ_DET 0x011c
36 #define MUX_SEL_TOP0 0x0200
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-mtk-tphy.txt5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
23 the child's base address to 0, the physical address
72 reg = <0 0x11290000 0 0x800>;
78 reg = <0 0x11290800 0 0x100>;
85 reg = <0 0x11290800 0 0x700>;
92 reg = <0 0x11291000 0 0x100>;
113 phy-names = "usb2-0", "usb3-0";
122 shared 0x0000 SPLLC
123 0x0100 FMREG
124 u2 port0 0x0800 U2PHY_COM
[all …]
/kernel/linux/linux-6.6/drivers/media/i2c/
Dhi556.c23 #define HI556_REG_CHIP_ID 0x0f16
24 #define HI556_CHIP_ID 0x0556
26 #define HI556_REG_MODE_SELECT 0x0a00
27 #define HI556_MODE_STANDBY 0x0000
28 #define HI556_MODE_STREAMING 0x0100
31 #define HI556_REG_FLL 0x0006
32 #define HI556_FLL_30FPS 0x0814
33 #define HI556_FLL_30FPS_MIN 0x0814
34 #define HI556_FLL_MAX 0x7fff
37 #define HI556_REG_LLP 0x0008
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Domap3430es1-clocks.dtsi9 #clock-cells = <0>;
12 reg = <0x0b10>;
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
21 reg = <0x0b40>;
26 #clock-cells = <0>;
34 #clock-cells = <0>;
37 reg = <0x0b00>;
42 #clock-cells = <0>;
45 reg = <0x0b00>;
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
Dprm33xx.h14 #define AM33XX_PRM_BASE 0x44E00000
21 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
22 #define AM33XX_PRM_PER_MOD 0x0C00
23 #define AM33XX_PRM_WKUP_MOD 0x0D00
24 #define AM33XX_PRM_MPU_MOD 0x0E00
25 #define AM33XX_PRM_DEVICE_MOD 0x0F00
26 #define AM33XX_PRM_RTC_MOD 0x1000
27 #define AM33XX_PRM_GFX_MOD 0x1100
28 #define AM33XX_PRM_CEFUSE_MOD 0x1200
31 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Domap3430es1-clocks.dtsi9 #clock-cells = <0>;
12 reg = <0x0b10>;
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
21 reg = <0x0b40>;
26 #clock-cells = <0>;
34 #clock-cells = <0>;
37 reg = <0x0b00>;
42 #clock-cells = <0>;
45 reg = <0x0b00>;
[all …]
/kernel/linux/linux-5.10/drivers/media/i2c/
Dhi556.c23 #define HI556_REG_CHIP_ID 0x0f16
24 #define HI556_CHIP_ID 0x0556
26 #define HI556_REG_MODE_SELECT 0x0a00
27 #define HI556_MODE_STANDBY 0x0000
28 #define HI556_MODE_STREAMING 0x0100
31 #define HI556_REG_FLL 0x0006
32 #define HI556_FLL_30FPS 0x0814
33 #define HI556_FLL_30FPS_MIN 0x0814
34 #define HI556_FLL_MAX 0x7fff
37 #define HI556_REG_LLP 0x0008
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_reg.c30 {NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
31 {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
32 {0x1200, 0x12E0} } },
33 {NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
34 {0x1610, 0x1618}, {0x1700, 0x17C8} } },
35 {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } },
36 {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
45 if (reg & 0x07) in rvu_check_valid_reg()
62 for (idx = 0; idx < map->num_ranges; idx++) { in rvu_check_valid_reg()
/kernel/linux/linux-5.10/arch/sh/include/mach-se/mach/
Dmrshpc.h9 if ((__raw_readw(MRSHPC_CSR) & 0x000c) != 0) in mrshpc_setup_windows()
12 if ((__raw_readw(MRSHPC_CSR) & 0x0080) == 0) { in mrshpc_setup_windows()
13 __raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ in mrshpc_setup_windows()
15 __raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */ in mrshpc_setup_windows()
23 __raw_writew(0x8a84, MRSHPC_MW0CR1); in mrshpc_setup_windows()
24 if((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) in mrshpc_setup_windows()
26 __raw_writew(0x0b00, MRSHPC_MW0CR2); in mrshpc_setup_windows()
28 /* common mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
29 __raw_writew(0x0300, MRSHPC_MW0CR2); in mrshpc_setup_windows()
32 __raw_writew(0x8a85, MRSHPC_MW1CR1); in mrshpc_setup_windows()
[all …]
/kernel/linux/linux-6.6/arch/sh/include/mach-se/mach/
Dmrshpc.h9 if ((__raw_readw(MRSHPC_CSR) & 0x000c) != 0) in mrshpc_setup_windows()
12 if ((__raw_readw(MRSHPC_CSR) & 0x0080) == 0) { in mrshpc_setup_windows()
13 __raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ in mrshpc_setup_windows()
15 __raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */ in mrshpc_setup_windows()
23 __raw_writew(0x8a84, MRSHPC_MW0CR1); in mrshpc_setup_windows()
24 if((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) in mrshpc_setup_windows()
26 __raw_writew(0x0b00, MRSHPC_MW0CR2); in mrshpc_setup_windows()
28 /* common mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
29 __raw_writew(0x0300, MRSHPC_MW0CR2); in mrshpc_setup_windows()
32 __raw_writew(0x8a85, MRSHPC_MW1CR1); in mrshpc_setup_windows()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_reg.c33 {NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
34 {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
35 {0x1200, 0x12E0} } },
36 {NIX_TXSCH_LVL_TL3, 3, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
37 {0x1610, 0x1618} } },
38 {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x1768} } },
39 {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
48 if (reg & 0x07) in rvu_check_valid_reg()
65 for (idx = 0; idx < map->num_ranges; idx++) { in rvu_check_valid_reg()
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dcavium-mdio.txt15 - #size-cells: Must be <0>. MDIO addresses have no size component.
23 #size-cells = <0>;
24 reg = <0x11800 0x00001800 0x0 0x40>;
26 ethernet-phy@0 {
28 reg = <0>;
58 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
59 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
60 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
65 #size-cells = <0>;
66 reg = <0x87e0 0x05003800 0x0 0x30>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dcavium-mdio.txt15 - #size-cells: Must be <0>. MDIO addresses have no size component.
23 #size-cells = <0>;
24 reg = <0x11800 0x00001800 0x0 0x40>;
26 ethernet-phy@0 {
28 reg = <0>;
58 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
59 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
60 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
65 #size-cells = <0>;
66 reg = <0x87e0 0x05003800 0x0 0x30>;
[all …]
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
Din6.h55 #define IPV6_FL_A_GET 0
62 #define IPV6_FL_S_NONE 0
67 #define IPV6_FLOWINFO_FLOWLABEL 0x000fffff
68 #define IPV6_FLOWINFO_PRIORITY 0x0ff00000
69 #define IPV6_PRIORITY_UNCHARACTERIZED 0x0000
70 #define IPV6_PRIORITY_FILLER 0x0100
71 #define IPV6_PRIORITY_UNATTENDED 0x0200
72 #define IPV6_PRIORITY_RESERVED1 0x0300
73 #define IPV6_PRIORITY_BULK 0x0400
74 #define IPV6_PRIORITY_RESERVED2 0x0500
[all …]
/kernel/linux/linux-6.6/arch/m68k/include/asm/
Dmcfpit.h18 #define MCFPIT_PCSR 0x0 /* PIT control register */
19 #define MCFPIT_PMR 0x2 /* PIT modulus register */
20 #define MCFPIT_PCNTR 0x4 /* PIT count register */
25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
[all …]
/kernel/linux/linux-5.10/arch/m68k/include/asm/
Dmcfpit.h18 #define MCFPIT_PCSR 0x0 /* PIT control register */
19 #define MCFPIT_PMR 0x2 /* PIT modulus register */
20 #define MCFPIT_PCNTR 0x4 /* PIT count register */
25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dprcm43xx.h18 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
19 #define AM43XX_PRM_MPU_INST 0x0300
20 #define AM43XX_PRM_GFX_INST 0x0400
21 #define AM43XX_PRM_RTC_INST 0x0500
22 #define AM43XX_PRM_TAMPER_INST 0x0600
23 #define AM43XX_PRM_CEFUSE_INST 0x0700
24 #define AM43XX_PRM_PER_INST 0x0800
25 #define AM43XX_PRM_WKUP_INST 0x2000
26 #define AM43XX_PRM_DEVICE_INST 0x4000
29 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
Dprm33xx.h22 #define AM33XX_PRM_BASE 0x44E00000
29 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
30 #define AM33XX_PRM_PER_MOD 0x0C00
31 #define AM33XX_PRM_WKUP_MOD 0x0D00
32 #define AM33XX_PRM_MPU_MOD 0x0E00
33 #define AM33XX_PRM_DEVICE_MOD 0x0F00
34 #define AM33XX_PRM_RTC_MOD 0x1000
35 #define AM33XX_PRM_GFX_MOD 0x1100
36 #define AM33XX_PRM_CEFUSE_MOD 0x1200
41 #define AM33XX_REVISION_PRM_OFFSET 0x0000
[all …]
/kernel/linux/linux-6.6/drivers/gpio/
Dgpio-mxs.c22 #define MXS_SET 0x4
23 #define MXS_CLR 0x8
25 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
26 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
27 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
28 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
29 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
30 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
31 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
32 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
[all …]
/kernel/linux/linux-5.10/drivers/gpio/
Dgpio-mxs.c23 #define MXS_SET 0x4
24 #define MXS_CLR 0x8
26 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
27 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
28 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
29 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
30 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
31 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
32 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
33 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
[all …]

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