| /kernel/linux/linux-6.6/drivers/net/dsa/microchip/ |
| D | ksz_ptp_reg.h | 9 #define REG_SW_GLOBAL_LED_OVR__4 0x0120
11 #define LED_OVR_1 BIT(0)
13 #define REG_SW_GLOBAL_LED_SRC__4 0x0128
18 #define REG_PTP_CLK_CTRL 0x0500
26 #define PTP_CLK_RESET BIT(0)
28 #define REG_PTP_RTC_SUB_NANOSEC__2 0x0502
30 #define PTP_RTC_SUB_NANOSEC_M 0x0007
31 #define PTP_RTC_0NS 0x00
33 #define REG_PTP_RTC_NANOSEC 0x0504
35 #define REG_PTP_RTC_SEC 0x0508
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| D | ksz9477_reg.h | 11 #define KS_PRIO_M 0x7
14 /* 0 - Operation */
15 #define REG_CHIP_ID0__1 0x0000
17 #define REG_CHIP_ID1__1 0x0001
19 #define FAMILY_ID 0x95
20 #define FAMILY_ID_94 0x94
21 #define FAMILY_ID_95 0x95
22 #define FAMILY_ID_85 0x85
23 #define FAMILY_ID_98 0x98
24 #define FAMILY_ID_88 0x88
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| /kernel/linux/linux-6.6/include/linux/bcma/ |
| D | bcma_driver_pcie2.h | 5 #define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
6 #define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
7 #define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
8 #define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
9 #define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
10 #define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
11 #define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
12 #define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
13 #define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
14 #define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
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| /kernel/linux/linux-5.10/include/linux/bcma/ |
| D | bcma_driver_pcie2.h | 5 #define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
6 #define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
7 #define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
8 #define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
9 #define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
10 #define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
11 #define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
12 #define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
13 #define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
14 #define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
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| /kernel/linux/linux-5.10/include/linux/ssb/ |
| D | ssb_driver_gige.h | 14 #define SSB_GIGE_PCIIO 0x0000 /* PCI I/O Registers (1024 bytes) */
15 #define SSB_GIGE_RESERVED 0x0400 /* Reserved (1024 bytes) */
16 #define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
17 #define SSB_GIGE_SHIM_FLUSHSTAT 0x0C00 /* PCI to OCP: Flush status control (32bit) */
18 #define SSB_GIGE_SHIM_FLUSHRDA 0x0C04 /* PCI to OCP: Flush read address (32bit) */
19 #define SSB_GIGE_SHIM_FLUSHTO 0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
20 #define SSB_GIGE_SHIM_BARRIER 0x0C0C /* PCI to OCP: Barrier register (32bit) */
21 #define SSB_GIGE_SHIM_MAOCPSI 0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
22 #define SSB_GIGE_SHIM_SIOCPMA 0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
25 #define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
[all …]
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| /kernel/linux/linux-6.6/include/linux/ssb/ |
| D | ssb_driver_gige.h | 14 #define SSB_GIGE_PCIIO 0x0000 /* PCI I/O Registers (1024 bytes) */
15 #define SSB_GIGE_RESERVED 0x0400 /* Reserved (1024 bytes) */
16 #define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
17 #define SSB_GIGE_SHIM_FLUSHSTAT 0x0C00 /* PCI to OCP: Flush status control (32bit) */
18 #define SSB_GIGE_SHIM_FLUSHRDA 0x0C04 /* PCI to OCP: Flush read address (32bit) */
19 #define SSB_GIGE_SHIM_FLUSHTO 0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
20 #define SSB_GIGE_SHIM_BARRIER 0x0C0C /* PCI to OCP: Barrier register (32bit) */
21 #define SSB_GIGE_SHIM_MAOCPSI 0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
22 #define SSB_GIGE_SHIM_SIOCPMA 0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
25 #define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_1_0_d.h | 26 #define ixCLIENT0_BM 0x0220
27 #define ixCLIENT0_CD0 0x0210
28 #define ixCLIENT0_CD1 0x0214
29 #define ixCLIENT0_CD2 0x0218
30 #define ixCLIENT0_CD3 0x021C
31 #define ixCLIENT0_CK0 0x0200
32 #define ixCLIENT0_CK1 0x0204
33 #define ixCLIENT0_CK2 0x0208
34 #define ixCLIENT0_CK3 0x020C
35 #define ixCLIENT0_K0 0x01F0
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_1_0_d.h | 26 #define ixCLIENT0_BM 0x0220
27 #define ixCLIENT0_CD0 0x0210
28 #define ixCLIENT0_CD1 0x0214
29 #define ixCLIENT0_CD2 0x0218
30 #define ixCLIENT0_CD3 0x021C
31 #define ixCLIENT0_CK0 0x0200
32 #define ixCLIENT0_CK1 0x0204
33 #define ixCLIENT0_CK2 0x0208
34 #define ixCLIENT0_CK3 0x020C
35 #define ixCLIENT0_K0 0x01F0
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/ |
| D | qcom,sdm845-camss.yaml | 96 port@0:
321 iommus = <&apps_smmu 0x0808 0x0>,
322 <&apps_smmu 0x0810 0x8>,
323 <&apps_smmu 0x0c08 0x0>,
324 <&apps_smmu 0x0c10 0x8>;
330 reg = <0 0xacb3000 0 0x1000>,
331 <0 0xacba000 0 0x1000>,
332 <0 0xacc8000 0 0x1000>,
333 <0 0xac65000 0 0x1000>,
334 <0 0xac66000 0 0x1000>,
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/st/sti/bdisp/ |
| D | bdisp-reg.h | 8 /* 0 - General */
87 #define BLT_CTL 0x0A00
88 #define BLT_ITS 0x0A04
89 #define BLT_STA1 0x0A08
90 #define BLT_AQ1_CTL 0x0A60
91 #define BLT_AQ1_IP 0x0A64
92 #define BLT_AQ1_LNA 0x0A68
93 #define BLT_AQ1_STA 0x0A6C
94 #define BLT_ITM0 0x0AD0
96 #define BLT_PLUGS1_OP2 0x0B04
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| /kernel/linux/linux-5.10/drivers/media/platform/sti/bdisp/ |
| D | bdisp-reg.h | 8 /* 0 - General */
87 #define BLT_CTL 0x0A00
88 #define BLT_ITS 0x0A04
89 #define BLT_STA1 0x0A08
90 #define BLT_AQ1_CTL 0x0A60
91 #define BLT_AQ1_IP 0x0A64
92 #define BLT_AQ1_LNA 0x0A68
93 #define BLT_AQ1_STA 0x0A6C
94 #define BLT_ITM0 0x0AD0
96 #define BLT_PLUGS1_OP2 0x0B04
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/ |
| D | rtw8723d.h | 20 IQK_ROUND_INVALID = 0xff,
37 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
53 u8 channel_plan; /* 0xb8 */
57 u8 pa_type; /* 0xbc */
58 u8 lna_type_2g[2]; /* 0xbd */
68 u8 rf_antenna_option; /* 0xc9 */
77 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
81 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
83 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
85 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/include/asm/ |
| D | cell-regs.h | 28 #define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul
29 #define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul
30 #define HID0_CBE_THERM_INT_EN 0x0000000400000000ul
31 #define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul
57 u64 pad_0x0000; /* 0x0000 */
59 u64 group_control; /* 0x0008 */
61 u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
63 u64 debug_bus_control; /* 0x00a8 */
65 u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
67 u64 trace_aux_data; /* 0x0100 */
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/include/asm/ |
| D | cell-regs.h | 28 #define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul
29 #define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul
30 #define HID0_CBE_THERM_INT_EN 0x0000000400000000ul
31 #define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul
57 u64 pad_0x0000; /* 0x0000 */
59 u64 group_control; /* 0x0008 */
61 u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
63 u64 debug_bus_control; /* 0x00a8 */
65 u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
67 u64 trace_aux_data; /* 0x0100 */
[all …]
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| /kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw88/ |
| D | rtw8723d.h | 20 IQK_ROUND_INVALID = 0xff,
37 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
45 u8 res4[48]; /* 0xd0 */
46 u8 vender_id[2]; /* 0x100 */
47 u8 product_id[2]; /* 0x102 */
48 u8 usb_option; /* 0x104 */
49 u8 res5[2]; /* 0x105 */
50 u8 mac_addr[ETH_ALEN]; /* 0x107 */
54 u8 res4[0x4a]; /* 0xd0 */
55 u8 mac_addr[ETH_ALEN]; /* 0x11a */
[all …]
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| /kernel/linux/linux-5.10/drivers/media/i2c/s5c73m3/ |
| D | s5c73m3.h | 44 #define AHB_MSB_ADDR_PTR 0xfcfc
45 #define REG_CMDWR_ADDRH 0x0050
46 #define REG_CMDWR_ADDRL 0x0054
47 #define REG_CMDRD_ADDRH 0x0058
48 #define REG_CMDRD_ADDRL 0x005c
49 #define REG_CMDBUF_ADDR 0x0f14
51 #define REG_I2C_SEQ_STATUS S5C73M3_REG(0x0009, 0x59A6)
52 #define SEQ_END_PLL (1<<0x0)
53 #define SEQ_END_SENSOR (1<<0x1)
54 #define SEQ_END_GPIO (1<<0x2)
[all …]
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| /kernel/linux/linux-6.6/drivers/media/i2c/s5c73m3/ |
| D | s5c73m3.h | 44 #define AHB_MSB_ADDR_PTR 0xfcfc
45 #define REG_CMDWR_ADDRH 0x0050
46 #define REG_CMDWR_ADDRL 0x0054
47 #define REG_CMDRD_ADDRH 0x0058
48 #define REG_CMDRD_ADDRL 0x005c
49 #define REG_CMDBUF_ADDR 0x0f14
51 #define REG_I2C_SEQ_STATUS S5C73M3_REG(0x0009, 0x59A6)
52 #define SEQ_END_PLL (1<<0x0)
53 #define SEQ_END_SENSOR (1<<0x1)
54 #define SEQ_END_GPIO (1<<0x2)
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| /kernel/linux/linux-6.6/drivers/iommu/ |
| D | fsl_pamu.h | 22 #define PAMU_PGC 0x00000000 /* Allows all peripheral accesses */
23 #define PAMU_PE 0x40000000 /* enable PAMU */
26 #define PAMU_OFFSET 0x1000
28 #define PAMU_MMAP_REGS_BASE 0
46 #define PAMU_POES1 0x0040
47 #define PAMU_POES2 0x0044
48 #define PAMU_POEAH 0x0048
49 #define PAMU_POEAL 0x004C
50 #define PAMU_AVS1 0x0050
51 #define PAMU_AVS1_AV 0x1
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| /kernel/linux/linux-5.10/drivers/iommu/ |
| D | fsl_pamu.h | 22 #define PAMU_PGC 0x00000000 /* Allows all peripheral accesses */
23 #define PAMU_PE 0x40000000 /* enable PAMU */
26 #define PAMU_OFFSET 0x1000
28 #define PAMU_MMAP_REGS_BASE 0
46 #define PAMU_POES1 0x0040
47 #define PAMU_POES2 0x0044
48 #define PAMU_POEAH 0x0048
49 #define PAMU_POEAL 0x004C
50 #define PAMU_AVS1 0x0050
51 #define PAMU_AVS1_AV 0x1
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| /kernel/linux/linux-5.10/drivers/video/fbdev/kyro/ |
| D | STG4000Reg.h | 54 NO_LUT = 0, RESERVED, GRAPHICS, OVERLAY
59 _8BPP = 0, _15BPP, _16BPP, _24BPP, _32BPP
64 GRAPHICS_MODE = 0, COLOR_KEY, PER_PIXEL_ALPHA, GLOBAL_ALPHA,
75 /* 0h */
76 volatile u32 Thread0Enable; /* 0x0000 */
77 volatile u32 Thread1Enable; /* 0x0004 */
78 volatile u32 Thread0Recover; /* 0x0008 */
79 volatile u32 Thread1Recover; /* 0x000C */
80 volatile u32 Thread0Step; /* 0x0010 */
81 volatile u32 Thread1Step; /* 0x0014 */
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| /kernel/linux/linux-6.6/drivers/video/fbdev/kyro/ |
| D | STG4000Reg.h | 54 NO_LUT = 0, RESERVED, GRAPHICS, OVERLAY
59 _8BPP = 0, _15BPP, _16BPP, _24BPP, _32BPP
64 GRAPHICS_MODE = 0, COLOR_KEY, PER_PIXEL_ALPHA, GLOBAL_ALPHA,
75 /* 0h */
76 volatile u32 Thread0Enable; /* 0x0000 */
77 volatile u32 Thread1Enable; /* 0x0004 */
78 volatile u32 Thread0Recover; /* 0x0008 */
79 volatile u32 Thread1Recover; /* 0x000C */
80 volatile u32 Thread0Step; /* 0x0010 */
81 volatile u32 Thread1Step; /* 0x0014 */
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/ |
| D | a4xx_gpu.c | 30 for (i = 0; i < submit->nr_cmds; i++) { in a4xx_submit()
61 OUT_RING(ring, 0x00000000); in a4xx_submit()
80 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
81 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
82 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
83 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
84 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
86 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
87 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/ |
| D | a4xx_gpu.c | 31 for (i = 0; i < submit->nr_cmds; i++) { in a4xx_submit()
62 OUT_RING(ring, 0x00000000); in a4xx_submit()
81 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
82 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
83 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
84 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
85 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
86 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
87 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
88 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
[all …]
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| /kernel/linux/linux-6.6/include/linux/mfd/ |
| D | motorola-cpcap.h | 17 #define CPCAP_VENDOR_ST 0
21 #define CPCAP_REVISION_MINOR(r) ((r) & 0xf)
23 #define CPCAP_REVISION_1_0 0x08
24 #define CPCAP_REVISION_1_1 0x09
25 #define CPCAP_REVISION_2_0 0x10
26 #define CPCAP_REVISION_2_1 0x11
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
31 #define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
32 #define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
[all …]
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| /kernel/linux/linux-5.10/include/linux/mfd/ |
| D | motorola-cpcap.h | 17 #define CPCAP_VENDOR_ST 0
21 #define CPCAP_REVISION_MINOR(r) ((r) & 0xf)
23 #define CPCAP_REVISION_1_0 0x08
24 #define CPCAP_REVISION_1_1 0x09
25 #define CPCAP_REVISION_2_0 0x10
26 #define CPCAP_REVISION_2_1 0x11
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
31 #define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
32 #define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
[all …]
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