Searched +full:0 +full:x17080 (Results 1 – 10 of 10) sorted by relevance
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interconnect/ |
| D | qcom,sm6350-rpmh.yaml | 66 reg = <0x01500000 0x28000>;
73 reg = <0x01620000 0x17080>;
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| /kernel/linux/linux-6.6/arch/powerpc/perf/ |
| D | power8-events-list.h | 11 EVENT(PM_CYC, 0x0001e)
12 EVENT(PM_GCT_NOSLOT_CYC, 0x100f8)
13 EVENT(PM_CMPLU_STALL, 0x4000a)
14 EVENT(PM_INST_CMPL, 0x00002)
15 EVENT(PM_BRU_FIN, 0x10068)
16 EVENT(PM_BR_MPRED_CMPL, 0x400f6)
19 EVENT(PM_LD_REF_L1, 0x100ee)
21 EVENT(PM_LD_MISS_L1, 0x3e054)
23 EVENT(PM_ST_MISS_L1, 0x300f0)
25 EVENT(PM_L1_PREF, 0x0d8b8)
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/perf/ |
| D | power8-events-list.h | 11 EVENT(PM_CYC, 0x0001e)
12 EVENT(PM_GCT_NOSLOT_CYC, 0x100f8)
13 EVENT(PM_CMPLU_STALL, 0x4000a)
14 EVENT(PM_INST_CMPL, 0x00002)
15 EVENT(PM_BRU_FIN, 0x10068)
16 EVENT(PM_BR_MPRED_CMPL, 0x400f6)
19 EVENT(PM_LD_REF_L1, 0x100ee)
21 EVENT(PM_LD_MISS_L1, 0x3e054)
23 EVENT(PM_ST_MISS_L1, 0x300f0)
25 EVENT(PM_L1_PREF, 0x0d8b8)
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/qcom/ |
| D | gcc-ipq5332.c | 51 .offset = 0x20000,
54 .enable_reg = 0xb000,
55 .enable_mask = BIT(0),
78 .offset = 0x20000,
91 .offset = 0x21000,
94 .enable_reg = 0xb000,
106 .offset = 0x21000,
119 .offset = 0x22000,
122 .enable_reg = 0xb000,
145 .offset = 0x22000,
[all …]
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| D | gcc-ipq9574.c | 55 { P_XO, 0 },
67 .offset = 0x20000,
70 .enable_reg = 0x0b000,
71 .enable_mask = BIT(0),
95 .offset = 0x20000,
109 .offset = 0x22000,
112 .enable_reg = 0x0b000,
124 .offset = 0x22000,
138 .offset = 0x21000,
141 .enable_reg = 0x0b000,
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/ |
| D | sm6350.dtsi | 31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
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| D | sc7180.dtsi | 63 #clock-cells = <0>;
69 #clock-cells = <0>;
75 #size-cells = <0>;
77 cpu0: cpu@0 {
80 reg = <0x0 0x0>;
81 clocks = <&cpufreq_hw 0>;
92 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x100>;
110 clocks = <&cpufreq_hw 0>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/ |
| D | sc7180.dtsi | 60 #clock-cells = <0>;
66 #clock-cells = <0>;
76 reg = <0x0 0x80000000 0x0 0x600000>;
81 reg = <0x0 0x80600000 0x0 0x200000>;
86 reg = <0x0 0x80800000 0x0 0x20000>;
91 reg = <0x0 0x80820000 0x0 0x20000>;
97 reg = <0x0 0x808ff000 0x0 0x1000>;
102 reg = <0x0 0x80900000 0x0 0x200000>;
107 reg = <0x0 0x80b00000 0x0 0x3900000>;
113 reg = <0x0 0x84400000 0x0 0x200000>;
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | other.json | 3 "EventCode": "0x1f05e",
9 "EventCode": "0x2006e",
11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
15 "EventCode": "0x4e05e",
17 …"BriefDescription": "Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 bel…
21 "EventCode": "0x610050",
27 "EventCode": "0x520050",
33 "EventCode": "0x620052",
39 "EventCode": "0x610052",
45 "EventCode": "0x610054",
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | other.json | 3 "EventCode": "0x1f05e",
9 "EventCode": "0x2006e",
11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
15 "EventCode": "0x4e05e",
17 …"BriefDescription": "Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 bel…
21 "EventCode": "0x610050",
27 "EventCode": "0x520050",
33 "EventCode": "0x620052",
39 "EventCode": "0x610052",
45 "EventCode": "0x610054",
[all …]
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