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/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8mm-mx8menlo.dts22 pinctrl-0 = <&pinctrl_led>;
40 pinctrl-0 = <&pinctrl_beeper>;
47 #clock-cells = <0>;
54 #size-cells = <0>;
56 pinctrl-0 = <&pinctrl_ecspi1>;
61 canfd: can@0 {
66 reg = <0>;
73 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
77 spidev@0 {
79 reg = <0>;
[all …]
Dimx8mp-verdin.dtsi25 brightness-levels = <0 45 63 88 119 158 203 255>;
30 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
33 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
39 brightness-levels = <0 45 63 88 119 158 203 255>;
44 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
51 pinctrl-0 = <&pinctrl_gpio_keys>;
56 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
92 pinctrl-0 = <&pinctrl_reg_eth>;
108 pinctrl-0 = <&pinctrl_usb1_vbus>;
120 pinctrl-0 = <&pinctrl_usb2_vbus>;
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/coda/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/chips-media/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/falcon/
Dv1.c38 reg = start | BIT(24) | (secure ? BIT(28) : 0); in nvkm_falcon_v1_load_imem()
39 nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg); in nvkm_falcon_v1_load_imem()
40 for (i = 0; i < size / 4; i++) { in nvkm_falcon_v1_load_imem()
42 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
43 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); in nvkm_falcon_v1_load_imem()
44 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]); in nvkm_falcon_v1_load_imem()
55 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
56 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); in nvkm_falcon_v1_load_imem()
57 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), in nvkm_falcon_v1_load_imem()
62 /* code must be padded to 0x40 words */ in nvkm_falcon_v1_load_imem()
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/
Dpinctrl-rockchip.c53 #define IOMUX_GPIO_ONLY BIT(0)
119 .pull_type[0] = pull0, \
144 .pull_type[0] = pull0, \
209 .pull_type[0] = pull0, \
249 for (i = 0; i < info->ngroups; i++) { in pinctrl_name_to_group()
279 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { in bank_num_to_bank()
318 return 0; in rockchip_get_group_pins()
358 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; in rockchip_dt_node_to_map()
359 new_map[0].data.mux.function = parent->name; in rockchip_dt_node_to_map()
360 new_map[0].data.mux.group = np->name; in rockchip_dt_node_to_map()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/nvmem/
Dmediatek,efuse.yaml22 pattern: "^efuse@[0-9a-f]+$"
55 reg = <0x11c10000 0x1000>;
60 reg = <0x184 0x1>;
61 bits = <0 5>;
64 reg = <0x184 0x2>;
68 reg = <0x185 0x1>;
72 reg = <0x186 0x1>;
73 bits = <0 5>;
76 reg = <0x186 0x2>;
80 reg = <0x187 0x1>;
[all …]
/kernel/linux/linux-5.10/drivers/phy/qualcomm/
Dphy-qcom-qmp.h10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
/kernel/linux/linux-6.6/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-pcs-pcie-v6_20.h10 #define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c
11 #define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018
12 #define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
13 #define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
14 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
15 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
16 #define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c
17 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
18 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184
19 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c
[all …]
Dphy-qcom-qmp-pcs-pcie-v5_20.h10 #define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c
11 #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
12 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
13 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
14 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
15 #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
16 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
17 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
18 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
19 #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
[all …]
Dphy-qcom-qmp-pcs-ufs-v6.h10 #define QPHY_V6_PCS_UFS_PHY_START 0x000
11 #define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V6_PCS_UFS_SW_RESET 0x008
13 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
14 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
15 #define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c
16 #define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
17 #define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
18 #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
19 #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
[all …]
Dphy-qcom-qmp-qserdes-pll.h10 #define QSERDES_PLL_BG_TIMER 0x00c
11 #define QSERDES_PLL_SSC_PER1 0x01c
12 #define QSERDES_PLL_SSC_PER2 0x020
13 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
14 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
15 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
16 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
17 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
18 #define QSERDES_PLL_CLK_ENABLE1 0x040
19 #define QSERDES_PLL_SYS_CLK_CTRL 0x044
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/falcon/
Dv1.c38 reg = start | BIT(24) | (secure ? BIT(28) : 0); in nvkm_falcon_v1_load_imem()
39 nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg); in nvkm_falcon_v1_load_imem()
40 for (i = 0; i < size / 4; i++) { in nvkm_falcon_v1_load_imem()
42 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
43 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); in nvkm_falcon_v1_load_imem()
44 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]); in nvkm_falcon_v1_load_imem()
55 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
56 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); in nvkm_falcon_v1_load_imem()
57 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), in nvkm_falcon_v1_load_imem()
62 /* code must be padded to 0x40 words */ in nvkm_falcon_v1_load_imem()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/omapdrm/dss/
Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/kernel/linux/linux-6.6/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/
Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/
Dbrcm,spi-bcm-qspi.yaml103 reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
105 interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;
115 #address-cells = <0x1>;
116 #size-cells = <0x0>;
118 flash@0 {
119 #size-cells = <0x2>;
120 #address-cells = <0x2>;
122 reg = <0x0>;
123 spi-max-frequency = <0x2625a00>;
132 reg = <0xf0416000 0x180>;
[all …]
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/kernel/linux/linux-6.6/include/dt-bindings/clock/
Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dbrcm,spi-bcm-qspi.txt22 Must be <0>, also as required by generic SPI binding.
89 #address-cells = <0x1>;
90 #size-cells = <0x0>;
92 reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
94 interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
95 interrupt-parent = <0x1c>;
107 m25p80@0 {
108 #size-cells = <0x2>;
109 #address-cells = <0x2>;
111 reg = <0x0>;
[all …]
/kernel/linux/linux-5.10/arch/xtensa/include/asm/
Dmxregs.h20 * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p
21 * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p
22 * 0180 0...0m..m Clear enable specified by mask (m)
23 * 0184 0...0m..m Set enable specified by mask (m)
24 * 0190 0...0x..x 8-bit IPI partition register
30 * 0200 0...0m..m RunStall core 'n'
34 #define MIROUT(irq) (0x000 + (irq))
35 #define MIPICAUSE(cpu) (0x100 + (cpu))
36 #define MIPISET(cause) (0x140 + (cause))
37 #define MIENG 0x180
[all …]
/kernel/linux/linux-6.6/arch/xtensa/include/asm/
Dmxregs.h20 * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p
21 * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p
22 * 0180 0...0m..m Clear enable specified by mask (m)
23 * 0184 0...0m..m Set enable specified by mask (m)
24 * 0190 0...0x..x 8-bit IPI partition register
30 * 0200 0...0m..m RunStall core 'n'
34 #define MIROUT(irq) (0x000 + (irq))
35 #define MIPICAUSE(cpu) (0x100 + (cpu))
36 #define MIPISET(cause) (0x140 + (cause))
37 #define MIENG 0x180
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]

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